xref: /llvm-project/llvm/test/CodeGen/SystemZ/call-zos-vec.ll (revision c17040599666c1f14906a899cabcf545c2c85744) 
1; RUN: llc < %s -mtriple=s390x-ibm-zos -mcpu=z13 | FileCheck %s
2
3; CHECK-LABEL: sum_vecs0
4; CHECK: vag 24,24,25
5define <2 x i64> @sum_vecs0(<2 x i64> %v1, <2 x i64> %v2) {
6entry:
7  %add0 = add <2 x i64> %v1, %v2
8  ret <2 x i64> %add0
9}
10
11; CHECK-LABEL: sum_vecs1
12; CHECK: vaf 1,24,25
13; CHECK: vaf 1,1,26
14; CHECK: vaf 1,1,27
15; CHECK: vaf 1,1,28
16; CHECK: vaf 1,1,29
17; CHECK: vl  0,2304(4),4
18; CHECK: vaf 1,1,30
19; CHECK: vaf 1,1,31
20; CHECK: vaf 24,1,0
21define <4 x i32> @sum_vecs1(<4 x i32> %v1, <4 x i32> %v2, <4 x i32> %v3, <4 x i32> %v4, <4 x i32> %v5, <4 x i32> %v6, <4 x i32> %v7, <4 x i32> %v8, <4 x i32> %v9) {
22entry:
23  %add0 = add <4 x i32> %v1, %v2
24  %add1 = add <4 x i32> %add0, %v3
25  %add2 = add <4 x i32> %add1, %v4
26  %add3 = add <4 x i32> %add2, %v5
27  %add4 = add <4 x i32> %add3, %v6
28  %add5 = add <4 x i32> %add4, %v7
29  %add6 = add <4 x i32> %add5, %v8
30  %add7 = add <4 x i32> %add6, %v9
31  ret <4 x i32> %add7
32}
33
34; Verify that 3 is used for passing integral types if
35; only 24 is used.
36; CHECK-LABEL: call_vecs0
37; CHECK: lgr 3,1
38define i64 @call_vecs0(i64 %n, <2 x i64> %v1) {
39entry:
40  %ret = call i64 (<2 x i64>, i64) @pass_vecs0(<2 x i64> %v1, i64 %n)
41  ret i64 %ret
42}
43
44; Verify that 3 is not allocated for passing integral types
45; if 24 and %f0 are used.
46; CHECK-LABEL: call_vecs1
47; CHECK: vlr 24,25
48; CHECK: stg 1,2200(4)
49define i64 @call_vecs1(i64 %n, <2 x i64> %v1, double %x, <2 x i64> %v2) {
50entry:
51  %ret = call i64 (<2 x i64>, double, i64) @pass_vecs1(<2 x i64> %v2, double %x, i64 %n)
52  ret i64 %ret
53}
54
55; Verify that 3 is not allocated for passing integral types
56; if 24 and 25 are used.
57; CHECK-LABEL: call_vecs2
58; CHECK: mvghi 2208(4),55
59define i64 @call_vecs2(<2 x i64> %v1, <2 x i64> %v2) {
60  %ret = call i64 (<2 x i64>, <2 x i64>, i64) @pass_vecs2(<2 x i64> %v1, <2 x i64> %v2, i64 55)
61  ret i64 %ret
62}
63
64declare i64 @pass_vecs0(<2 x i64> %v1, i64 %n)
65declare i64 @pass_vecs1(<2 x i64> %v1, double %x, i64 %n)
66declare i64 @pass_vecs2(<2 x i64> %v1, <2 x i64> %v2, i64 %n)
67