xref: /llvm-project/llvm/test/CodeGen/SystemZ/atomic-memops.ll (revision 8b8e1adbdecd5f37ebcaa8d4fdf333962f7a0eb7) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
2; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z16 | FileCheck %s
3
4; Sign-extending atomic loads.
5define void @f1(ptr %src, ptr %dst) {
6; CHECK-LABEL: f1:
7; CHECK:       # %bb.0:
8; CHECK-NEXT:    lb %r0, 0(%r2)
9; CHECK-NEXT:    sth %r0, 0(%r3)
10; CHECK-NEXT:    br %r14
11  %b = load atomic i8, ptr %src seq_cst, align 1
12  %s = sext i8 %b to i16
13  store volatile i16 %s, ptr %dst
14  ret void
15}
16
17define void @f2(ptr %src, ptr %dst) {
18; CHECK-LABEL: f2:
19; CHECK:       # %bb.0:
20; CHECK-NEXT:    lb %r0, 0(%r2)
21; CHECK-NEXT:    st %r0, 0(%r3)
22; CHECK-NEXT:    br %r14
23  %b = load atomic i8, ptr %src seq_cst, align 1
24  %s = sext i8 %b to i32
25  store volatile i32 %s, ptr %dst
26  ret void
27}
28
29define void @f3(ptr %src, ptr %dst) {
30; CHECK-LABEL: f3:
31; CHECK:       # %bb.0:
32; CHECK-NEXT:    lgb %r0, 0(%r2)
33; CHECK-NEXT:    stg %r0, 0(%r3)
34; CHECK-NEXT:    br %r14
35  %b = load atomic i8, ptr %src seq_cst, align 1
36  %s = sext i8 %b to i64
37  store volatile i64 %s, ptr %dst
38  ret void
39}
40
41define void @f4(ptr %src, ptr %dst) {
42; CHECK-LABEL: f4:
43; CHECK:       # %bb.0:
44; CHECK-NEXT:    lh %r0, 0(%r2)
45; CHECK-NEXT:    st %r0, 0(%r3)
46; CHECK-NEXT:    br %r14
47  %b = load atomic i16, ptr %src seq_cst, align 2
48  %s = sext i16 %b to i32
49  store volatile i32 %s, ptr %dst
50  ret void
51}
52
53define void @f5(ptr %src, ptr %dst) {
54; CHECK-LABEL: f5:
55; CHECK:       # %bb.0:
56; CHECK-NEXT:    lgh %r0, 0(%r2)
57; CHECK-NEXT:    stg %r0, 0(%r3)
58; CHECK-NEXT:    br %r14
59  %b = load atomic i16, ptr %src seq_cst, align 2
60  %s = sext i16 %b to i64
61  store volatile i64 %s, ptr %dst
62  ret void
63}
64
65define void @f6(ptr %src, ptr %dst) {
66; CHECK-LABEL: f6:
67; CHECK:       # %bb.0:
68; CHECK-NEXT:    lgf %r0, 0(%r2)
69; CHECK-NEXT:    stg %r0, 0(%r3)
70; CHECK-NEXT:    br %r14
71  %b = load atomic i32, ptr %src seq_cst, align 4
72  %s = sext i32 %b to i64
73  store volatile i64 %s, ptr %dst
74  ret void
75}
76
77; Zero-extending atomic loads.
78define void @f7(ptr %src, ptr %dst) {
79; CHECK-LABEL: f7:
80; CHECK:       # %bb.0:
81; CHECK-NEXT:    llc %r0, 0(%r2)
82; CHECK-NEXT:    sth %r0, 0(%r3)
83; CHECK-NEXT:    br %r14
84  %b = load atomic i8, ptr %src seq_cst, align 1
85  %z = zext i8 %b to i16
86  store volatile i16 %z, ptr %dst
87  ret void
88}
89
90define void @f8(ptr %src, ptr %dst) {
91; CHECK-LABEL: f8:
92; CHECK:       # %bb.0:
93; CHECK-NEXT:    llc %r0, 0(%r2)
94; CHECK-NEXT:    st %r0, 0(%r3)
95; CHECK-NEXT:    br %r14
96  %b = load atomic i8, ptr %src seq_cst, align 1
97  %z = zext i8 %b to i32
98  store volatile i32 %z, ptr %dst
99  ret void
100}
101
102define void @f9(ptr %src, ptr %dst) {
103; CHECK-LABEL: f9:
104; CHECK:       # %bb.0:
105; CHECK-NEXT:    llgc %r0, 0(%r2)
106; CHECK-NEXT:    stg %r0, 0(%r3)
107; CHECK-NEXT:    br %r14
108  %b = load atomic i8, ptr %src seq_cst, align 1
109  %z = zext i8 %b to i64
110  store volatile i64 %z, ptr %dst
111  ret void
112}
113
114define void @f10(ptr %src, ptr %dst) {
115; CHECK-LABEL: f10:
116; CHECK:       # %bb.0:
117; CHECK-NEXT:    llh %r0, 0(%r2)
118; CHECK-NEXT:    st %r0, 0(%r3)
119; CHECK-NEXT:    br %r14
120  %b = load atomic i16, ptr %src seq_cst, align 2
121  %z = zext i16 %b to i32
122  store volatile i32 %z, ptr %dst
123  ret void
124}
125
126define void @f11(ptr %src, ptr %dst) {
127; CHECK-LABEL: f11:
128; CHECK:       # %bb.0:
129; CHECK-NEXT:    llgh %r0, 0(%r2)
130; CHECK-NEXT:    stg %r0, 0(%r3)
131; CHECK-NEXT:    br %r14
132  %b = load atomic i16, ptr %src seq_cst, align 2
133  %z = zext i16 %b to i64
134  store volatile i64 %z, ptr %dst
135  ret void
136}
137
138define void @f12(ptr %src, ptr %dst) {
139; CHECK-LABEL: f12:
140; CHECK:       # %bb.0:
141; CHECK-NEXT:    llgf %r0, 0(%r2)
142; CHECK-NEXT:    stg %r0, 0(%r3)
143; CHECK-NEXT:    br %r14
144  %b = load atomic i32, ptr %src seq_cst, align 4
145  %z = zext i32 %b to i64
146  store volatile i64 %z, ptr %dst
147  ret void
148}
149
150; reg/mem
151define i64 @f13(i64 %a, ptr %src) {
152; CHECK-LABEL: f13:
153; CHECK:       # %bb.0:
154; CHECK-NEXT:    ag %r2, 0(%r3)
155; CHECK-NEXT:    br %r14
156  %b = load atomic i64, ptr %src seq_cst, align 8
157  %add = add i64 %a, %b
158  ret i64 %add
159}
160
161; reg/mem op with extension from memory.
162define i64 @f14(i64 %a, ptr %src) {
163; CHECK-LABEL: f14:
164; CHECK:       # %bb.0:
165; CHECK-NEXT:    slgf %r2, 0(%r3)
166; CHECK-NEXT:    br %r14
167  %b = load atomic i32, ptr %src seq_cst, align 4
168  %bext = zext i32 %b to i64
169  %sub = sub i64 %a, %bext
170  ret i64 %sub
171}
172
173define float @f15(float %f1, ptr %ptr, float %acc) {
174; CHECK-LABEL: f15:
175; CHECK:       # %bb.0:
176; CHECK-NEXT:    maeb %f2, %f0, 0(%r2)
177; CHECK-NEXT:    ldr %f0, %f2
178; CHECK-NEXT:    br %r14
179  %f2 = load atomic float, ptr %ptr seq_cst, align 4
180  %res = call float @llvm.fma.f32 (float %f1, float %f2, float %acc)
181  ret float %res
182}
183declare float @llvm.fma.f32(float %f1, float %f2, float %f3)
184
185define double @f15_b(ptr %src) {
186; CHECK-LABEL: f15_b:
187; CHECK:       # %bb.0:
188; CHECK-NEXT:    ldeb %f0, 0(%r2)
189; CHECK-NEXT:    br %r14
190  %V  = load atomic float, ptr %src seq_cst, align 4
191  %Res = fpext float %V to double
192  ret double %Res
193}
194
195define fp128 @f15_c(ptr %src) {
196; CHECK-LABEL: f15_c:
197; CHECK:       # %bb.0:
198; CHECK-NEXT:    lde %f0, 0(%r3)
199; CHECK-NEXT:    ldebr %f0, %f0
200; CHECK-NEXT:    wflld %v0, %f0
201; CHECK-NEXT:    vst %v0, 0(%r2), 3
202; CHECK-NEXT:    br %r14
203  %V  = load atomic float, ptr %src seq_cst, align 4
204  %Res = fpext float %V to fp128
205  ret fp128 %Res
206}
207
208define fp128 @f15_d(ptr %src) {
209; CHECK-LABEL: f15_d:
210; CHECK:       # %bb.0:
211; CHECK-NEXT:    ld %f0, 0(%r3)
212; CHECK-NEXT:    wflld %v0, %f0
213; CHECK-NEXT:    vst %v0, 0(%r2), 3
214; CHECK-NEXT:    br %r14
215  %V  = load atomic double, ptr %src seq_cst, align 8
216  %Res = fpext double %V to fp128
217  ret fp128 %Res
218}
219
220; Do it twice for good measure given the involved DAG combines.
221define void @f16(ptr %src, ptr %dst) {
222; CHECK-LABEL: f16:
223; CHECK:       # %bb.0:
224; CHECK-NEXT:    llgc %r0, 0(%r2)
225; CHECK-NEXT:    lgbr %r1, %r0
226; CHECK-NEXT:    stg %r1, 0(%r3)
227; CHECK-NEXT:    stg %r0, 0(%r3)
228; CHECK-NEXT:    llgc %r0, 0(%r2)
229; CHECK-NEXT:    lgbr %r1, %r0
230; CHECK-NEXT:    stg %r1, 0(%r3)
231; CHECK-NEXT:    stg %r0, 0(%r3)
232; CHECK-NEXT:    br %r14
233  %b = load atomic i8, ptr %src seq_cst, align 1
234  %s = sext i8 %b to i64
235  %z = zext i8 %b to i64
236  store volatile i64 %s, ptr %dst
237  store volatile i64 %z, ptr %dst
238
239  %b2 = load atomic i8, ptr %src seq_cst, align 1
240  %s2 = sext i8 %b2 to i64
241  %z2 = zext i8 %b2 to i64
242  store volatile i64 %s2, ptr %dst
243  store volatile i64 %z2, ptr %dst
244
245  ret void
246}
247
248define void @f16_b(ptr %src, ptr %dst) {
249; CHECK-LABEL: f16_b:
250; CHECK:       # %bb.0:
251; CHECK-NEXT:    lgb %r0, 0(%r2)
252; CHECK-NEXT:    sth %r0, 0(%r3)
253; CHECK-NEXT:    stg %r0, 0(%r3)
254; CHECK-NEXT:    br %r14
255  %b = load atomic i8, ptr %src seq_cst, align 1
256  %s = sext i8 %b to i16
257  store volatile i16 %s, ptr %dst
258
259  %s2 = sext i8 %b to i64
260  store volatile i64 %s2, ptr %dst
261
262  ret void
263}
264
265define void @f16_c(ptr %src, ptr %dst) {
266; CHECK-LABEL: f16_c:
267; CHECK:       # %bb.0:
268; CHECK-NEXT:    llgc %r0, 0(%r2)
269; CHECK-NEXT:    sth %r0, 0(%r3)
270; CHECK-NEXT:    stg %r0, 0(%r3)
271; CHECK-NEXT:    br %r14
272  %b = load atomic i8, ptr %src seq_cst, align 1
273  %z = zext i8 %b to i16
274  store volatile i16 %z, ptr %dst
275
276  %z2 = zext i8 %b to i64
277  store volatile i64 %z2, ptr %dst
278
279  ret void
280}
281
282; Check that two i8 loads use a reg/reg op.
283define i8 @f16_d(ptr %src, ptr %src2) {
284; CHECK-LABEL: f16_d:
285; CHECK:       # %bb.0:
286; CHECK-NEXT:    lb %r2, 0(%r2)
287; CHECK-NEXT:    lb %r0, 0(%r3)
288; CHECK-NEXT:    ar %r2, %r0
289; CHECK-NEXT:    br %r14
290  %b = load atomic i8, ptr %src seq_cst, align 1
291  %b2 = load atomic i8, ptr %src2 seq_cst, align 1
292  %add = add i8 %b, %b2
293  ret i8 %add
294}
295
296; Binary operations on a byte in memory, with an atomic load.
297define void @f17(ptr %ptr) {
298; CHECK-LABEL: f17:
299; CHECK:       # %bb.0:
300; CHECK-NEXT:    ni 0(%r2), 1
301; CHECK-NEXT:    br %r14
302  %val = load atomic i8, ptr %ptr seq_cst, align 1
303  %xor = and i8 %val, -255
304  store i8 %xor, ptr %ptr
305  ret void
306}
307
308define void @f18(ptr %src) {
309; CHECK-LABEL: f18:
310; CHECK:       # %bb.0:
311; CHECK-NEXT:    oiy 4096(%r2), 1
312; CHECK-NEXT:    br %r14
313  %ptr = getelementptr i8, ptr %src, i64 4096
314  %val = load atomic i8, ptr %ptr seq_cst, align 1
315  %xor = or i8 %val, -255
316  store i8 %xor, ptr %ptr
317  ret void
318}
319
320define void @f19(ptr %src) {
321; CHECK-LABEL: f19:
322; CHECK:       # %bb.0:
323; CHECK-NEXT:    xi 4095(%r2), 1
324; CHECK-NEXT:    br %r14
325  %ptr = getelementptr i8, ptr %src, i64 4095
326  %val = load atomic i8, ptr %ptr seq_cst, align 1
327  %xor = xor i8 %val, -255
328  store i8 %xor, ptr %ptr
329  ret void
330}
331
332; TM
333define double @f20(ptr %src, double %a, double %b) {
334; CHECK-LABEL: f20:
335; CHECK:       # %bb.0:
336; CHECK-NEXT:    tm 0(%r2), 1
337; CHECK-NEXT:    je .LBB25_2
338; CHECK-NEXT:  # %bb.1:
339; CHECK-NEXT:    ldr %f2, %f0
340; CHECK-NEXT:  .LBB25_2:
341; CHECK-NEXT:    ldr %f0, %f2
342; CHECK-NEXT:    br %r14
343  %byte = load atomic i8, ptr %src seq_cst, align 1
344  %and = and i8 %byte, 1
345  %cmp = icmp eq i8 %and, 0
346  %res = select i1 %cmp, double %b, double %a
347  ret double %res
348}
349
350; vector load and replicate
351define void @f21(ptr %src, ptr %dst) {
352; CHECK-LABEL: f21:
353; CHECK:       # %bb.0:
354; CHECK-NEXT:    vlrepb %v0, 0(%r2)
355; CHECK-NEXT:    vst %v0, 0(%r3), 3
356; CHECK-NEXT:    br %r14
357  %b = load atomic i8, ptr %src seq_cst, align 1
358  %v = insertelement <16 x i8> undef, i8 %b, i32 1
359  store volatile <16 x i8> %v, ptr %dst
360  ret void
361}
362
363define void @f22(ptr %src, ptr %dst) {
364; CHECK-LABEL: f22:
365; CHECK:       # %bb.0:
366; CHECK-NEXT:    vlreph %v0, 0(%r2)
367; CHECK-NEXT:    vst %v0, 0(%r3), 3
368; CHECK-NEXT:    br %r14
369  %b = load atomic i16, ptr %src seq_cst, align 2
370  %v = insertelement <8 x i16> undef, i16 %b, i32 1
371  store volatile <8 x i16> %v, ptr %dst
372  ret void
373}
374
375define void @f23(ptr %src, ptr %dst) {
376; CHECK-LABEL: f23:
377; CHECK:       # %bb.0:
378; CHECK-NEXT:    vlrepf %v0, 0(%r2)
379; CHECK-NEXT:    vst %v0, 0(%r3), 3
380; CHECK-NEXT:    br %r14
381  %b = load atomic i32, ptr %src seq_cst, align 4
382  %v = insertelement <4 x i32> undef, i32 %b, i32 2
383  store volatile <4 x i32> %v, ptr %dst
384  ret void
385}
386
387define void @f24(ptr %src, ptr %dst) {
388; CHECK-LABEL: f24:
389; CHECK:       # %bb.0:
390; CHECK-NEXT:    vlrepg %v0, 0(%r2)
391; CHECK-NEXT:    vst %v0, 0(%r3), 3
392; CHECK-NEXT:    br %r14
393  %b = load atomic i64, ptr %src seq_cst, align 8
394  %v = insertelement <2 x i64> undef, i64 %b, i32 0
395  store volatile <2 x i64> %v, ptr %dst
396  ret void
397}
398
399define void @f25(ptr %src, ptr %dst) {
400; CHECK-LABEL: f25:
401; CHECK:       # %bb.0:
402; CHECK-NEXT:    vlrepf %v0, 0(%r2)
403; CHECK-NEXT:    vst %v0, 0(%r3), 3
404; CHECK-NEXT:    br %r14
405  %b = load atomic float, ptr %src seq_cst, align 4
406  %v = insertelement <4 x float> undef, float %b, i32 1
407  store volatile <4 x float> %v, ptr %dst
408  ret void
409}
410
411; Do *not* use vlrep for an extending load.
412define <4 x i32> @f25_c(ptr %ptr) {
413; CHECK-LABEL: f25_c:
414; CHECK:       # %bb.0:
415; CHECK-NEXT:    lb %r0, 0(%r2)
416; CHECK-NEXT:    vlvgp %v0, %r0, %r0
417; CHECK-NEXT:    vrepf %v24, %v0, 1
418; CHECK-NEXT:    br %r14
419  %L = load atomic i8, ptr %ptr seq_cst, align 4
420  %S = sext i8 %L to i32
421  %val = insertelement <4 x i32> undef, i32 %S, i32 0
422  %ret = shufflevector <4 x i32> %val, <4 x i32> undef,
423                       <4 x i32> zeroinitializer
424  ret <4 x i32> %ret
425}
426
427; Do *not* use vlrep if there is another scalar use.
428define <4 x i32> @f25_d(ptr %ptr, ptr %dst) {
429; CHECK-LABEL: f25_d:
430; CHECK:       # %bb.0:
431; CHECK-NEXT:    l %r0, 0(%r2)
432; CHECK-NEXT:    vlvgp %v0, %r0, %r0
433; CHECK-NEXT:    vrepf %v24, %v0, 1
434; CHECK-NEXT:    st %r0, 0(%r3)
435; CHECK-NEXT:    br %r14
436  %L = load atomic i32, ptr %ptr seq_cst, align 4
437  store i32 %L, ptr %dst, align 4
438  %val = insertelement <4 x i32> undef, i32 %L, i32 0
439  %ret = shufflevector <4 x i32> %val, <4 x i32> undef,
440                       <4 x i32> zeroinitializer
441  ret <4 x i32> %ret
442}
443
444define void @f26(ptr %src, ptr %dst) {
445; CHECK-LABEL: f26:
446; CHECK:       # %bb.0:
447; CHECK-NEXT:    vlrepg %v0, 0(%r2)
448; CHECK-NEXT:    vst %v0, 0(%r3), 3
449; CHECK-NEXT:    br %r14
450  %b = load atomic double, ptr %src seq_cst, align 8
451  %v = insertelement <2 x double> undef, double %b, i32 0
452  store volatile <2 x double> %v, ptr %dst
453  ret void
454}
455
456; Vector Load logical element and zero.
457define <16 x i8> @f27(ptr %ptr) {
458; CHECK-LABEL: f27:
459; CHECK:       # %bb.0:
460; CHECK-NEXT:    vllezb %v24, 0(%r2)
461; CHECK-NEXT:    br %r14
462  %val = load atomic i8, ptr %ptr seq_cst, align 1
463  %ret = insertelement <16 x i8> zeroinitializer, i8 %val, i32 7
464  ret <16 x i8> %ret
465}
466
467define <8 x i16> @f28(ptr %ptr) {
468; CHECK-LABEL: f28:
469; CHECK:       # %bb.0:
470; CHECK-NEXT:    vllezh %v24, 0(%r2)
471; CHECK-NEXT:    br %r14
472  %val = load atomic i16, ptr %ptr seq_cst, align 2
473  %ret = insertelement <8 x i16> zeroinitializer, i16 %val, i32 3
474  ret <8 x i16> %ret
475}
476
477define <4 x i32> @f29(ptr %ptr) {
478; CHECK-LABEL: f29:
479; CHECK:       # %bb.0:
480; CHECK-NEXT:    vllezf %v24, 0(%r2)
481; CHECK-NEXT:    br %r14
482  %val = load atomic i32, ptr %ptr seq_cst, align 4
483  %ret = insertelement <4 x i32> zeroinitializer, i32 %val, i32 1
484  ret <4 x i32> %ret
485}
486
487define <2 x i64> @f30(ptr %ptr) {
488; CHECK-LABEL: f30:
489; CHECK:       # %bb.0:
490; CHECK-NEXT:    vllezg %v24, 0(%r2)
491; CHECK-NEXT:    br %r14
492  %val = load atomic i64, ptr %ptr seq_cst, align 8
493  %ret = insertelement <2 x i64> zeroinitializer, i64 %val, i32 0
494  ret <2 x i64> %ret
495}
496
497define <4 x i32> @f31(ptr %ptr) {
498; CHECK-LABEL: f31:
499; CHECK:       # %bb.0:
500; CHECK-NEXT:    vllezlf %v24, 0(%r2)
501; CHECK-NEXT:    br %r14
502  %val = load atomic i32, ptr %ptr seq_cst, align 4
503  %ret = insertelement <4 x i32> zeroinitializer, i32 %val, i32 0
504  ret <4 x i32> %ret
505}
506
507define <4 x float> @f32(ptr %ptr) {
508; CHECK-LABEL: f32:
509; CHECK:       # %bb.0:
510; CHECK-NEXT:    vllezlf %v24, 0(%r2)
511; CHECK-NEXT:    br %r14
512  %val = load atomic float, ptr %ptr seq_cst, align 4
513  %ret = insertelement <4 x float> zeroinitializer, float %val, i32 0
514  ret <4 x float> %ret
515}
516
517; Vector Load element.
518define <16 x i8> @f33(<16 x i8> %val, ptr %ptr) {
519; CHECK-LABEL: f33:
520; CHECK:       # %bb.0:
521; CHECK-NEXT:    vleb %v24, 0(%r2), 0
522; CHECK-NEXT:    br %r14
523  %element = load atomic i8, ptr %ptr seq_cst, align 1
524  %ret = insertelement <16 x i8> %val, i8 %element, i32 0
525  ret <16 x i8> %ret
526}
527
528define <8 x i16> @f34(<8 x i16> %val, ptr %ptr) {
529; CHECK-LABEL: f34:
530; CHECK:       # %bb.0:
531; CHECK-NEXT:    vleh %v24, 0(%r2), 0
532; CHECK-NEXT:    br %r14
533  %element = load atomic i16, ptr %ptr seq_cst, align 2
534  %ret = insertelement <8 x i16> %val, i16 %element, i32 0
535  ret <8 x i16> %ret
536}
537
538define <4 x i32> @f35(<4 x i32> %val, ptr %ptr) {
539; CHECK-LABEL: f35:
540; CHECK:       # %bb.0:
541; CHECK-NEXT:    vlef %v24, 0(%r2), 0
542; CHECK-NEXT:    br %r14
543  %element = load atomic i32, ptr %ptr seq_cst, align 4
544  %ret = insertelement <4 x i32> %val, i32 %element, i32 0
545  ret <4 x i32> %ret
546}
547
548define <2 x i64> @f36(<2 x i64> %val, ptr %ptr) {
549; CHECK-LABEL: f36:
550; CHECK:       # %bb.0:
551; CHECK-NEXT:    vleg %v24, 0(%r2), 0
552; CHECK-NEXT:    br %r14
553  %element = load atomic i64, ptr %ptr seq_cst, align 8
554  %ret = insertelement <2 x i64> %val, i64 %element, i32 0
555  ret <2 x i64> %ret
556}
557
558; Test operation on memory involving atomic load and store.
559define void @f39(ptr %ptr) {
560; CHECK-LABEL: f39:
561; CHECK:       # %bb.0:
562; CHECK-NEXT:    oi 0(%r2), 1
563; CHECK-NEXT:    bcr 14, %r0
564; CHECK-NEXT:    br %r14
565  %val = load atomic i8, ptr %ptr seq_cst, align 1
566  %or = or i8 %val, -255
567  store atomic i8 %or, ptr %ptr seq_cst, align 1
568  ret void
569}
570
571; Some atomic stores of immediates.
572define void @f40(ptr %ptr) {
573; CHECK-LABEL: f40:
574; CHECK:       # %bb.0:
575; CHECK-NEXT:    mvi 0(%r2), 128
576; CHECK-NEXT:    bcr 14, %r0
577; CHECK-NEXT:    br %r14
578  store atomic i8 128, ptr %ptr seq_cst, align 1
579  ret void
580}
581
582define void @f41(ptr %ptr) {
583; CHECK-LABEL: f41:
584; CHECK:       # %bb.0:
585; CHECK-NEXT:    mvhi 0(%r2), -1
586; CHECK-NEXT:    bcr 14, %r0
587; CHECK-NEXT:    br %r14
588  store atomic i32 4294967295, ptr %ptr seq_cst, align 4
589  ret void
590}
591
592define void @f42(ptr %ptr) {
593; CHECK-LABEL: f42:
594; CHECK:       # %bb.0:
595; CHECK-NEXT:    mvhi 0(%r2), -1
596; CHECK-NEXT:    bcr 14, %r0
597; CHECK-NEXT:    br %r14
598  store atomic i32 4294967295, ptr %ptr seq_cst, align 4
599  ret void
600}
601
602define void @f43(ptr %ptr) {
603; CHECK-LABEL: f43:
604; CHECK:       # %bb.0:
605; CHECK-NEXT:    llihl %r0, 255
606; CHECK-NEXT:    oilf %r0, 4294967295
607; CHECK-NEXT:    stg %r0, 0(%r2)
608; CHECK-NEXT:    bcr 14, %r0
609; CHECK-NEXT:    br %r14
610  store atomic i64 1099511627775, ptr %ptr seq_cst, align 8
611  ret void
612}
613
614define void @f44(ptr %ptr) {
615; CHECK-LABEL: f44:
616; CHECK:       # %bb.0:
617; CHECK-NEXT:    larl %r1, .LCPI49_0
618; CHECK-NEXT:    ld %f0, 0(%r1)
619; CHECK-NEXT:    std %f0, 0(%r2)
620; CHECK-NEXT:    bcr 14, %r0
621; CHECK-NEXT:    br %r14
622  store atomic double 0x3ff0000020000000, ptr %ptr seq_cst, align 8
623  ret void
624}
625
626; Vector Store Element.
627define void @f45(<16 x i8> %val, ptr %ptr) {
628; CHECK-LABEL: f45:
629; CHECK:       # %bb.0:
630; CHECK-NEXT:    vsteb %v24, 0(%r2), 0
631; CHECK-NEXT:    bcr 14, %r0
632; CHECK-NEXT:    br %r14
633  %element = extractelement <16 x i8> %val, i32 0
634  store atomic i8 %element, ptr %ptr seq_cst, align 1
635  ret void
636}
637
638define void @f46(<8 x i16> %val, ptr %base) {
639; CHECK-LABEL: f46:
640; CHECK:       # %bb.0:
641; CHECK-NEXT:    vsteh %v24, 4094(%r2), 5
642; CHECK-NEXT:    bcr 14, %r0
643; CHECK-NEXT:    br %r14
644  %ptr = getelementptr i16, ptr %base, i32 2047
645  %element = extractelement <8 x i16> %val, i32 5
646  store atomic i16 %element, ptr %ptr seq_cst, align 2
647  ret void
648}
649
650define void @f47(<4 x i32> %val, ptr %ptr) {
651; CHECK-LABEL: f47:
652; CHECK:       # %bb.0:
653; CHECK-NEXT:    vstef %v24, 0(%r2), 3
654; CHECK-NEXT:    bcr 14, %r0
655; CHECK-NEXT:    br %r14
656  %element = extractelement <4 x i32> %val, i32 3
657  store atomic i32 %element, ptr %ptr seq_cst, align 4
658  ret void
659}
660
661define void @f48(<2 x i64> %val, ptr %ptr) {
662; CHECK-LABEL: f48:
663; CHECK:       # %bb.0:
664; CHECK-NEXT:    vsteg %v24, 0(%r2), 1
665; CHECK-NEXT:    bcr 14, %r0
666; CHECK-NEXT:    br %r14
667  %element = extractelement <2 x i64> %val, i32 1
668  store atomic i64 %element, ptr %ptr seq_cst, align 8
669  ret void
670}
671
672define void @f49(<4 x float> %val, ptr %ptr) {
673; CHECK-LABEL: f49:
674; CHECK:       # %bb.0:
675; CHECK-NEXT:    vstef %v24, 0(%r2), 0
676; CHECK-NEXT:    bcr 14, %r0
677; CHECK-NEXT:    br %r14
678  %element = extractelement <4 x float> %val, i32 0
679  store atomic float %element, ptr %ptr seq_cst, align 4
680  ret void
681}
682
683define void @f50(<2 x double> %val, ptr %ptr) {
684; CHECK-LABEL: f50:
685; CHECK:       # %bb.0:
686; CHECK-NEXT:    vsteg %v24, 0(%r2), 1
687; CHECK-NEXT:    bcr 14, %r0
688; CHECK-NEXT:    br %r14
689  %element = extractelement <2 x double> %val, i32 1
690  store atomic double %element, ptr %ptr seq_cst, align 8
691  ret void
692}
693
694define void @f51(ptr %src, ptr %dst) {
695; CHECK-LABEL: f51:
696; CHECK:       # %bb.0:
697; CHECK-NEXT:    lpq %r0, 0(%r2)
698; CHECK-NEXT:    vlvgp %v0, %r0, %r1
699; CHECK-NEXT:    vgmf %v1, 2, 8
700; CHECK-NEXT:    aebr %f0, %f1
701; CHECK-NEXT:    ste %f0, 0(%r3)
702; CHECK-NEXT:    bcr 14, %r0
703; CHECK-NEXT:    br %r14
704  %atomic-load = load atomic i128, ptr %src seq_cst, align 16
705  %b0 = bitcast i128 %atomic-load to <4 x float>
706  %vecext = extractelement <4 x float> %b0, i64 0
707  %add = fadd float %vecext, 1.000000e+00
708  store atomic float %add, ptr %dst seq_cst, align 4
709  ret void
710}
711
712define void @f52(ptr %src, ptr %dst) {
713; CHECK-LABEL: f52:
714; CHECK:       # %bb.0:
715; CHECK-NEXT:    lpq %r0, 0(%r2)
716; CHECK-NEXT:    vlvgp %v0, %r0, %r1
717; CHECK-NEXT:    vgmg %v1, 2, 11
718; CHECK-NEXT:    adbr %f0, %f1
719; CHECK-NEXT:    std %f0, 0(%r3)
720; CHECK-NEXT:    bcr 14, %r0
721; CHECK-NEXT:    br %r14
722  %atomic-load = load atomic i128, ptr %src seq_cst, align 16
723  %b0 = bitcast i128 %atomic-load to <2 x double>
724  %vecext = extractelement <2 x double> %b0, i64 0
725  %add = fadd double %vecext, 1.000000e+00
726  store atomic double %add, ptr %dst seq_cst, align 8
727  ret void
728}
729
730define void @fun58(ptr %ptr, i64 %arg) {
731; CHECK-LABEL: fun58:
732; CHECK:       # %bb.0:
733; CHECK-NEXT:    st %r3, 0(%r2)
734; CHECK-NEXT:    bcr 14, %r0
735; CHECK-NEXT:    br %r14
736  %res = trunc i64 %arg to i32
737  store atomic i32 %res, ptr %ptr seq_cst, align 4
738  ret void
739}
740