xref: /llvm-project/llvm/test/CodeGen/SystemZ/atomic-load-08.ll (revision 0a0cac6dbd0ef67eb473f85a968bbf4ebea5220d)
1; Test long double atomic loads - via i128.
2;
3; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck -check-prefixes=CHECK,BASE %s
4; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck -check-prefixes=CHECK,Z13 %s
5; RUN: llc < %s -mtriple=s390x-linux-gnu -mattr=+soft-float | FileCheck -check-prefixes=SOFTFP %s
6
7define void @f1(ptr %ret, ptr %src) {
8; CHECK-LABEL: f1:
9; CHECK:       # %bb.0:
10; CHECK-NEXT:    lpq %r0, 0(%r3)
11; CHECK-NEXT:    stg %r1, 8(%r2)
12; CHECK-NEXT:    stg %r0, 0(%r2)
13; CHECK-NEXT:    br %r14
14
15; SOFTFP-LABEL: f1:
16; SOFTFP:       # %bb.0:
17; SOFTFP-NEXT:    lpq %r0, 0(%r3)
18; SOFTFP-NEXT:    stg %r1, 8(%r2)
19; SOFTFP-NEXT:    stg %r0, 0(%r2)
20; SOFTFP-NEXT:    br %r14
21  %val = load atomic fp128, ptr %src seq_cst, align 16
22  store fp128 %val, ptr %ret, align 8
23  ret void
24}
25
26define void @f1_fpuse(ptr %ret, ptr %src) {
27; CHECK-LABEL: f1_fpuse:
28; CHECK:       # %bb.0:
29; CHECK-NEXT:	lpq	%r0, 0(%r3)
30
31; BASE-NEXT: ldgr	%f0, %r0
32; BASE-NEXT: ldgr	%f2, %r1
33
34; Z13-NEXT: vlvgp %v0, %r0, %r1
35; Z13-NEXT: vrepg %v2, %v0, 1
36
37; CHECK-NEXT:	axbr	%f0, %f0
38; CHECK-NEXT:	std	%f0, 0(%r2)
39; CHECK-NEXT:	std	%f2, 8(%r2)
40; CHECK-NEXT:	br	%r14
41
42
43; SOFTFP-LABEL: f1_fpuse:
44; SOFTFP: stmg	%r13, %r15, 104(%r15)
45; SOFTFP: aghi	%r15, -208
46; SOFTFP:	lpq	%r0, 0(%r3)
47; SOFTFP-NEXT: lgr	%r13, %r2
48; SOFTFP-NEXT: stg	%r1, 168(%r15)
49; SOFTFP-NEXT: stg	%r0, 160(%r15)
50; SOFTFP-NEXT: stg	%r1, 184(%r15)
51; SOFTFP-NEXT: la	%r2, 192(%r15)
52; SOFTFP-NEXT: la	%r3, 176(%r15)
53; SOFTFP-NEXT: la	%r4, 160(%r15)
54; SOFTFP-NEXT: stg	%r0, 176(%r15)
55; SOFTFP-NEXT: brasl	%r14, __addtf3@PLT
56; SOFTFP-NEXT: lg	%r0, 200(%r15)
57; SOFTFP-NEXT: lg	%r1, 192(%r15)
58; SOFTFP-NEXT: stg	%r0, 8(%r13)
59; SOFTFP-NEXT: stg	%r1, 0(%r13)
60; SOFTFP-NEXT: lmg	%r13, %r15, 312(%r15)
61; SOFTFP-NEXT: br	%r14
62  %val = load atomic fp128, ptr %src seq_cst, align 16
63  %use = fadd fp128 %val, %val
64  store fp128 %use, ptr %ret, align 8
65  ret void
66}
67
68define void @f2(ptr %ret, ptr %src) {
69; CHECK-LABEL: f2:
70; CHECK: brasl %r14, __atomic_load@PLT
71  %val = load atomic fp128, ptr %src seq_cst, align 8
72  store fp128 %val, ptr %ret, align 8
73  ret void
74}
75
76define void @f2_fpuse(ptr %ret, ptr %src) {
77; CHECK-LABEL: f2_fpuse:
78; CHECK: brasl %r14, __atomic_load@PLT
79; CHECK-NEXT:   ld	%f0, 160(%r15)
80; CHECK-NEXT:	ld	%f2, 168(%r15)
81; CHECK-NEXT:	axbr	%f0, %f0
82; CHECK-NEXT:	std	%f0, 0(%r13)
83; CHECK-NEXT:	std	%f2, 8(%r13)
84; CHECK-NEXT:	lmg	%r13, %r15, 280(%r15)
85; CHECK-NEXT:	br	%r14
86  %val = load atomic fp128, ptr %src seq_cst, align 8
87  %use = fadd fp128 %val, %val
88  store fp128 %use, ptr %ret, align 8
89  ret void
90}
91