1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 2; Test 128-bit AND / AND-NOT in vector registers on z13 3; 4; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s 5 6; And. 7define i128 @f1(i128 %a, i128 %b) { 8; CHECK-LABEL: f1: 9; CHECK: # %bb.0: 10; CHECK-NEXT: vl %v0, 0(%r4), 3 11; CHECK-NEXT: vl %v1, 0(%r3), 3 12; CHECK-NEXT: vn %v0, %v1, %v0 13; CHECK-NEXT: vst %v0, 0(%r2), 3 14; CHECK-NEXT: br %r14 15 %res = and i128 %a, %b 16 ret i128 %res 17} 18 19; And with complement. 20define i128 @f2(i128 %a, i128 %b) { 21; CHECK-LABEL: f2: 22; CHECK: # %bb.0: 23; CHECK-NEXT: vl %v0, 0(%r4), 3 24; CHECK-NEXT: vl %v1, 0(%r3), 3 25; CHECK-NEXT: vnc %v0, %v1, %v0 26; CHECK-NEXT: vst %v0, 0(%r2), 3 27; CHECK-NEXT: br %r14 28 %notb = xor i128 %b, -1 29 %res = and i128 %a, %notb 30 ret i128 %res 31} 32