1; RUN: llc -O0 -verify-machineinstrs -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-HLSL 2; RUN: llc -O0 -verify-machineinstrs -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-OCL 3; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %} 4; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %} 5; Make sure spirv operation function calls for all are generated. 6 7; CHECK-HLSL-DAG: OpMemoryModel Logical GLSL450 8; CHECK-OCL-DAG: OpMemoryModel Physical32 OpenCL 9; CHECK-DAG: OpName %[[#all_bool_arg:]] "a" 10; CHECK-DAG: %[[#int_64:]] = OpTypeInt 64 0 11; CHECK-DAG: %[[#bool:]] = OpTypeBool 12; CHECK-DAG: %[[#int_32:]] = OpTypeInt 32 0 13; CHECK-DAG: %[[#int_16:]] = OpTypeInt 16 0 14; CHECK-DAG: %[[#float_64:]] = OpTypeFloat 64 15; CHECK-DAG: %[[#float_32:]] = OpTypeFloat 32 16; CHECK-DAG: %[[#float_16:]] = OpTypeFloat 16 17; CHECK-DAG: %[[#vec4_bool:]] = OpTypeVector %[[#bool]] 4 18; CHECK-DAG: %[[#vec4_16:]] = OpTypeVector %[[#int_16]] 4 19; CHECK-DAG: %[[#vec4_32:]] = OpTypeVector %[[#int_32]] 4 20; CHECK-DAG: %[[#vec4_64:]] = OpTypeVector %[[#int_64]] 4 21; CHECK-DAG: %[[#vec4_float_16:]] = OpTypeVector %[[#float_16]] 4 22; CHECK-DAG: %[[#vec4_float_32:]] = OpTypeVector %[[#float_32]] 4 23; CHECK-DAG: %[[#vec4_float_64:]] = OpTypeVector %[[#float_64]] 4 24 25; CHECK-HLSL-DAG: %[[#const_i64_0:]] = OpConstant %[[#int_64]] 0 26; CHECK-HLSL-DAG: %[[#const_i32_0:]] = OpConstant %[[#int_32]] 0 27; CHECK-HLSL-DAG: %[[#const_i16_0:]] = OpConstant %[[#int_16]] 0 28; CHECK-HLSL-DAG: %[[#const_f64_0:]] = OpConstant %[[#float_64]] 0 29; CHECK-HLSL-DAG: %[[#const_f32_0:]] = OpConstant %[[#float_32]] 0 30; CHECK-HLSL-DAG: %[[#const_f16_0:]] = OpConstant %[[#float_16]] 0 31; CHECK-HLSL-DAG: %[[#vec4_const_zeros_i16:]] = OpConstantComposite %[[#vec4_16]] %[[#const_i16_0]] %[[#const_i16_0]] %[[#const_i16_0]] %[[#const_i16_0]] 32; CHECK-HLSL-DAG: %[[#vec4_const_zeros_i32:]] = OpConstantComposite %[[#vec4_32]] %[[#const_i32_0]] %[[#const_i32_0]] %[[#const_i32_0]] %[[#const_i32_0]] 33; CHECK-HLSL-DAG: %[[#vec4_const_zeros_i64:]] = OpConstantComposite %[[#vec4_64]] %[[#const_i64_0]] %[[#const_i64_0]] %[[#const_i64_0]] %[[#const_i64_0]] 34; CHECK-HLSL-DAG: %[[#vec4_const_zeros_f16:]] = OpConstantComposite %[[#vec4_float_16]] %[[#const_f16_0]] %[[#const_f16_0]] %[[#const_f16_0]] %[[#const_f16_0]] 35; CHECK-HLSL-DAG: %[[#vec4_const_zeros_f32:]] = OpConstantComposite %[[#vec4_float_32]] %[[#const_f32_0]] %[[#const_f32_0]] %[[#const_f32_0]] %[[#const_f32_0]] 36; CHECK-HLSL-DAG: %[[#vec4_const_zeros_f64:]] = OpConstantComposite %[[#vec4_float_64]] %[[#const_f64_0]] %[[#const_f64_0]] %[[#const_f64_0]] %[[#const_f64_0]] 37 38; CHECK-OCL-DAG: %[[#const_i64_0:]] = OpConstantNull %[[#int_64]] 39; CHECK-OCL-DAG: %[[#const_i32_0:]] = OpConstantNull %[[#int_32]] 40; CHECK-OCL-DAG: %[[#const_i16_0:]] = OpConstantNull %[[#int_16]] 41; CHECK-OCL-DAG: %[[#const_f64_0:]] = OpConstantNull %[[#float_64]] 42; CHECK-OCL-DAG: %[[#const_f32_0:]] = OpConstantNull %[[#float_32]] 43; CHECK-OCL-DAG: %[[#const_f16_0:]] = OpConstantNull %[[#float_16]] 44; CHECK-OCL-DAG: %[[#vec4_const_zeros_i16:]] = OpConstantNull %[[#vec4_16]] 45; CHECK-OCL-DAG: %[[#vec4_const_zeros_i32:]] = OpConstantNull %[[#vec4_32]] 46; CHECK-OCL-DAG: %[[#vec4_const_zeros_i64:]] = OpConstantNull %[[#vec4_64]] 47; CHECK-OCL-DAG: %[[#vec4_const_zeros_f16:]] = OpConstantNull %[[#vec4_float_16]] 48; CHECK-OCL-DAG: %[[#vec4_const_zeros_f32:]] = OpConstantNull %[[#vec4_float_32]] 49; CHECK-OCL-DAG: %[[#vec4_const_zeros_f64:]] = OpConstantNull %[[#vec4_float_64]] 50 51define noundef i1 @all_int64_t(i64 noundef %p0) { 52entry: 53 ; CHECK: %[[#arg0:]] = OpFunctionParameter %[[#]] 54 ; CHECK: %[[#]] = OpINotEqual %[[#bool]] %[[#arg0]] %[[#const_i64_0]] 55 %hlsl.all = call i1 @llvm.spv.all.i64(i64 %p0) 56 ret i1 %hlsl.all 57} 58 59 60define noundef i1 @all_int(i32 noundef %p0) { 61entry: 62 ; CHECK: %[[#arg0:]] = OpFunctionParameter %[[#]] 63 ; CHECK: %[[#]] = OpINotEqual %[[#bool]] %[[#arg0]] %[[#const_i32_0]] 64 %hlsl.all = call i1 @llvm.spv.all.i32(i32 %p0) 65 ret i1 %hlsl.all 66} 67 68 69define noundef i1 @all_int16_t(i16 noundef %p0) { 70entry: 71 ; CHECK: %[[#arg0:]] = OpFunctionParameter %[[#]] 72 ; CHECK: %[[#]] = OpINotEqual %[[#bool]] %[[#arg0]] %[[#const_i16_0]] 73 %hlsl.all = call i1 @llvm.spv.all.i16(i16 %p0) 74 ret i1 %hlsl.all 75} 76 77define noundef i1 @all_double(double noundef %p0) { 78entry: 79 ; CHECK: %[[#arg0:]] = OpFunctionParameter %[[#]] 80 ; CHECK: %[[#]] = OpFOrdNotEqual %[[#bool]] %[[#arg0]] %[[#const_f64_0]] 81 %hlsl.all = call i1 @llvm.spv.all.f64(double %p0) 82 ret i1 %hlsl.all 83} 84 85 86define noundef i1 @all_float(float noundef %p0) { 87entry: 88 ; CHECK: %[[#arg0:]] = OpFunctionParameter %[[#]] 89 ; CHECK: %[[#]] = OpFOrdNotEqual %[[#bool]] %[[#arg0]] %[[#const_f32_0]] 90 %hlsl.all = call i1 @llvm.spv.all.f32(float %p0) 91 ret i1 %hlsl.all 92} 93 94 95define noundef i1 @all_half(half noundef %p0) { 96entry: 97 ; CHECK: %[[#arg0:]] = OpFunctionParameter %[[#]] 98 ; CHECK: %[[#]] = OpFOrdNotEqual %[[#bool]] %[[#arg0]] %[[#const_f16_0]] 99 %hlsl.all = call i1 @llvm.spv.all.f16(half %p0) 100 ret i1 %hlsl.all 101} 102 103 104define noundef i1 @all_bool4(<4 x i1> noundef %p0) { 105entry: 106 ; CHECK: %[[#arg0:]] = OpFunctionParameter %[[#vec4_bool]] 107 ; CHECK: %[[#]] = OpAll %[[#bool]] %[[#arg0]] 108 %hlsl.all = call i1 @llvm.spv.all.v4i1(<4 x i1> %p0) 109 ret i1 %hlsl.all 110} 111 112define noundef i1 @all_short4(<4 x i16> noundef %p0) { 113entry: 114 ; CHECK: %[[#arg0:]] = OpFunctionParameter %[[#]] 115 ; CHECK: %[[#shortVecNotEq:]] = OpINotEqual %[[#vec4_bool]] %[[#arg0]] %[[#vec4_const_zeros_i16]] 116 ; CHECK: %[[#]] = OpAll %[[#bool]] %[[#shortVecNotEq]] 117 %hlsl.all = call i1 @llvm.spv.all.v4i16(<4 x i16> %p0) 118 ret i1 %hlsl.all 119} 120 121define noundef i1 @all_int4(<4 x i32> noundef %p0) { 122entry: 123 ; CHECK: %[[#arg0:]] = OpFunctionParameter %[[#]] 124 ; CHECK: %[[#i32VecNotEq:]] = OpINotEqual %[[#vec4_bool]] %[[#arg0]] %[[#vec4_const_zeros_i32]] 125 ; CHECK: %[[#]] = OpAll %[[#bool]] %[[#i32VecNotEq]] 126 %hlsl.all = call i1 @llvm.spv.all.v4i32(<4 x i32> %p0) 127 ret i1 %hlsl.all 128} 129 130define noundef i1 @all_int64_t4(<4 x i64> noundef %p0) { 131entry: 132 ; CHECK: %[[#arg0:]] = OpFunctionParameter %[[#]] 133 ; CHECK: %[[#i64VecNotEq:]] = OpINotEqual %[[#vec4_bool]] %[[#arg0]] %[[#vec4_const_zeros_i64]] 134 ; CHECK: %[[#]] = OpAll %[[#bool]] %[[#i64VecNotEq]] 135 %hlsl.all = call i1 @llvm.spv.all.v4i64(<4 x i64> %p0) 136 ret i1 %hlsl.all 137} 138 139define noundef i1 @all_half4(<4 x half> noundef %p0) { 140entry: 141 ; CHECK: %[[#arg0:]] = OpFunctionParameter %[[#]] 142 ; CHECK: %[[#f16VecNotEq:]] = OpFOrdNotEqual %[[#vec4_bool]] %[[#arg0]] %[[#vec4_const_zeros_f16]] 143 ; CHECK: %[[#]] = OpAll %[[#bool]] %[[#f16VecNotEq]] 144 %hlsl.all = call i1 @llvm.spv.all.v4f16(<4 x half> %p0) 145 ret i1 %hlsl.all 146} 147 148define noundef i1 @all_float4(<4 x float> noundef %p0) { 149entry: 150 ; CHECK: %[[#arg0:]] = OpFunctionParameter %[[#]] 151 ; CHECK: %[[#f32VecNotEq:]] = OpFOrdNotEqual %[[#vec4_bool]] %[[#arg0]] %[[#vec4_const_zeros_f32]] 152 ; CHECK: %[[#]] = OpAll %[[#bool]] %[[#f32VecNotEq]] 153 %hlsl.all = call i1 @llvm.spv.all.v4f32(<4 x float> %p0) 154 ret i1 %hlsl.all 155} 156 157define noundef i1 @all_double4(<4 x double> noundef %p0) { 158entry: 159 ; CHECK: %[[#arg0:]] = OpFunctionParameter %[[#]] 160 ; CHECK: %[[#f64VecNotEq:]] = OpFOrdNotEqual %[[#vec4_bool]] %[[#arg0]] %[[#vec4_const_zeros_f64]] 161 ; CHECK: %[[#]] = OpAll %[[#bool]] %[[#f64VecNotEq]] 162 %hlsl.all = call i1 @llvm.spv.all.v4f64(<4 x double> %p0) 163 ret i1 %hlsl.all 164} 165 166define noundef i1 @all_bool(i1 noundef %a) { 167entry: 168 ; CHECK: %[[#all_bool_arg:]] = OpFunctionParameter %[[#bool]] 169 ; CHECK: OpReturnValue %[[#all_bool_arg]] 170 %hlsl.all = call i1 @llvm.spv.all.i1(i1 %a) 171 ret i1 %hlsl.all 172} 173 174declare i1 @llvm.spv.all.v4f16(<4 x half>) 175declare i1 @llvm.spv.all.v4f32(<4 x float>) 176declare i1 @llvm.spv.all.v4f64(<4 x double>) 177declare i1 @llvm.spv.all.v4i1(<4 x i1>) 178declare i1 @llvm.spv.all.v4i16(<4 x i16>) 179declare i1 @llvm.spv.all.v4i32(<4 x i32>) 180declare i1 @llvm.spv.all.v4i64(<4 x i64>) 181declare i1 @llvm.spv.all.i1(i1) 182declare i1 @llvm.spv.all.i16(i16) 183declare i1 @llvm.spv.all.i32(i32) 184declare i1 @llvm.spv.all.i64(i64) 185declare i1 @llvm.spv.all.f16(half) 186declare i1 @llvm.spv.all.f32(float) 187declare i1 @llvm.spv.all.f64(double) 188