1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 2; RUN: llc < %s -mtriple=sparc64-pc-openbsd -disable-sparc-leaf-proc | FileCheck %s 3; Testing 64-bit conditionals. The sparc64 triple is an alias for sparcv9. 4 5define void @cmpri(ptr %p, i64 %x) nounwind { 6; CHECK-LABEL: cmpri: 7; CHECK: ! %bb.0: ! %entry 8; CHECK-NEXT: save %sp, -128, %sp 9; CHECK-NEXT: cmp %i1, 1 10; CHECK-NEXT: be %xcc, .LBB0_2 11; CHECK-NEXT: nop 12; CHECK-NEXT: ! %bb.1: ! %if.then 13; CHECK-NEXT: stx %i1, [%i0] 14; CHECK-NEXT: .LBB0_2: ! %if.end 15; CHECK-NEXT: ret 16; CHECK-NEXT: restore 17entry: 18 %tobool = icmp eq i64 %x, 1 19 br i1 %tobool, label %if.end, label %if.then 20 21if.then: 22 store i64 %x, ptr %p, align 8 23 br label %if.end 24 25if.end: 26 ret void 27} 28 29define void @cmprr(ptr %p, i64 %x, i64 %y) nounwind { 30; CHECK-LABEL: cmprr: 31; CHECK: ! %bb.0: ! %entry 32; CHECK-NEXT: save %sp, -128, %sp 33; CHECK-NEXT: cmp %i1, %i2 34; CHECK-NEXT: bgu %xcc, .LBB1_2 35; CHECK-NEXT: nop 36; CHECK-NEXT: ! %bb.1: ! %if.then 37; CHECK-NEXT: stx %i1, [%i0] 38; CHECK-NEXT: .LBB1_2: ! %if.end 39; CHECK-NEXT: ret 40; CHECK-NEXT: restore 41entry: 42 %tobool = icmp ugt i64 %x, %y 43 br i1 %tobool, label %if.end, label %if.then 44 45if.then: 46 store i64 %x, ptr %p, align 8 47 br label %if.end 48 49if.end: 50 ret void 51} 52 53define i32 @selecti32_xcc(i64 %x, i64 %y, i32 %a, i32 %b) nounwind { 54; CHECK-LABEL: selecti32_xcc: 55; CHECK: ! %bb.0: ! %entry 56; CHECK-NEXT: save %sp, -128, %sp 57; CHECK-NEXT: cmp %i0, %i1 58; CHECK-NEXT: movg %xcc, %i2, %i3 59; CHECK-NEXT: ret 60; CHECK-NEXT: restore %g0, %i3, %o0 61entry: 62 %tobool = icmp sgt i64 %x, %y 63 %rv = select i1 %tobool, i32 %a, i32 %b 64 ret i32 %rv 65} 66 67define i64 @selecti64_xcc(i64 %x, i64 %y, i64 %a, i64 %b) nounwind { 68; CHECK-LABEL: selecti64_xcc: 69; CHECK: ! %bb.0: ! %entry 70; CHECK-NEXT: save %sp, -128, %sp 71; CHECK-NEXT: cmp %i0, %i1 72; CHECK-NEXT: movg %xcc, %i2, %i3 73; CHECK-NEXT: ret 74; CHECK-NEXT: restore %g0, %i3, %o0 75entry: 76 %tobool = icmp sgt i64 %x, %y 77 %rv = select i1 %tobool, i64 %a, i64 %b 78 ret i64 %rv 79} 80 81define i64 @selecti64_icc(i32 %x, i32 %y, i64 %a, i64 %b) nounwind { 82; CHECK-LABEL: selecti64_icc: 83; CHECK: ! %bb.0: ! %entry 84; CHECK-NEXT: save %sp, -128, %sp 85; CHECK-NEXT: cmp %i0, %i1 86; CHECK-NEXT: movg %icc, %i2, %i3 87; CHECK-NEXT: ret 88; CHECK-NEXT: restore %g0, %i3, %o0 89entry: 90 %tobool = icmp sgt i32 %x, %y 91 %rv = select i1 %tobool, i64 %a, i64 %b 92 ret i64 %rv 93} 94 95define i64 @selecti64_fcc(float %x, float %y, i64 %a, i64 %b) nounwind { 96; CHECK-LABEL: selecti64_fcc: 97; CHECK: ! %bb.0: ! %entry 98; CHECK-NEXT: save %sp, -128, %sp 99; CHECK-NEXT: mov %i3, %i0 100; CHECK-NEXT: fcmps %fcc0, %f1, %f3 101; CHECK-NEXT: movul %fcc0, %i2, %i0 102; CHECK-NEXT: ret 103; CHECK-NEXT: restore 104entry: 105 %tobool = fcmp ult float %x, %y 106 %rv = select i1 %tobool, i64 %a, i64 %b 107 ret i64 %rv 108} 109 110define float @selectf32_xcc(i64 %x, i64 %y, float %a, float %b) nounwind { 111; CHECK-LABEL: selectf32_xcc: 112; CHECK: ! %bb.0: ! %entry 113; CHECK-NEXT: save %sp, -128, %sp 114; CHECK-NEXT: fmovs %f7, %f0 115; CHECK-NEXT: cmp %i0, %i1 116; CHECK-NEXT: fmovsg %xcc, %f5, %f0 117; CHECK-NEXT: ret 118; CHECK-NEXT: restore 119entry: 120 %tobool = icmp sgt i64 %x, %y 121 %rv = select i1 %tobool, float %a, float %b 122 ret float %rv 123} 124 125define double @selectf64_xcc(i64 %x, i64 %y, double %a, double %b) nounwind { 126; CHECK-LABEL: selectf64_xcc: 127; CHECK: ! %bb.0: ! %entry 128; CHECK-NEXT: save %sp, -128, %sp 129; CHECK-NEXT: fmovd %f6, %f0 130; CHECK-NEXT: cmp %i0, %i1 131; CHECK-NEXT: fmovdg %xcc, %f4, %f0 132; CHECK-NEXT: ret 133; CHECK-NEXT: restore 134entry: 135 %tobool = icmp sgt i64 %x, %y 136 %rv = select i1 %tobool, double %a, double %b 137 ret double %rv 138} 139 140; The MOVXCC instruction can't use %g0 for its tied operand. 141define i64 @select_consti64_xcc(i64 %x, i64 %y) nounwind { 142; CHECK-LABEL: select_consti64_xcc: 143; CHECK: ! %bb.0: ! %entry 144; CHECK-NEXT: save %sp, -128, %sp 145; CHECK-NEXT: mov %g0, %i2 146; CHECK-NEXT: cmp %i0, %i1 147; CHECK-NEXT: movg %xcc, 123, %i2 148; CHECK-NEXT: ret 149; CHECK-NEXT: restore %g0, %i2, %o0 150entry: 151 %tobool = icmp sgt i64 %x, %y 152 %rv = select i1 %tobool, i64 123, i64 0 153 ret i64 %rv 154} 155 156define i1 @setcc_resultty(i64 %a, i1 %b) nounwind { 157; CHECK-LABEL: setcc_resultty: 158; CHECK: ! %bb.0: 159; CHECK-NEXT: save %sp, -128, %sp 160; CHECK-NEXT: mov %g0, %i2 161; CHECK-NEXT: sethi 4194303, %i3 162; CHECK-NEXT: or %i3, 1023, %i3 163; CHECK-NEXT: sethi 131071, %i4 164; CHECK-NEXT: or %i4, 1023, %i4 165; CHECK-NEXT: sllx %i4, 32, %i4 166; CHECK-NEXT: or %i4, %i3, %i3 167; CHECK-NEXT: and %i0, %i3, %i3 168; CHECK-NEXT: cmp %i3, %i0 169; CHECK-NEXT: movne %xcc, 1, %i2 170; CHECK-NEXT: or %i2, %i1, %i0 171; CHECK-NEXT: ret 172; CHECK-NEXT: restore 173 %a0 = tail call { i64, i1 } @llvm.umul.with.overflow.i64(i64 %a, i64 32) 174 %a1 = extractvalue { i64, i1 } %a0, 1 175 %a4 = or i1 %a1, %b 176 ret i1 %a4 177} 178 179declare { i64, i1 } @llvm.umul.with.overflow.i64(i64, i64) 180