xref: /llvm-project/llvm/test/CodeGen/RISCV/zcmp-additional-stack.ll (revision 97982a8c605fac7c86d02e641a6cd7898b3ca343)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
2; RUN: llc -mtriple=riscv32 -mattr=+zcmp,+e -target-abi ilp32e -verify-machineinstrs < %s | FileCheck %s --check-prefix=RV32
3define ptr @func(ptr %s, i32 %_c, ptr %incdec.ptr, i1 %0, i8 %conv14) #0 {
4; RV32-LABEL: func:
5; RV32:       # %bb.0: # %entry
6; RV32-NEXT:    cm.push {ra, s0-s1}, -16
7; RV32-NEXT:    .cfi_def_cfa_offset 16
8; RV32-NEXT:    .cfi_offset ra, -12
9; RV32-NEXT:    .cfi_offset s0, -8
10; RV32-NEXT:    .cfi_offset s1, -4
11; RV32-NEXT:    addi sp, sp, -8
12; RV32-NEXT:    .cfi_def_cfa_offset 24
13; RV32-NEXT:    sw a4, 4(sp) # 4-byte Folded Spill
14; RV32-NEXT:    sw a2, 0(sp) # 4-byte Folded Spill
15; RV32-NEXT:    mv a2, a1
16; RV32-NEXT:    mv s1, a0
17; RV32-NEXT:    li a0, 1
18; RV32-NEXT:    andi a3, a3, 1
19; RV32-NEXT:  .LBB0_1: # %while.body
20; RV32-NEXT:    # =>This Inner Loop Header: Depth=1
21; RV32-NEXT:    mv s0, a0
22; RV32-NEXT:    li a0, 0
23; RV32-NEXT:    bnez a3, .LBB0_1
24; RV32-NEXT:  # %bb.2: # %while.end
25; RV32-NEXT:    lui a0, 4112
26; RV32-NEXT:    addi a1, a0, 257
27; RV32-NEXT:    mv a0, a2
28; RV32-NEXT:    call __mulsi3
29; RV32-NEXT:    sw a0, 0(zero)
30; RV32-NEXT:    andi s0, s0, 1
31; RV32-NEXT:    lw a0, 0(sp) # 4-byte Folded Reload
32; RV32-NEXT:    add s0, s0, a0
33; RV32-NEXT:    lw a0, 4(sp) # 4-byte Folded Reload
34; RV32-NEXT:    sb a0, 0(s0)
35; RV32-NEXT:    mv a0, s1
36; RV32-NEXT:    addi sp, sp, 8
37; RV32-NEXT:    .cfi_def_cfa_offset 16
38; RV32-NEXT:    cm.popret {ra, s0-s1}, 16
39entry:
40  br label %while.body
41
42while.body:                                       ; preds = %while.body, %entry
43  %n.addr.042 = phi i32 [ 1, %entry ], [ 0, %while.body ]
44  br i1 %0, label %while.body, label %while.end
45
46while.end:                                        ; preds = %while.body
47  %or5 = mul i32 %_c, 16843009
48  store i32 %or5, ptr null, align 4
49  %1 = and i32 %n.addr.042, 1
50  %scevgep = getelementptr i8, ptr %incdec.ptr, i32 %1
51  store i8 %conv14, ptr %scevgep, align 1
52  ret ptr %s
53}
54