xref: /llvm-project/llvm/test/CodeGen/RISCV/zcb-regalloc-hints.ll (revision d360963aaa90710752d684035404db80c3dc1645)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
2; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+zba,+zbb,+zcb | FileCheck %s
3
4define i64 @c_not(i64 %x, i64 %y, i64 %z) {
5; CHECK-LABEL: c_not:
6; CHECK:       # %bb.0:
7; CHECK-NEXT:    not a1, a1
8; CHECK-NEXT:    li a0, 1234
9; CHECK-NEXT:    mul a0, a0, a1
10; CHECK-NEXT:    ret
11  %a = xor i64 %y, -1
12  %b = mul i64 %a, 1234
13  ret i64 %b
14}
15
16define i64 @c_mul(i64 %x, i64 %y, i64 %z, i64 %w) {
17; CHECK-LABEL: c_mul:
18; CHECK:       # %bb.0:
19; CHECK-NEXT:    mul a1, a1, a2
20; CHECK-NEXT:    lui a0, 1
21; CHECK-NEXT:    or a0, a0, a1
22; CHECK-NEXT:    ret
23  %a = mul i64 %y, %z
24  %b = or i64 %a, 4096
25  ret i64 %b
26}
27
28define i64 @c_sext_b(i64 %x, i8 %y, i64 %z) {
29; CHECK-LABEL: c_sext_b:
30; CHECK:       # %bb.0:
31; CHECK-NEXT:    sext.b a1, a1
32; CHECK-NEXT:    lui a0, 1
33; CHECK-NEXT:    or a0, a0, a1
34; CHECK-NEXT:    ret
35  %a = sext i8 %y to i64
36  %b = or i64 %a, 4096
37  ret i64 %b
38}
39
40define i64 @c_sext_h(i64 %x, i16 %y, i64 %z) {
41; CHECK-LABEL: c_sext_h:
42; CHECK:       # %bb.0:
43; CHECK-NEXT:    sext.h a1, a1
44; CHECK-NEXT:    lui a0, 1
45; CHECK-NEXT:    or a0, a0, a1
46; CHECK-NEXT:    ret
47  %a = sext i16 %y to i64
48  %b = or i64 %a, 4096
49  ret i64 %b
50}
51
52define i64 @c_zext_b(i64 %x, i8 %y, i64 %z) {
53; CHECK-LABEL: c_zext_b:
54; CHECK:       # %bb.0:
55; CHECK-NEXT:    andi a1, a1, 255
56; CHECK-NEXT:    lui a0, 1
57; CHECK-NEXT:    or a0, a0, a1
58; CHECK-NEXT:    ret
59  %a = zext i8 %y to i64
60  %b = or i64 %a, 4096
61  ret i64 %b
62}
63
64define i64 @c_zext_h(i64 %x, i16 %y) {
65; CHECK-LABEL: c_zext_h:
66; CHECK:       # %bb.0:
67; CHECK-NEXT:    zext.h a1, a1
68; CHECK-NEXT:    lui a0, 4096
69; CHECK-NEXT:    or a0, a0, a1
70; CHECK-NEXT:    ret
71  %a = zext i16 %y to i64
72  %b = or i64 %a, 16777216
73  ret i64 %b
74}
75
76define i64 @c_zext_w(i64 %x, i32 %y) {
77; CHECK-LABEL: c_zext_w:
78; CHECK:       # %bb.0:
79; CHECK-NEXT:    zext.w a1, a1
80; CHECK-NEXT:    li a0, 1234
81; CHECK-NEXT:    mul a0, a0, a1
82; CHECK-NEXT:    ret
83  %a = zext i32 %y to i64
84  %b = mul i64 %a, 1234
85  ret i64 %b
86}
87