xref: /llvm-project/llvm/test/CodeGen/RISCV/xcvmac.ll (revision 6441df3b5930ff9f8b3b9af6fd5d2684cf9a337b) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+m -mattr=+xcvmac -verify-machineinstrs < %s \
3; RUN:   | FileCheck %s
4
5declare i32 @llvm.riscv.cv.mac.mac(i32, i32, i32)
6
7define i32 @test.mac(i32 %a, i32 %b, i32 %c) {
8; CHECK-LABEL: test.mac:
9; CHECK:       # %bb.0:
10; CHECK-NEXT:    cv.mac a2, a0, a1
11; CHECK-NEXT:    mv a0, a2
12; CHECK-NEXT:    ret
13  %1 = call i32 @llvm.riscv.cv.mac.mac(i32 %a, i32 %b, i32 %c)
14  ret i32 %1
15}
16
17declare i32 @llvm.riscv.cv.mac.msu(i32, i32, i32)
18
19define i32 @test.msu(i32 %a, i32 %b, i32 %c) {
20; CHECK-LABEL: test.msu:
21; CHECK:       # %bb.0:
22; CHECK-NEXT:    cv.msu a2, a0, a1
23; CHECK-NEXT:    mv a0, a2
24; CHECK-NEXT:    ret
25  %1 = call i32 @llvm.riscv.cv.mac.msu(i32 %a, i32 %b, i32 %c)
26  ret i32 %1
27}
28
29declare i32 @llvm.riscv.cv.mac.muluN(i32, i32, i32)
30
31define i32 @test.muluN(i32 %a, i32 %b) {
32; CHECK-LABEL: test.muluN:
33; CHECK:       # %bb.0:
34; CHECK-NEXT:    cv.mulun a0, a0, a1, 5
35; CHECK-NEXT:    ret
36  %1 = call i32 @llvm.riscv.cv.mac.muluN(i32 %a, i32 %b, i32 5)
37  ret i32 %1
38}
39
40declare i32 @llvm.riscv.cv.mac.mulhhuN(i32, i32, i32)
41
42define i32 @test.mulhhuN(i32 %a, i32 %b) {
43; CHECK-LABEL: test.mulhhuN:
44; CHECK:       # %bb.0:
45; CHECK-NEXT:    cv.mulhhun a0, a0, a1, 5
46; CHECK-NEXT:    ret
47  %1 = call i32 @llvm.riscv.cv.mac.mulhhuN(i32 %a, i32 %b, i32 5)
48  ret i32 %1
49}
50
51declare i32 @llvm.riscv.cv.mac.mulsN(i32, i32, i32)
52
53define i32 @test.mulsN(i32 %a, i32 %b) {
54; CHECK-LABEL: test.mulsN:
55; CHECK:       # %bb.0:
56; CHECK-NEXT:    cv.mulsn a0, a0, a1, 5
57; CHECK-NEXT:    ret
58  %1 = call i32 @llvm.riscv.cv.mac.mulsN(i32 %a, i32 %b, i32 5)
59  ret i32 %1
60}
61
62declare i32 @llvm.riscv.cv.mac.mulhhsN(i32, i32, i32)
63
64define i32 @test.mulhhsN(i32 %a, i32 %b) {
65; CHECK-LABEL: test.mulhhsN:
66; CHECK:       # %bb.0:
67; CHECK-NEXT:    cv.mulhhsn a0, a0, a1, 5
68; CHECK-NEXT:    ret
69  %1 = call i32 @llvm.riscv.cv.mac.mulhhsN(i32 %a, i32 %b, i32 5)
70  ret i32 %1
71}
72
73declare i32 @llvm.riscv.cv.mac.muluRN(i32, i32, i32)
74
75define i32 @test.muluRN(i32 %a, i32 %b) {
76; CHECK-LABEL: test.muluRN:
77; CHECK:       # %bb.0:
78; CHECK-NEXT:    cv.mulurn a0, a0, a1, 5
79; CHECK-NEXT:    ret
80  %1 = call i32 @llvm.riscv.cv.mac.muluRN(i32 %a, i32 %b, i32 5)
81  ret i32 %1
82}
83
84declare i32 @llvm.riscv.cv.mac.mulhhuRN(i32, i32, i32)
85
86define i32 @test.mulhhuRN(i32 %a, i32 %b) {
87; CHECK-LABEL: test.mulhhuRN:
88; CHECK:       # %bb.0:
89; CHECK-NEXT:    cv.mulhhurn a0, a0, a1, 5
90; CHECK-NEXT:    ret
91  %1 = call i32 @llvm.riscv.cv.mac.mulhhuRN(i32 %a, i32 %b, i32 5)
92  ret i32 %1
93}
94
95declare i32 @llvm.riscv.cv.mac.mulsRN(i32, i32, i32)
96
97define i32 @test.mulsRN(i32 %a, i32 %b) {
98; CHECK-LABEL: test.mulsRN:
99; CHECK:       # %bb.0:
100; CHECK-NEXT:    cv.mulsrn a0, a0, a1, 5
101; CHECK-NEXT:    ret
102  %1 = call i32 @llvm.riscv.cv.mac.mulsRN(i32 %a, i32 %b, i32 5)
103  ret i32 %1
104}
105
106declare i32 @llvm.riscv.cv.mac.mulhhsRN(i32, i32, i32)
107
108define i32 @test.mulhhsRN(i32 %a, i32 %b) {
109; CHECK-LABEL: test.mulhhsRN:
110; CHECK:       # %bb.0:
111; CHECK-NEXT:    cv.mulhhsrn a0, a0, a1, 5
112; CHECK-NEXT:    ret
113  %1 = call i32 @llvm.riscv.cv.mac.mulhhsRN(i32 %a, i32 %b, i32 5)
114  ret i32 %1
115}
116
117declare i32 @llvm.riscv.cv.mac.macuN(i32, i32, i32, i32)
118
119define i32 @test.macuN(i32 %a, i32 %b, i32 %c) {
120; CHECK-LABEL: test.macuN:
121; CHECK:       # %bb.0:
122; CHECK-NEXT:    cv.macun a2, a0, a1, 5
123; CHECK-NEXT:    mv a0, a2
124; CHECK-NEXT:    ret
125  %1 = call i32 @llvm.riscv.cv.mac.macuN(i32 %a, i32 %b, i32 %c, i32 5)
126  ret i32 %1
127}
128
129declare i32 @llvm.riscv.cv.mac.machhuN(i32, i32, i32, i32)
130
131define i32 @test.machhuN(i32 %a, i32 %b, i32 %c) {
132; CHECK-LABEL: test.machhuN:
133; CHECK:       # %bb.0:
134; CHECK-NEXT:    cv.machhun a2, a0, a1, 5
135; CHECK-NEXT:    mv a0, a2
136; CHECK-NEXT:    ret
137  %1 = call i32 @llvm.riscv.cv.mac.machhuN(i32 %a, i32 %b, i32 %c, i32 5)
138  ret i32 %1
139}
140
141declare i32 @llvm.riscv.cv.mac.macsN(i32, i32, i32, i32)
142
143define i32 @test.macsN(i32 %a, i32 %b, i32 %c) {
144; CHECK-LABEL: test.macsN:
145; CHECK:       # %bb.0:
146; CHECK-NEXT:    cv.macsn a2, a0, a1, 5
147; CHECK-NEXT:    mv a0, a2
148; CHECK-NEXT:    ret
149  %1 = call i32 @llvm.riscv.cv.mac.macsN(i32 %a, i32 %b, i32 %c, i32 5)
150  ret i32 %1
151}
152
153declare i32 @llvm.riscv.cv.mac.machhsN(i32, i32, i32, i32)
154
155define i32 @test.machhsN(i32 %a, i32 %b, i32 %c) {
156; CHECK-LABEL: test.machhsN:
157; CHECK:       # %bb.0:
158; CHECK-NEXT:    cv.machhsn a2, a0, a1, 5
159; CHECK-NEXT:    mv a0, a2
160; CHECK-NEXT:    ret
161  %1 = call i32 @llvm.riscv.cv.mac.machhsN(i32 %a, i32 %b, i32 %c, i32 5)
162  ret i32 %1
163}
164
165declare i32 @llvm.riscv.cv.mac.macuRN(i32, i32, i32, i32)
166
167define i32 @test.macuRN(i32 %a, i32 %b, i32 %c) {
168; CHECK-LABEL: test.macuRN:
169; CHECK:       # %bb.0:
170; CHECK-NEXT:    cv.macurn a2, a0, a1, 5
171; CHECK-NEXT:    mv a0, a2
172; CHECK-NEXT:    ret
173  %1 = call i32 @llvm.riscv.cv.mac.macuRN(i32 %a, i32 %b, i32 %c, i32 5)
174  ret i32 %1
175}
176
177declare i32 @llvm.riscv.cv.mac.machhuRN(i32, i32, i32, i32)
178
179define i32 @test.machhuRN(i32 %a, i32 %b, i32 %c) {
180; CHECK-LABEL: test.machhuRN:
181; CHECK:       # %bb.0:
182; CHECK-NEXT:    cv.machhurn a2, a0, a1, 5
183; CHECK-NEXT:    mv a0, a2
184; CHECK-NEXT:    ret
185  %1 = call i32 @llvm.riscv.cv.mac.machhuRN(i32 %a, i32 %b, i32 %c, i32 5)
186  ret i32 %1
187}
188
189declare i32 @llvm.riscv.cv.mac.macsRN(i32, i32, i32, i32)
190
191define i32 @test.macsRN(i32 %a, i32 %b, i32 %c) {
192; CHECK-LABEL: test.macsRN:
193; CHECK:       # %bb.0:
194; CHECK-NEXT:    cv.macsrn a2, a0, a1, 5
195; CHECK-NEXT:    mv a0, a2
196; CHECK-NEXT:    ret
197  %1 = call i32 @llvm.riscv.cv.mac.macsRN(i32 %a, i32 %b, i32 %c, i32 5)
198  ret i32 %1
199}
200
201declare i32 @llvm.riscv.cv.mac.machhsRN(i32, i32, i32, i32)
202
203define i32 @test.machhsRN(i32 %a, i32 %b, i32 %c) {
204; CHECK-LABEL: test.machhsRN:
205; CHECK:       # %bb.0:
206; CHECK-NEXT:    cv.machhsrn a2, a0, a1, 5
207; CHECK-NEXT:    mv a0, a2
208; CHECK-NEXT:    ret
209  %1 = call i32 @llvm.riscv.cv.mac.machhsRN(i32 %a, i32 %b, i32 %c, i32 5)
210  ret i32 %1
211}
212