1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple riscv64 -mattr +v -filetype asm -o - %s | FileCheck %s 3 4declare i8 @llvm.vscale.i8() 5declare <vscale x 8 x i8> @llvm.stepvector.nxv8i8() 6 7define <vscale x 8 x i8> @f() #0 { 8; CHECK-LABEL: f: 9; CHECK: # %bb.0: # %entry 10; CHECK-NEXT: csrr a0, vlenb 11; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma 12; CHECK-NEXT: vid.v v8 13; CHECK-NEXT: vadd.vx v8, v8, a0 14; CHECK-NEXT: ret 15entry: 16 %0 = tail call i8 @llvm.vscale.i8() 17 %1 = shl i8 %0, 3 18 %.splat.insert = insertelement <vscale x 8 x i8> poison, i8 %1, i64 0 19 %.splat = shufflevector <vscale x 8 x i8> %.splat.insert, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer 20 %2 = tail call <vscale x 8 x i8> @llvm.stepvector.nxv8i8() 21 %3 = add <vscale x 8 x i8> %2, %.splat 22 ret <vscale x 8 x i8> %3 23} 24 25attributes #0 = { vscale_range(2,1024) } 26