1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 2; RUN: llc -mtriple=riscv32 -mattr=+v \ 3; RUN: -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK 4; RUN: llc -mtriple=riscv64 -mattr=+v \ 5; RUN: -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK 6 7define target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_tuple_zero_power_of_2() { 8; CHECK-LABEL: test_tuple_zero_power_of_2: 9; CHECK: # %bb.0: # %entry 10; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma 11; CHECK-NEXT: vmv.v.i v8, 0 12; CHECK-NEXT: vmv.v.i v10, 0 13; CHECK-NEXT: ret 14entry: 15 ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) zeroinitializer 16} 17 18define target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_tuple_zero_non_power_of_2() { 19; CHECK-LABEL: test_tuple_zero_non_power_of_2: 20; CHECK: # %bb.0: # %entry 21; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma 22; CHECK-NEXT: vmv.v.i v8, 0 23; CHECK-NEXT: vmv.v.i v10, 0 24; CHECK-NEXT: vmv.v.i v12, 0 25; CHECK-NEXT: ret 26entry: 27 ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) zeroinitializer 28} 29 30define target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_tuple_zero_insert1(<vscale x 4 x i32> %a) { 31; CHECK-LABEL: test_tuple_zero_insert1: 32; CHECK: # %bb.0: # %entry 33; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma 34; CHECK-NEXT: vmv.v.i v10, 0 35; CHECK-NEXT: ret 36entry: 37 %1 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv16i8_2t.nxv4i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) zeroinitializer, <vscale x 4 x i32> %a, i32 0) 38 ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %1 39} 40 41define target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_tuple_zero_insert2(<vscale x 4 x i32> %a) { 42; CHECK-LABEL: test_tuple_zero_insert2: 43; CHECK: # %bb.0: # %entry 44; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma 45; CHECK-NEXT: vmv.v.i v6, 0 46; CHECK-NEXT: vmv2r.v v10, v8 47; CHECK-NEXT: vmv2r.v v8, v6 48; CHECK-NEXT: ret 49entry: 50 %1 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv16i8_2t.nxv4i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) zeroinitializer, <vscale x 4 x i32> %a, i32 1) 51 ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %1 52} 53