xref: /llvm-project/llvm/test/CodeGen/RISCV/uadd_sat.ll (revision 86eff6be686a1e41e13c08ebfc2db4dd4d58e7c6) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=riscv32 -mattr=+m | FileCheck %s --check-prefix=RV32I
3; RUN: llc < %s -mtriple=riscv64 -mattr=+m | FileCheck %s --check-prefix=RV64I
4; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+zbb | FileCheck %s --check-prefix=RV32IZbb
5; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+zbb | FileCheck %s --check-prefix=RV64IZbb
6
7declare i4 @llvm.uadd.sat.i4(i4, i4)
8declare i8 @llvm.uadd.sat.i8(i8, i8)
9declare i16 @llvm.uadd.sat.i16(i16, i16)
10declare i32 @llvm.uadd.sat.i32(i32, i32)
11declare i64 @llvm.uadd.sat.i64(i64, i64)
12
13define signext i32 @func(i32 signext %x, i32 signext %y) nounwind {
14; RV32I-LABEL: func:
15; RV32I:       # %bb.0:
16; RV32I-NEXT:    add a1, a0, a1
17; RV32I-NEXT:    sltu a0, a1, a0
18; RV32I-NEXT:    neg a0, a0
19; RV32I-NEXT:    or a0, a0, a1
20; RV32I-NEXT:    ret
21;
22; RV64I-LABEL: func:
23; RV64I:       # %bb.0:
24; RV64I-NEXT:    addw a1, a0, a1
25; RV64I-NEXT:    sltu a0, a1, a0
26; RV64I-NEXT:    neg a0, a0
27; RV64I-NEXT:    or a0, a0, a1
28; RV64I-NEXT:    ret
29;
30; RV32IZbb-LABEL: func:
31; RV32IZbb:       # %bb.0:
32; RV32IZbb-NEXT:    not a2, a1
33; RV32IZbb-NEXT:    minu a0, a0, a2
34; RV32IZbb-NEXT:    add a0, a0, a1
35; RV32IZbb-NEXT:    ret
36;
37; RV64IZbb-LABEL: func:
38; RV64IZbb:       # %bb.0:
39; RV64IZbb-NEXT:    not a2, a1
40; RV64IZbb-NEXT:    minu a0, a0, a2
41; RV64IZbb-NEXT:    addw a0, a0, a1
42; RV64IZbb-NEXT:    ret
43  %tmp = call i32 @llvm.uadd.sat.i32(i32 %x, i32 %y);
44  ret i32 %tmp;
45}
46
47define i64 @func2(i64 %x, i64 %y) nounwind {
48; RV32I-LABEL: func2:
49; RV32I:       # %bb.0:
50; RV32I-NEXT:    add a3, a1, a3
51; RV32I-NEXT:    add a2, a0, a2
52; RV32I-NEXT:    sltu a0, a2, a0
53; RV32I-NEXT:    add a3, a3, a0
54; RV32I-NEXT:    beq a3, a1, .LBB1_2
55; RV32I-NEXT:  # %bb.1:
56; RV32I-NEXT:    sltu a0, a3, a1
57; RV32I-NEXT:  .LBB1_2:
58; RV32I-NEXT:    neg a1, a0
59; RV32I-NEXT:    or a0, a1, a2
60; RV32I-NEXT:    or a1, a1, a3
61; RV32I-NEXT:    ret
62;
63; RV64I-LABEL: func2:
64; RV64I:       # %bb.0:
65; RV64I-NEXT:    add a1, a0, a1
66; RV64I-NEXT:    sltu a0, a1, a0
67; RV64I-NEXT:    neg a0, a0
68; RV64I-NEXT:    or a0, a0, a1
69; RV64I-NEXT:    ret
70;
71; RV32IZbb-LABEL: func2:
72; RV32IZbb:       # %bb.0:
73; RV32IZbb-NEXT:    add a3, a1, a3
74; RV32IZbb-NEXT:    add a2, a0, a2
75; RV32IZbb-NEXT:    sltu a0, a2, a0
76; RV32IZbb-NEXT:    add a3, a3, a0
77; RV32IZbb-NEXT:    beq a3, a1, .LBB1_2
78; RV32IZbb-NEXT:  # %bb.1:
79; RV32IZbb-NEXT:    sltu a0, a3, a1
80; RV32IZbb-NEXT:  .LBB1_2:
81; RV32IZbb-NEXT:    neg a1, a0
82; RV32IZbb-NEXT:    or a0, a1, a2
83; RV32IZbb-NEXT:    or a1, a1, a3
84; RV32IZbb-NEXT:    ret
85;
86; RV64IZbb-LABEL: func2:
87; RV64IZbb:       # %bb.0:
88; RV64IZbb-NEXT:    not a2, a1
89; RV64IZbb-NEXT:    minu a0, a0, a2
90; RV64IZbb-NEXT:    add a0, a0, a1
91; RV64IZbb-NEXT:    ret
92  %tmp = call i64 @llvm.uadd.sat.i64(i64 %x, i64 %y);
93  ret i64 %tmp;
94}
95
96define zeroext i16 @func16(i16 zeroext %x, i16 zeroext %y) nounwind {
97; RV32I-LABEL: func16:
98; RV32I:       # %bb.0:
99; RV32I-NEXT:    add a0, a0, a1
100; RV32I-NEXT:    lui a1, 16
101; RV32I-NEXT:    addi a1, a1, -1
102; RV32I-NEXT:    bltu a0, a1, .LBB2_2
103; RV32I-NEXT:  # %bb.1:
104; RV32I-NEXT:    mv a0, a1
105; RV32I-NEXT:  .LBB2_2:
106; RV32I-NEXT:    ret
107;
108; RV64I-LABEL: func16:
109; RV64I:       # %bb.0:
110; RV64I-NEXT:    add a0, a0, a1
111; RV64I-NEXT:    lui a1, 16
112; RV64I-NEXT:    addiw a1, a1, -1
113; RV64I-NEXT:    bltu a0, a1, .LBB2_2
114; RV64I-NEXT:  # %bb.1:
115; RV64I-NEXT:    mv a0, a1
116; RV64I-NEXT:  .LBB2_2:
117; RV64I-NEXT:    ret
118;
119; RV32IZbb-LABEL: func16:
120; RV32IZbb:       # %bb.0:
121; RV32IZbb-NEXT:    add a0, a0, a1
122; RV32IZbb-NEXT:    lui a1, 16
123; RV32IZbb-NEXT:    addi a1, a1, -1
124; RV32IZbb-NEXT:    minu a0, a0, a1
125; RV32IZbb-NEXT:    ret
126;
127; RV64IZbb-LABEL: func16:
128; RV64IZbb:       # %bb.0:
129; RV64IZbb-NEXT:    add a0, a0, a1
130; RV64IZbb-NEXT:    lui a1, 16
131; RV64IZbb-NEXT:    addiw a1, a1, -1
132; RV64IZbb-NEXT:    minu a0, a0, a1
133; RV64IZbb-NEXT:    ret
134  %tmp = call i16 @llvm.uadd.sat.i16(i16 %x, i16 %y);
135  ret i16 %tmp;
136}
137
138define zeroext i8 @func8(i8 zeroext %x, i8 zeroext %y) nounwind {
139; RV32I-LABEL: func8:
140; RV32I:       # %bb.0:
141; RV32I-NEXT:    add a0, a0, a1
142; RV32I-NEXT:    li a1, 255
143; RV32I-NEXT:    bltu a0, a1, .LBB3_2
144; RV32I-NEXT:  # %bb.1:
145; RV32I-NEXT:    li a0, 255
146; RV32I-NEXT:  .LBB3_2:
147; RV32I-NEXT:    ret
148;
149; RV64I-LABEL: func8:
150; RV64I:       # %bb.0:
151; RV64I-NEXT:    add a0, a0, a1
152; RV64I-NEXT:    li a1, 255
153; RV64I-NEXT:    bltu a0, a1, .LBB3_2
154; RV64I-NEXT:  # %bb.1:
155; RV64I-NEXT:    li a0, 255
156; RV64I-NEXT:  .LBB3_2:
157; RV64I-NEXT:    ret
158;
159; RV32IZbb-LABEL: func8:
160; RV32IZbb:       # %bb.0:
161; RV32IZbb-NEXT:    add a0, a0, a1
162; RV32IZbb-NEXT:    li a1, 255
163; RV32IZbb-NEXT:    minu a0, a0, a1
164; RV32IZbb-NEXT:    ret
165;
166; RV64IZbb-LABEL: func8:
167; RV64IZbb:       # %bb.0:
168; RV64IZbb-NEXT:    add a0, a0, a1
169; RV64IZbb-NEXT:    li a1, 255
170; RV64IZbb-NEXT:    minu a0, a0, a1
171; RV64IZbb-NEXT:    ret
172  %tmp = call i8 @llvm.uadd.sat.i8(i8 %x, i8 %y);
173  ret i8 %tmp;
174}
175
176define zeroext i4 @func3(i4 zeroext %x, i4 zeroext %y) nounwind {
177; RV32I-LABEL: func3:
178; RV32I:       # %bb.0:
179; RV32I-NEXT:    add a0, a0, a1
180; RV32I-NEXT:    li a1, 15
181; RV32I-NEXT:    bltu a0, a1, .LBB4_2
182; RV32I-NEXT:  # %bb.1:
183; RV32I-NEXT:    li a0, 15
184; RV32I-NEXT:  .LBB4_2:
185; RV32I-NEXT:    ret
186;
187; RV64I-LABEL: func3:
188; RV64I:       # %bb.0:
189; RV64I-NEXT:    add a0, a0, a1
190; RV64I-NEXT:    li a1, 15
191; RV64I-NEXT:    bltu a0, a1, .LBB4_2
192; RV64I-NEXT:  # %bb.1:
193; RV64I-NEXT:    li a0, 15
194; RV64I-NEXT:  .LBB4_2:
195; RV64I-NEXT:    ret
196;
197; RV32IZbb-LABEL: func3:
198; RV32IZbb:       # %bb.0:
199; RV32IZbb-NEXT:    add a0, a0, a1
200; RV32IZbb-NEXT:    li a1, 15
201; RV32IZbb-NEXT:    minu a0, a0, a1
202; RV32IZbb-NEXT:    ret
203;
204; RV64IZbb-LABEL: func3:
205; RV64IZbb:       # %bb.0:
206; RV64IZbb-NEXT:    add a0, a0, a1
207; RV64IZbb-NEXT:    li a1, 15
208; RV64IZbb-NEXT:    minu a0, a0, a1
209; RV64IZbb-NEXT:    ret
210  %tmp = call i4 @llvm.uadd.sat.i4(i4 %x, i4 %y);
211  ret i4 %tmp;
212}
213