xref: /llvm-project/llvm/test/CodeGen/RISCV/switch-width.ll (revision 9e1ad3cff6a855fdfdc1d91323e2021726da04ea) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -O2 -mtriple=riscv64 | FileCheck %s
3
4define i32 @native_i64(i64 %a)  {
5; CHECK-LABEL: native_i64:
6; CHECK:       # %bb.0: # %entry
7; CHECK-NEXT:    li a1, -1
8; CHECK-NEXT:    beq a0, a1, .LBB0_3
9; CHECK-NEXT:  # %bb.1: # %entry
10; CHECK-NEXT:    li a1, 1
11; CHECK-NEXT:    bne a0, a1, .LBB0_4
12; CHECK-NEXT:  # %bb.2: # %sw.bb0
13; CHECK-NEXT:    li a0, 0
14; CHECK-NEXT:    ret
15; CHECK-NEXT:  .LBB0_3: # %sw.bb1
16; CHECK-NEXT:    li a0, 1
17; CHECK-NEXT:    ret
18; CHECK-NEXT:  .LBB0_4: # %sw.default
19; CHECK-NEXT:    li a0, -1
20; CHECK-NEXT:    ret
21entry:
22  switch i64 %a, label %sw.default [
23  i64 1, label %sw.bb0
24  i64 -1, label %sw.bb1
25  ]
26
27sw.bb0:
28  br label %return
29
30sw.bb1:
31  br label %return
32
33sw.default:
34  br label %return
35
36return:
37  %retval = phi i32 [ -1, %sw.default ], [ 0, %sw.bb0 ], [ 1, %sw.bb1 ]
38  ret i32 %retval
39}
40
41define i32 @native_i32(i32 %a)  {
42; CHECK-LABEL: native_i32:
43; CHECK:       # %bb.0: # %entry
44; CHECK-NEXT:    sext.w a0, a0
45; CHECK-NEXT:    li a1, -1
46; CHECK-NEXT:    beq a0, a1, .LBB1_3
47; CHECK-NEXT:  # %bb.1: # %entry
48; CHECK-NEXT:    li a1, 1
49; CHECK-NEXT:    bne a0, a1, .LBB1_4
50; CHECK-NEXT:  # %bb.2: # %sw.bb0
51; CHECK-NEXT:    li a0, 0
52; CHECK-NEXT:    ret
53; CHECK-NEXT:  .LBB1_3: # %sw.bb1
54; CHECK-NEXT:    li a0, 1
55; CHECK-NEXT:    ret
56; CHECK-NEXT:  .LBB1_4: # %sw.default
57; CHECK-NEXT:    li a0, -1
58; CHECK-NEXT:    ret
59entry:
60  switch i32 %a, label %sw.default [
61  i32 1, label %sw.bb0
62  i32 -1, label %sw.bb1
63  ]
64
65sw.bb0:
66  br label %return
67
68sw.bb1:
69  br label %return
70
71sw.default:
72  br label %return
73
74return:
75  %retval = phi i32 [ -1, %sw.default ], [ 0, %sw.bb0 ], [ 1, %sw.bb1 ]
76  ret i32 %retval
77}
78
79define i32 @trunc_i32(i64 %a)  {
80; CHECK-LABEL: trunc_i32:
81; CHECK:       # %bb.0: # %entry
82; CHECK-NEXT:    sext.w a0, a0
83; CHECK-NEXT:    li a1, -1
84; CHECK-NEXT:    beq a0, a1, .LBB2_3
85; CHECK-NEXT:  # %bb.1: # %entry
86; CHECK-NEXT:    li a1, 1
87; CHECK-NEXT:    bne a0, a1, .LBB2_4
88; CHECK-NEXT:  # %bb.2: # %sw.bb0
89; CHECK-NEXT:    li a0, 0
90; CHECK-NEXT:    ret
91; CHECK-NEXT:  .LBB2_3: # %sw.bb1
92; CHECK-NEXT:    li a0, 1
93; CHECK-NEXT:    ret
94; CHECK-NEXT:  .LBB2_4: # %sw.default
95; CHECK-NEXT:    li a0, -1
96; CHECK-NEXT:    ret
97entry:
98  %trunc = trunc i64 %a to i32
99  switch i32 %trunc, label %sw.default [
100  i32 1, label %sw.bb0
101  i32 -1, label %sw.bb1
102  ]
103
104sw.bb0:
105  br label %return
106
107sw.bb1:
108  br label %return
109
110sw.default:
111  br label %return
112
113return:
114  %retval = phi i32 [ -1, %sw.default ], [ 0, %sw.bb0 ], [ 1, %sw.bb1 ]
115  ret i32 %retval
116}
117
118define i32 @trunc_i17(i64 %a)  {
119; CHECK-LABEL: trunc_i17:
120; CHECK:       # %bb.0: # %entry
121; CHECK-NEXT:    lui a1, 32
122; CHECK-NEXT:    addiw a1, a1, -1
123; CHECK-NEXT:    and a0, a0, a1
124; CHECK-NEXT:    beq a0, a1, .LBB3_3
125; CHECK-NEXT:  # %bb.1: # %entry
126; CHECK-NEXT:    li a1, 1
127; CHECK-NEXT:    bne a0, a1, .LBB3_4
128; CHECK-NEXT:  # %bb.2: # %sw.bb0
129; CHECK-NEXT:    li a0, 0
130; CHECK-NEXT:    ret
131; CHECK-NEXT:  .LBB3_3: # %sw.bb1
132; CHECK-NEXT:    li a0, 1
133; CHECK-NEXT:    ret
134; CHECK-NEXT:  .LBB3_4: # %sw.default
135; CHECK-NEXT:    li a0, -1
136; CHECK-NEXT:    ret
137entry:
138  %trunc = trunc i64 %a to i17
139  switch i17 %trunc, label %sw.default [
140  i17 1, label %sw.bb0
141  i17 -1, label %sw.bb1
142  ]
143
144sw.bb0:
145  br label %return
146
147sw.bb1:
148  br label %return
149
150sw.default:
151  br label %return
152
153return:
154  %retval = phi i32 [ -1, %sw.default ], [ 0, %sw.bb0 ], [ 1, %sw.bb1 ]
155  ret i32 %retval
156}
157
158define i32 @trunc_i16(i64 %a)  {
159; CHECK-LABEL: trunc_i16:
160; CHECK:       # %bb.0: # %entry
161; CHECK-NEXT:    lui a1, 16
162; CHECK-NEXT:    addiw a1, a1, -1
163; CHECK-NEXT:    and a0, a0, a1
164; CHECK-NEXT:    beq a0, a1, .LBB4_3
165; CHECK-NEXT:  # %bb.1: # %entry
166; CHECK-NEXT:    li a1, 1
167; CHECK-NEXT:    bne a0, a1, .LBB4_4
168; CHECK-NEXT:  # %bb.2: # %sw.bb0
169; CHECK-NEXT:    li a0, 0
170; CHECK-NEXT:    ret
171; CHECK-NEXT:  .LBB4_3: # %sw.bb1
172; CHECK-NEXT:    li a0, 1
173; CHECK-NEXT:    ret
174; CHECK-NEXT:  .LBB4_4: # %sw.default
175; CHECK-NEXT:    li a0, -1
176; CHECK-NEXT:    ret
177entry:
178  %trunc = trunc i64 %a to i16
179  switch i16 %trunc, label %sw.default [
180  i16 1, label %sw.bb0
181  i16 -1, label %sw.bb1
182  ]
183
184sw.bb0:
185  br label %return
186
187sw.bb1:
188  br label %return
189
190sw.default:
191  br label %return
192
193return:
194  %retval = phi i32 [ -1, %sw.default ], [ 0, %sw.bb0 ], [ 1, %sw.bb1 ]
195  ret i32 %retval
196}
197
198
199define i32 @trunc_i12(i64 %a)  {
200; CHECK-LABEL: trunc_i12:
201; CHECK:       # %bb.0: # %entry
202; CHECK-NEXT:    lui a1, 1
203; CHECK-NEXT:    addiw a1, a1, -1
204; CHECK-NEXT:    and a0, a0, a1
205; CHECK-NEXT:    beq a0, a1, .LBB5_3
206; CHECK-NEXT:  # %bb.1: # %entry
207; CHECK-NEXT:    li a1, 1
208; CHECK-NEXT:    bne a0, a1, .LBB5_4
209; CHECK-NEXT:  # %bb.2: # %sw.bb0
210; CHECK-NEXT:    li a0, 0
211; CHECK-NEXT:    ret
212; CHECK-NEXT:  .LBB5_3: # %sw.bb1
213; CHECK-NEXT:    li a0, 1
214; CHECK-NEXT:    ret
215; CHECK-NEXT:  .LBB5_4: # %sw.default
216; CHECK-NEXT:    li a0, -1
217; CHECK-NEXT:    ret
218entry:
219  %trunc = trunc i64 %a to i12
220  switch i12 %trunc, label %sw.default [
221  i12 1, label %sw.bb0
222  i12 -1, label %sw.bb1
223  ]
224
225sw.bb0:
226  br label %return
227
228sw.bb1:
229  br label %return
230
231sw.default:
232  br label %return
233
234return:
235  %retval = phi i32 [ -1, %sw.default ], [ 0, %sw.bb0 ], [ 1, %sw.bb1 ]
236  ret i32 %retval
237}
238
239define i32 @trunc_i11(i64 %a)  {
240; CHECK-LABEL: trunc_i11:
241; CHECK:       # %bb.0: # %entry
242; CHECK-NEXT:    andi a0, a0, 2047
243; CHECK-NEXT:    li a1, 2047
244; CHECK-NEXT:    beq a0, a1, .LBB6_3
245; CHECK-NEXT:  # %bb.1: # %entry
246; CHECK-NEXT:    li a1, 1
247; CHECK-NEXT:    bne a0, a1, .LBB6_4
248; CHECK-NEXT:  # %bb.2: # %sw.bb0
249; CHECK-NEXT:    li a0, 0
250; CHECK-NEXT:    ret
251; CHECK-NEXT:  .LBB6_3: # %sw.bb1
252; CHECK-NEXT:    li a0, 1
253; CHECK-NEXT:    ret
254; CHECK-NEXT:  .LBB6_4: # %sw.default
255; CHECK-NEXT:    li a0, -1
256; CHECK-NEXT:    ret
257entry:
258  %trunc = trunc i64 %a to i11
259  switch i11 %trunc, label %sw.default [
260  i11 1, label %sw.bb0
261  i11 -1, label %sw.bb1
262  ]
263
264sw.bb0:
265  br label %return
266
267sw.bb1:
268  br label %return
269
270sw.default:
271  br label %return
272
273return:
274  %retval = phi i32 [ -1, %sw.default ], [ 0, %sw.bb0 ], [ 1, %sw.bb1 ]
275  ret i32 %retval
276}
277
278
279define i32 @trunc_i10(i64 %a)  {
280; CHECK-LABEL: trunc_i10:
281; CHECK:       # %bb.0: # %entry
282; CHECK-NEXT:    andi a0, a0, 1023
283; CHECK-NEXT:    li a1, 1023
284; CHECK-NEXT:    beq a0, a1, .LBB7_3
285; CHECK-NEXT:  # %bb.1: # %entry
286; CHECK-NEXT:    li a1, 1
287; CHECK-NEXT:    bne a0, a1, .LBB7_4
288; CHECK-NEXT:  # %bb.2: # %sw.bb0
289; CHECK-NEXT:    li a0, 0
290; CHECK-NEXT:    ret
291; CHECK-NEXT:  .LBB7_3: # %sw.bb1
292; CHECK-NEXT:    li a0, 1
293; CHECK-NEXT:    ret
294; CHECK-NEXT:  .LBB7_4: # %sw.default
295; CHECK-NEXT:    li a0, -1
296; CHECK-NEXT:    ret
297entry:
298  %trunc = trunc i64 %a to i10
299  switch i10 %trunc, label %sw.default [
300  i10 1, label %sw.bb0
301  i10 -1, label %sw.bb1
302  ]
303
304sw.bb0:
305  br label %return
306
307sw.bb1:
308  br label %return
309
310sw.default:
311  br label %return
312
313return:
314  %retval = phi i32 [ -1, %sw.default ], [ 0, %sw.bb0 ], [ 1, %sw.bb1 ]
315  ret i32 %retval
316}
317