xref: /llvm-project/llvm/test/CodeGen/RISCV/stack-clash-prologue.ll (revision 01d7f434d21a70158094a9c7da971ce9e0d0915c) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv64 -mattr=+m -O2 < %s \
3; RUN:   | FileCheck %s -check-prefix=RV64I
4; RUN: llc -mtriple=riscv32 -mattr=+m -O2 < %s \
5; RUN:   | FileCheck %s -check-prefix=RV32I
6
7; Tests copied from PowerPC.
8
9; Free probe
10define i8 @f0() #0 {
11; RV64I-LABEL: f0:
12; RV64I:       # %bb.0: # %entry
13; RV64I-NEXT:    addi sp, sp, -64
14; RV64I-NEXT:    .cfi_def_cfa_offset 64
15; RV64I-NEXT:    li a0, 3
16; RV64I-NEXT:    sb a0, 0(sp)
17; RV64I-NEXT:    lbu a0, 0(sp)
18; RV64I-NEXT:    addi sp, sp, 64
19; RV64I-NEXT:    .cfi_def_cfa_offset 0
20; RV64I-NEXT:    ret
21;
22; RV32I-LABEL: f0:
23; RV32I:       # %bb.0: # %entry
24; RV32I-NEXT:    addi sp, sp, -64
25; RV32I-NEXT:    .cfi_def_cfa_offset 64
26; RV32I-NEXT:    li a0, 3
27; RV32I-NEXT:    sb a0, 0(sp)
28; RV32I-NEXT:    lbu a0, 0(sp)
29; RV32I-NEXT:    addi sp, sp, 64
30; RV32I-NEXT:    .cfi_def_cfa_offset 0
31; RV32I-NEXT:    ret
32entry:
33  %a = alloca i8, i64 64
34  %b = getelementptr inbounds i8, ptr %a, i64 63
35  store volatile i8 3, ptr %a
36  %c = load volatile i8, ptr %a
37  ret i8 %c
38}
39
40define i8 @f1() #0 {
41; RV64I-LABEL: f1:
42; RV64I:       # %bb.0: # %entry
43; RV64I-NEXT:    lui a0, 1
44; RV64I-NEXT:    sub sp, sp, a0
45; RV64I-NEXT:    sd zero, 0(sp)
46; RV64I-NEXT:    .cfi_def_cfa_offset 4096
47; RV64I-NEXT:    addi sp, sp, -16
48; RV64I-NEXT:    .cfi_def_cfa_offset 4112
49; RV64I-NEXT:    li a0, 3
50; RV64I-NEXT:    sb a0, 16(sp)
51; RV64I-NEXT:    lbu a0, 16(sp)
52; RV64I-NEXT:    lui a1, 1
53; RV64I-NEXT:    addiw a1, a1, 16
54; RV64I-NEXT:    add sp, sp, a1
55; RV64I-NEXT:    .cfi_def_cfa_offset 0
56; RV64I-NEXT:    ret
57;
58; RV32I-LABEL: f1:
59; RV32I:       # %bb.0: # %entry
60; RV32I-NEXT:    lui a0, 1
61; RV32I-NEXT:    sub sp, sp, a0
62; RV32I-NEXT:    sw zero, 0(sp)
63; RV32I-NEXT:    .cfi_def_cfa_offset 4096
64; RV32I-NEXT:    addi sp, sp, -16
65; RV32I-NEXT:    .cfi_def_cfa_offset 4112
66; RV32I-NEXT:    li a0, 3
67; RV32I-NEXT:    sb a0, 16(sp)
68; RV32I-NEXT:    lbu a0, 16(sp)
69; RV32I-NEXT:    lui a1, 1
70; RV32I-NEXT:    addi a1, a1, 16
71; RV32I-NEXT:    add sp, sp, a1
72; RV32I-NEXT:    .cfi_def_cfa_offset 0
73; RV32I-NEXT:    ret
74entry:
75  %a = alloca i8, i64 4096
76  %b = getelementptr inbounds i8, ptr %a, i64 63
77  store volatile i8 3, ptr %a
78  %c = load volatile i8, ptr %a
79  ret i8 %c
80}
81
82define i8 @f2() #0 {
83; RV64I-LABEL: f2:
84; RV64I:       # %bb.0: # %entry
85; RV64I-NEXT:    lui a0, 16
86; RV64I-NEXT:    sub t1, sp, a0
87; RV64I-NEXT:    .cfi_def_cfa t1, 65536
88; RV64I-NEXT:    lui t2, 1
89; RV64I-NEXT:  .LBB2_1: # %entry
90; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
91; RV64I-NEXT:    sub sp, sp, t2
92; RV64I-NEXT:    sd zero, 0(sp)
93; RV64I-NEXT:    bne sp, t1, .LBB2_1
94; RV64I-NEXT:  # %bb.2: # %entry
95; RV64I-NEXT:    .cfi_def_cfa_register sp
96; RV64I-NEXT:    addi sp, sp, -16
97; RV64I-NEXT:    .cfi_def_cfa_offset 65552
98; RV64I-NEXT:    li a0, 3
99; RV64I-NEXT:    sb a0, 16(sp)
100; RV64I-NEXT:    lbu a0, 16(sp)
101; RV64I-NEXT:    lui a1, 16
102; RV64I-NEXT:    addiw a1, a1, 16
103; RV64I-NEXT:    add sp, sp, a1
104; RV64I-NEXT:    .cfi_def_cfa_offset 0
105; RV64I-NEXT:    ret
106;
107; RV32I-LABEL: f2:
108; RV32I:       # %bb.0: # %entry
109; RV32I-NEXT:    lui a0, 16
110; RV32I-NEXT:    sub t1, sp, a0
111; RV32I-NEXT:    .cfi_def_cfa t1, 65536
112; RV32I-NEXT:    lui t2, 1
113; RV32I-NEXT:  .LBB2_1: # %entry
114; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
115; RV32I-NEXT:    sub sp, sp, t2
116; RV32I-NEXT:    sw zero, 0(sp)
117; RV32I-NEXT:    bne sp, t1, .LBB2_1
118; RV32I-NEXT:  # %bb.2: # %entry
119; RV32I-NEXT:    .cfi_def_cfa_register sp
120; RV32I-NEXT:    addi sp, sp, -16
121; RV32I-NEXT:    .cfi_def_cfa_offset 65552
122; RV32I-NEXT:    li a0, 3
123; RV32I-NEXT:    sb a0, 16(sp)
124; RV32I-NEXT:    lbu a0, 16(sp)
125; RV32I-NEXT:    lui a1, 16
126; RV32I-NEXT:    addi a1, a1, 16
127; RV32I-NEXT:    add sp, sp, a1
128; RV32I-NEXT:    .cfi_def_cfa_offset 0
129; RV32I-NEXT:    ret
130entry:
131  %a = alloca i8, i64 65536
132  %b = getelementptr inbounds i8, ptr %a, i64 63
133  store volatile i8 3, ptr %a
134  %c = load volatile i8, ptr %a
135  ret i8 %c
136}
137
138define i8 @f3() #0 "stack-probe-size"="32768" {
139; RV64I-LABEL: f3:
140; RV64I:       # %bb.0: # %entry
141; RV64I-NEXT:    lui a0, 8
142; RV64I-NEXT:    sub sp, sp, a0
143; RV64I-NEXT:    sd zero, 0(sp)
144; RV64I-NEXT:    .cfi_def_cfa_offset 32768
145; RV64I-NEXT:    lui a0, 8
146; RV64I-NEXT:    sub sp, sp, a0
147; RV64I-NEXT:    sd zero, 0(sp)
148; RV64I-NEXT:    .cfi_def_cfa_offset 65536
149; RV64I-NEXT:    addi sp, sp, -16
150; RV64I-NEXT:    .cfi_def_cfa_offset 65552
151; RV64I-NEXT:    li a0, 3
152; RV64I-NEXT:    sb a0, 16(sp)
153; RV64I-NEXT:    lbu a0, 16(sp)
154; RV64I-NEXT:    lui a1, 16
155; RV64I-NEXT:    addiw a1, a1, 16
156; RV64I-NEXT:    add sp, sp, a1
157; RV64I-NEXT:    .cfi_def_cfa_offset 0
158; RV64I-NEXT:    ret
159;
160; RV32I-LABEL: f3:
161; RV32I:       # %bb.0: # %entry
162; RV32I-NEXT:    lui a0, 8
163; RV32I-NEXT:    sub sp, sp, a0
164; RV32I-NEXT:    sw zero, 0(sp)
165; RV32I-NEXT:    .cfi_def_cfa_offset 32768
166; RV32I-NEXT:    lui a0, 8
167; RV32I-NEXT:    sub sp, sp, a0
168; RV32I-NEXT:    sw zero, 0(sp)
169; RV32I-NEXT:    .cfi_def_cfa_offset 65536
170; RV32I-NEXT:    addi sp, sp, -16
171; RV32I-NEXT:    .cfi_def_cfa_offset 65552
172; RV32I-NEXT:    li a0, 3
173; RV32I-NEXT:    sb a0, 16(sp)
174; RV32I-NEXT:    lbu a0, 16(sp)
175; RV32I-NEXT:    lui a1, 16
176; RV32I-NEXT:    addi a1, a1, 16
177; RV32I-NEXT:    add sp, sp, a1
178; RV32I-NEXT:    .cfi_def_cfa_offset 0
179; RV32I-NEXT:    ret
180entry:
181  %a = alloca i8, i64 65536
182  %b = getelementptr inbounds i8, ptr %a, i64 63
183  store volatile i8 3, ptr %a
184  %c = load volatile i8, ptr %a
185  ret i8 %c
186}
187
188; Same as f2, but without protection.
189define i8 @f4() {
190; RV64I-LABEL: f4:
191; RV64I:       # %bb.0: # %entry
192; RV64I-NEXT:    lui a0, 16
193; RV64I-NEXT:    addiw a0, a0, 16
194; RV64I-NEXT:    sub sp, sp, a0
195; RV64I-NEXT:    .cfi_def_cfa_offset 65552
196; RV64I-NEXT:    li a0, 3
197; RV64I-NEXT:    sb a0, 16(sp)
198; RV64I-NEXT:    lbu a0, 16(sp)
199; RV64I-NEXT:    lui a1, 16
200; RV64I-NEXT:    addiw a1, a1, 16
201; RV64I-NEXT:    add sp, sp, a1
202; RV64I-NEXT:    .cfi_def_cfa_offset 0
203; RV64I-NEXT:    ret
204;
205; RV32I-LABEL: f4:
206; RV32I:       # %bb.0: # %entry
207; RV32I-NEXT:    lui a0, 16
208; RV32I-NEXT:    addi a0, a0, 16
209; RV32I-NEXT:    sub sp, sp, a0
210; RV32I-NEXT:    .cfi_def_cfa_offset 65552
211; RV32I-NEXT:    li a0, 3
212; RV32I-NEXT:    sb a0, 16(sp)
213; RV32I-NEXT:    lbu a0, 16(sp)
214; RV32I-NEXT:    lui a1, 16
215; RV32I-NEXT:    addi a1, a1, 16
216; RV32I-NEXT:    add sp, sp, a1
217; RV32I-NEXT:    .cfi_def_cfa_offset 0
218; RV32I-NEXT:    ret
219entry:
220  %a = alloca i8, i64 65536
221  %b = getelementptr inbounds i8, ptr %a, i64 63
222  store volatile i8 3, ptr %a
223  %c = load volatile i8, ptr %a
224  ret i8 %c
225}
226
227define i8 @f5() #0 "stack-probe-size"="65536" {
228; RV64I-LABEL: f5:
229; RV64I:       # %bb.0: # %entry
230; RV64I-NEXT:    lui a0, 256
231; RV64I-NEXT:    sub t1, sp, a0
232; RV64I-NEXT:    .cfi_def_cfa t1, 1048576
233; RV64I-NEXT:    lui t2, 16
234; RV64I-NEXT:  .LBB5_1: # %entry
235; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
236; RV64I-NEXT:    sub sp, sp, t2
237; RV64I-NEXT:    sd zero, 0(sp)
238; RV64I-NEXT:    bne sp, t1, .LBB5_1
239; RV64I-NEXT:  # %bb.2: # %entry
240; RV64I-NEXT:    .cfi_def_cfa_register sp
241; RV64I-NEXT:    addi sp, sp, -16
242; RV64I-NEXT:    .cfi_def_cfa_offset 1048592
243; RV64I-NEXT:    li a0, 3
244; RV64I-NEXT:    sb a0, 16(sp)
245; RV64I-NEXT:    lbu a0, 16(sp)
246; RV64I-NEXT:    lui a1, 256
247; RV64I-NEXT:    addiw a1, a1, 16
248; RV64I-NEXT:    add sp, sp, a1
249; RV64I-NEXT:    .cfi_def_cfa_offset 0
250; RV64I-NEXT:    ret
251;
252; RV32I-LABEL: f5:
253; RV32I:       # %bb.0: # %entry
254; RV32I-NEXT:    lui a0, 256
255; RV32I-NEXT:    sub t1, sp, a0
256; RV32I-NEXT:    .cfi_def_cfa t1, 1048576
257; RV32I-NEXT:    lui t2, 16
258; RV32I-NEXT:  .LBB5_1: # %entry
259; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
260; RV32I-NEXT:    sub sp, sp, t2
261; RV32I-NEXT:    sw zero, 0(sp)
262; RV32I-NEXT:    bne sp, t1, .LBB5_1
263; RV32I-NEXT:  # %bb.2: # %entry
264; RV32I-NEXT:    .cfi_def_cfa_register sp
265; RV32I-NEXT:    addi sp, sp, -16
266; RV32I-NEXT:    .cfi_def_cfa_offset 1048592
267; RV32I-NEXT:    li a0, 3
268; RV32I-NEXT:    sb a0, 16(sp)
269; RV32I-NEXT:    lbu a0, 16(sp)
270; RV32I-NEXT:    lui a1, 256
271; RV32I-NEXT:    addi a1, a1, 16
272; RV32I-NEXT:    add sp, sp, a1
273; RV32I-NEXT:    .cfi_def_cfa_offset 0
274; RV32I-NEXT:    ret
275entry:
276  %a = alloca i8, i64 1048576
277  %b = getelementptr inbounds i8, ptr %a, i64 63
278  store volatile i8 3, ptr %a
279  %c = load volatile i8, ptr %a
280  ret i8 %c
281}
282
283define i8 @f6() #0 {
284; RV64I-LABEL: f6:
285; RV64I:       # %bb.0: # %entry
286; RV64I-NEXT:    lui a0, 262144
287; RV64I-NEXT:    sub t1, sp, a0
288; RV64I-NEXT:    .cfi_def_cfa t1, 1073741824
289; RV64I-NEXT:    lui t2, 1
290; RV64I-NEXT:  .LBB6_1: # %entry
291; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
292; RV64I-NEXT:    sub sp, sp, t2
293; RV64I-NEXT:    sd zero, 0(sp)
294; RV64I-NEXT:    bne sp, t1, .LBB6_1
295; RV64I-NEXT:  # %bb.2: # %entry
296; RV64I-NEXT:    .cfi_def_cfa_register sp
297; RV64I-NEXT:    addi sp, sp, -16
298; RV64I-NEXT:    .cfi_def_cfa_offset 1073741840
299; RV64I-NEXT:    li a0, 3
300; RV64I-NEXT:    sb a0, 16(sp)
301; RV64I-NEXT:    lbu a0, 16(sp)
302; RV64I-NEXT:    lui a1, 262144
303; RV64I-NEXT:    addiw a1, a1, 16
304; RV64I-NEXT:    add sp, sp, a1
305; RV64I-NEXT:    .cfi_def_cfa_offset 0
306; RV64I-NEXT:    ret
307;
308; RV32I-LABEL: f6:
309; RV32I:       # %bb.0: # %entry
310; RV32I-NEXT:    lui a0, 262144
311; RV32I-NEXT:    sub t1, sp, a0
312; RV32I-NEXT:    .cfi_def_cfa t1, 1073741824
313; RV32I-NEXT:    lui t2, 1
314; RV32I-NEXT:  .LBB6_1: # %entry
315; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
316; RV32I-NEXT:    sub sp, sp, t2
317; RV32I-NEXT:    sw zero, 0(sp)
318; RV32I-NEXT:    bne sp, t1, .LBB6_1
319; RV32I-NEXT:  # %bb.2: # %entry
320; RV32I-NEXT:    .cfi_def_cfa_register sp
321; RV32I-NEXT:    addi sp, sp, -16
322; RV32I-NEXT:    .cfi_def_cfa_offset 1073741840
323; RV32I-NEXT:    li a0, 3
324; RV32I-NEXT:    sb a0, 16(sp)
325; RV32I-NEXT:    lbu a0, 16(sp)
326; RV32I-NEXT:    lui a1, 262144
327; RV32I-NEXT:    addi a1, a1, 16
328; RV32I-NEXT:    add sp, sp, a1
329; RV32I-NEXT:    .cfi_def_cfa_offset 0
330; RV32I-NEXT:    ret
331entry:
332  %a = alloca i8, i64 1073741824
333  %b = getelementptr inbounds i8, ptr %a, i64 63
334  store volatile i8 3, ptr %a
335  %c = load volatile i8, ptr %a
336  ret i8 %c
337}
338
339define i8 @f7() #0 "stack-probe-size"="65536" {
340; RV64I-LABEL: f7:
341; RV64I:       # %bb.0: # %entry
342; RV64I-NEXT:    lui a0, 244128
343; RV64I-NEXT:    sub t1, sp, a0
344; RV64I-NEXT:    .cfi_def_cfa t1, 999948288
345; RV64I-NEXT:    lui t2, 16
346; RV64I-NEXT:  .LBB7_1: # %entry
347; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
348; RV64I-NEXT:    sub sp, sp, t2
349; RV64I-NEXT:    sd zero, 0(sp)
350; RV64I-NEXT:    bne sp, t1, .LBB7_1
351; RV64I-NEXT:  # %bb.2: # %entry
352; RV64I-NEXT:    .cfi_def_cfa_register sp
353; RV64I-NEXT:    lui a0, 13
354; RV64I-NEXT:    addiw a0, a0, -1520
355; RV64I-NEXT:    sub sp, sp, a0
356; RV64I-NEXT:    .cfi_def_cfa_offset 1000000016
357; RV64I-NEXT:    li a0, 3
358; RV64I-NEXT:    sb a0, 9(sp)
359; RV64I-NEXT:    lbu a0, 9(sp)
360; RV64I-NEXT:    lui a1, 244141
361; RV64I-NEXT:    addiw a1, a1, -1520
362; RV64I-NEXT:    add sp, sp, a1
363; RV64I-NEXT:    .cfi_def_cfa_offset 0
364; RV64I-NEXT:    ret
365;
366; RV32I-LABEL: f7:
367; RV32I:       # %bb.0: # %entry
368; RV32I-NEXT:    lui a0, 244128
369; RV32I-NEXT:    sub t1, sp, a0
370; RV32I-NEXT:    .cfi_def_cfa t1, 999948288
371; RV32I-NEXT:    lui t2, 16
372; RV32I-NEXT:  .LBB7_1: # %entry
373; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
374; RV32I-NEXT:    sub sp, sp, t2
375; RV32I-NEXT:    sw zero, 0(sp)
376; RV32I-NEXT:    bne sp, t1, .LBB7_1
377; RV32I-NEXT:  # %bb.2: # %entry
378; RV32I-NEXT:    .cfi_def_cfa_register sp
379; RV32I-NEXT:    lui a0, 13
380; RV32I-NEXT:    addi a0, a0, -1520
381; RV32I-NEXT:    sub sp, sp, a0
382; RV32I-NEXT:    .cfi_def_cfa_offset 1000000016
383; RV32I-NEXT:    li a0, 3
384; RV32I-NEXT:    sb a0, 9(sp)
385; RV32I-NEXT:    lbu a0, 9(sp)
386; RV32I-NEXT:    lui a1, 244141
387; RV32I-NEXT:    addi a1, a1, -1520
388; RV32I-NEXT:    add sp, sp, a1
389; RV32I-NEXT:    .cfi_def_cfa_offset 0
390; RV32I-NEXT:    ret
391entry:
392  %a = alloca i8, i64 1000000007
393  %b = getelementptr inbounds i8, ptr %a, i64 101
394  store volatile i8 3, ptr %a
395  %c = load volatile i8, ptr %a
396  ret i8 %c
397}
398
399; alloca + align < probe_size
400define i32 @f8(i64 %i) local_unnamed_addr #0 {
401; RV64I-LABEL: f8:
402; RV64I:       # %bb.0:
403; RV64I-NEXT:    addi sp, sp, -832
404; RV64I-NEXT:    .cfi_def_cfa_offset 832
405; RV64I-NEXT:    sd ra, 824(sp) # 8-byte Folded Spill
406; RV64I-NEXT:    sd s0, 816(sp) # 8-byte Folded Spill
407; RV64I-NEXT:    .cfi_offset ra, -8
408; RV64I-NEXT:    .cfi_offset s0, -16
409; RV64I-NEXT:    addi s0, sp, 832
410; RV64I-NEXT:    .cfi_def_cfa s0, 0
411; RV64I-NEXT:    andi sp, sp, -64
412; RV64I-NEXT:    slli a0, a0, 2
413; RV64I-NEXT:    mv a1, sp
414; RV64I-NEXT:    add a0, a1, a0
415; RV64I-NEXT:    li a1, 1
416; RV64I-NEXT:    sw a1, 0(a0)
417; RV64I-NEXT:    lw a0, 0(sp)
418; RV64I-NEXT:    addi sp, s0, -832
419; RV64I-NEXT:    .cfi_def_cfa sp, 832
420; RV64I-NEXT:    ld ra, 824(sp) # 8-byte Folded Reload
421; RV64I-NEXT:    ld s0, 816(sp) # 8-byte Folded Reload
422; RV64I-NEXT:    .cfi_restore ra
423; RV64I-NEXT:    .cfi_restore s0
424; RV64I-NEXT:    addi sp, sp, 832
425; RV64I-NEXT:    .cfi_def_cfa_offset 0
426; RV64I-NEXT:    ret
427;
428; RV32I-LABEL: f8:
429; RV32I:       # %bb.0:
430; RV32I-NEXT:    addi sp, sp, -832
431; RV32I-NEXT:    .cfi_def_cfa_offset 832
432; RV32I-NEXT:    sw ra, 828(sp) # 4-byte Folded Spill
433; RV32I-NEXT:    sw s0, 824(sp) # 4-byte Folded Spill
434; RV32I-NEXT:    .cfi_offset ra, -4
435; RV32I-NEXT:    .cfi_offset s0, -8
436; RV32I-NEXT:    addi s0, sp, 832
437; RV32I-NEXT:    .cfi_def_cfa s0, 0
438; RV32I-NEXT:    andi sp, sp, -64
439; RV32I-NEXT:    slli a0, a0, 2
440; RV32I-NEXT:    mv a1, sp
441; RV32I-NEXT:    add a0, a1, a0
442; RV32I-NEXT:    li a1, 1
443; RV32I-NEXT:    sw a1, 0(a0)
444; RV32I-NEXT:    lw a0, 0(sp)
445; RV32I-NEXT:    addi sp, s0, -832
446; RV32I-NEXT:    .cfi_def_cfa sp, 832
447; RV32I-NEXT:    lw ra, 828(sp) # 4-byte Folded Reload
448; RV32I-NEXT:    lw s0, 824(sp) # 4-byte Folded Reload
449; RV32I-NEXT:    .cfi_restore ra
450; RV32I-NEXT:    .cfi_restore s0
451; RV32I-NEXT:    addi sp, sp, 832
452; RV32I-NEXT:    .cfi_def_cfa_offset 0
453; RV32I-NEXT:    ret
454  %a = alloca i32, i32 200, align 64
455  %b = getelementptr inbounds i32, ptr %a, i64 %i
456  store volatile i32 1, ptr %b
457  %c = load volatile i32, ptr %a
458  ret i32 %c
459}
460
461; alloca > probe_size, align > probe_size
462define i32 @f9(i64 %i) local_unnamed_addr #0 {
463; RV64I-LABEL: f9:
464; RV64I:       # %bb.0:
465; RV64I-NEXT:    addi sp, sp, -2032
466; RV64I-NEXT:    .cfi_def_cfa_offset 2032
467; RV64I-NEXT:    sd ra, 2024(sp) # 8-byte Folded Spill
468; RV64I-NEXT:    sd s0, 2016(sp) # 8-byte Folded Spill
469; RV64I-NEXT:    .cfi_offset ra, -8
470; RV64I-NEXT:    .cfi_offset s0, -16
471; RV64I-NEXT:    addi s0, sp, 2032
472; RV64I-NEXT:    .cfi_def_cfa s0, 0
473; RV64I-NEXT:    lui a1, 1
474; RV64I-NEXT:    sub sp, sp, a1
475; RV64I-NEXT:    sd zero, 0(sp)
476; RV64I-NEXT:    sub sp, sp, a1
477; RV64I-NEXT:    sd zero, 0(sp)
478; RV64I-NEXT:    addi sp, sp, -16
479; RV64I-NEXT:    andi sp, sp, -2048
480; RV64I-NEXT:    slli a0, a0, 2
481; RV64I-NEXT:    addi a1, sp, 2047
482; RV64I-NEXT:    addi a1, a1, 1
483; RV64I-NEXT:    add a0, a1, a0
484; RV64I-NEXT:    li a1, 1
485; RV64I-NEXT:    sw a1, 0(a0)
486; RV64I-NEXT:    lui a0, 1
487; RV64I-NEXT:    add a0, sp, a0
488; RV64I-NEXT:    lw a0, -2048(a0)
489; RV64I-NEXT:    addi sp, s0, -2032
490; RV64I-NEXT:    .cfi_def_cfa sp, 2032
491; RV64I-NEXT:    ld ra, 2024(sp) # 8-byte Folded Reload
492; RV64I-NEXT:    ld s0, 2016(sp) # 8-byte Folded Reload
493; RV64I-NEXT:    .cfi_restore ra
494; RV64I-NEXT:    .cfi_restore s0
495; RV64I-NEXT:    addi sp, sp, 2032
496; RV64I-NEXT:    .cfi_def_cfa_offset 0
497; RV64I-NEXT:    ret
498;
499; RV32I-LABEL: f9:
500; RV32I:       # %bb.0:
501; RV32I-NEXT:    addi sp, sp, -2032
502; RV32I-NEXT:    .cfi_def_cfa_offset 2032
503; RV32I-NEXT:    sw ra, 2028(sp) # 4-byte Folded Spill
504; RV32I-NEXT:    sw s0, 2024(sp) # 4-byte Folded Spill
505; RV32I-NEXT:    .cfi_offset ra, -4
506; RV32I-NEXT:    .cfi_offset s0, -8
507; RV32I-NEXT:    addi s0, sp, 2032
508; RV32I-NEXT:    .cfi_def_cfa s0, 0
509; RV32I-NEXT:    lui a1, 1
510; RV32I-NEXT:    sub sp, sp, a1
511; RV32I-NEXT:    sw zero, 0(sp)
512; RV32I-NEXT:    sub sp, sp, a1
513; RV32I-NEXT:    sw zero, 0(sp)
514; RV32I-NEXT:    addi sp, sp, -16
515; RV32I-NEXT:    andi sp, sp, -2048
516; RV32I-NEXT:    slli a0, a0, 2
517; RV32I-NEXT:    addi a1, sp, 2047
518; RV32I-NEXT:    addi a1, a1, 1
519; RV32I-NEXT:    add a0, a1, a0
520; RV32I-NEXT:    li a1, 1
521; RV32I-NEXT:    sw a1, 0(a0)
522; RV32I-NEXT:    lui a0, 1
523; RV32I-NEXT:    add a0, sp, a0
524; RV32I-NEXT:    lw a0, -2048(a0)
525; RV32I-NEXT:    addi sp, s0, -2032
526; RV32I-NEXT:    .cfi_def_cfa sp, 2032
527; RV32I-NEXT:    lw ra, 2028(sp) # 4-byte Folded Reload
528; RV32I-NEXT:    lw s0, 2024(sp) # 4-byte Folded Reload
529; RV32I-NEXT:    .cfi_restore ra
530; RV32I-NEXT:    .cfi_restore s0
531; RV32I-NEXT:    addi sp, sp, 2032
532; RV32I-NEXT:    .cfi_def_cfa_offset 0
533; RV32I-NEXT:    ret
534  %a = alloca i32, i32 2000, align 2048
535  %b = getelementptr inbounds i32, ptr %a, i64 %i
536  store volatile i32 1, ptr %b
537  %c = load volatile i32, ptr %a
538  ret i32 %c
539}
540
541; alloca < probe_size, align < probe_size, alloca + align > probe_size
542define i32 @f10(i64 %i) local_unnamed_addr #0 {
543; RV64I-LABEL: f10:
544; RV64I:       # %bb.0:
545; RV64I-NEXT:    addi sp, sp, -2032
546; RV64I-NEXT:    .cfi_def_cfa_offset 2032
547; RV64I-NEXT:    sd ra, 2024(sp) # 8-byte Folded Spill
548; RV64I-NEXT:    sd s0, 2016(sp) # 8-byte Folded Spill
549; RV64I-NEXT:    .cfi_offset ra, -8
550; RV64I-NEXT:    .cfi_offset s0, -16
551; RV64I-NEXT:    addi s0, sp, 2032
552; RV64I-NEXT:    .cfi_def_cfa s0, 0
553; RV64I-NEXT:    addi sp, sp, -2048
554; RV64I-NEXT:    addi sp, sp, -1040
555; RV64I-NEXT:    andi sp, sp, -1024
556; RV64I-NEXT:    sd zero, 0(sp)
557; RV64I-NEXT:    slli a0, a0, 2
558; RV64I-NEXT:    addi a1, sp, 1024
559; RV64I-NEXT:    add a0, a1, a0
560; RV64I-NEXT:    li a1, 1
561; RV64I-NEXT:    sw a1, 0(a0)
562; RV64I-NEXT:    lw a0, 1024(sp)
563; RV64I-NEXT:    addi sp, s0, -2032
564; RV64I-NEXT:    .cfi_def_cfa sp, 2032
565; RV64I-NEXT:    ld ra, 2024(sp) # 8-byte Folded Reload
566; RV64I-NEXT:    ld s0, 2016(sp) # 8-byte Folded Reload
567; RV64I-NEXT:    .cfi_restore ra
568; RV64I-NEXT:    .cfi_restore s0
569; RV64I-NEXT:    addi sp, sp, 2032
570; RV64I-NEXT:    .cfi_def_cfa_offset 0
571; RV64I-NEXT:    ret
572;
573; RV32I-LABEL: f10:
574; RV32I:       # %bb.0:
575; RV32I-NEXT:    addi sp, sp, -2032
576; RV32I-NEXT:    .cfi_def_cfa_offset 2032
577; RV32I-NEXT:    sw ra, 2028(sp) # 4-byte Folded Spill
578; RV32I-NEXT:    sw s0, 2024(sp) # 4-byte Folded Spill
579; RV32I-NEXT:    .cfi_offset ra, -4
580; RV32I-NEXT:    .cfi_offset s0, -8
581; RV32I-NEXT:    addi s0, sp, 2032
582; RV32I-NEXT:    .cfi_def_cfa s0, 0
583; RV32I-NEXT:    addi sp, sp, -2048
584; RV32I-NEXT:    addi sp, sp, -1040
585; RV32I-NEXT:    andi sp, sp, -1024
586; RV32I-NEXT:    sw zero, 0(sp)
587; RV32I-NEXT:    slli a0, a0, 2
588; RV32I-NEXT:    addi a1, sp, 1024
589; RV32I-NEXT:    add a0, a1, a0
590; RV32I-NEXT:    li a1, 1
591; RV32I-NEXT:    sw a1, 0(a0)
592; RV32I-NEXT:    lw a0, 1024(sp)
593; RV32I-NEXT:    addi sp, s0, -2032
594; RV32I-NEXT:    .cfi_def_cfa sp, 2032
595; RV32I-NEXT:    lw ra, 2028(sp) # 4-byte Folded Reload
596; RV32I-NEXT:    lw s0, 2024(sp) # 4-byte Folded Reload
597; RV32I-NEXT:    .cfi_restore ra
598; RV32I-NEXT:    .cfi_restore s0
599; RV32I-NEXT:    addi sp, sp, 2032
600; RV32I-NEXT:    .cfi_def_cfa_offset 0
601; RV32I-NEXT:    ret
602  %a = alloca i32, i32 1000, align 1024
603  %b = getelementptr inbounds i32, ptr %a, i64 %i
604  store volatile i32 1, ptr %b
605  %c = load volatile i32, ptr %a
606  ret i32 %c
607}
608
609define void @f11(i32 %vla_size, i64 %i) #0 {
610; RV64I-LABEL: f11:
611; RV64I:       # %bb.0:
612; RV64I-NEXT:    addi sp, sp, -2032
613; RV64I-NEXT:    .cfi_def_cfa_offset 2032
614; RV64I-NEXT:    sd zero, 0(sp)
615; RV64I-NEXT:    sd ra, 2024(sp) # 8-byte Folded Spill
616; RV64I-NEXT:    sd s0, 2016(sp) # 8-byte Folded Spill
617; RV64I-NEXT:    sd s1, 2008(sp) # 8-byte Folded Spill
618; RV64I-NEXT:    .cfi_offset ra, -8
619; RV64I-NEXT:    .cfi_offset s0, -16
620; RV64I-NEXT:    .cfi_offset s1, -24
621; RV64I-NEXT:    addi s0, sp, 2032
622; RV64I-NEXT:    .cfi_def_cfa s0, 0
623; RV64I-NEXT:    lui a2, 15
624; RV64I-NEXT:    sub t1, sp, a2
625; RV64I-NEXT:    lui t2, 1
626; RV64I-NEXT:  .LBB11_1: # =>This Inner Loop Header: Depth=1
627; RV64I-NEXT:    sub sp, sp, t2
628; RV64I-NEXT:    sd zero, 0(sp)
629; RV64I-NEXT:    bne sp, t1, .LBB11_1
630; RV64I-NEXT:  # %bb.2:
631; RV64I-NEXT:    addi sp, sp, -2048
632; RV64I-NEXT:    addi sp, sp, -16
633; RV64I-NEXT:    sd zero, 0(sp)
634; RV64I-NEXT:    srli a2, sp, 15
635; RV64I-NEXT:    slli sp, a2, 15
636; RV64I-NEXT:    mv s1, sp
637; RV64I-NEXT:    slli a1, a1, 2
638; RV64I-NEXT:    lui a2, 8
639; RV64I-NEXT:    add a2, s1, a2
640; RV64I-NEXT:    add a1, a2, a1
641; RV64I-NEXT:    li a2, 1
642; RV64I-NEXT:    slli a0, a0, 32
643; RV64I-NEXT:    srli a0, a0, 32
644; RV64I-NEXT:    sw a2, 0(a1)
645; RV64I-NEXT:    addi a0, a0, 15
646; RV64I-NEXT:    andi a0, a0, -16
647; RV64I-NEXT:    sub a0, sp, a0
648; RV64I-NEXT:    andi a0, a0, -2048
649; RV64I-NEXT:    lui a1, 1
650; RV64I-NEXT:  .LBB11_3: # =>This Inner Loop Header: Depth=1
651; RV64I-NEXT:    sub sp, sp, a1
652; RV64I-NEXT:    sd zero, 0(sp)
653; RV64I-NEXT:    blt a0, sp, .LBB11_3
654; RV64I-NEXT:  # %bb.4:
655; RV64I-NEXT:    mv sp, a0
656; RV64I-NEXT:    lbu zero, 0(a0)
657; RV64I-NEXT:    addi sp, s0, -2032
658; RV64I-NEXT:    .cfi_def_cfa sp, 2032
659; RV64I-NEXT:    ld ra, 2024(sp) # 8-byte Folded Reload
660; RV64I-NEXT:    ld s0, 2016(sp) # 8-byte Folded Reload
661; RV64I-NEXT:    ld s1, 2008(sp) # 8-byte Folded Reload
662; RV64I-NEXT:    .cfi_restore ra
663; RV64I-NEXT:    .cfi_restore s0
664; RV64I-NEXT:    .cfi_restore s1
665; RV64I-NEXT:    addi sp, sp, 2032
666; RV64I-NEXT:    .cfi_def_cfa_offset 0
667; RV64I-NEXT:    ret
668;
669; RV32I-LABEL: f11:
670; RV32I:       # %bb.0:
671; RV32I-NEXT:    addi sp, sp, -2032
672; RV32I-NEXT:    .cfi_def_cfa_offset 2032
673; RV32I-NEXT:    sw zero, 0(sp)
674; RV32I-NEXT:    sw ra, 2028(sp) # 4-byte Folded Spill
675; RV32I-NEXT:    sw s0, 2024(sp) # 4-byte Folded Spill
676; RV32I-NEXT:    sw s1, 2020(sp) # 4-byte Folded Spill
677; RV32I-NEXT:    .cfi_offset ra, -4
678; RV32I-NEXT:    .cfi_offset s0, -8
679; RV32I-NEXT:    .cfi_offset s1, -12
680; RV32I-NEXT:    addi s0, sp, 2032
681; RV32I-NEXT:    .cfi_def_cfa s0, 0
682; RV32I-NEXT:    lui a2, 15
683; RV32I-NEXT:    sub t1, sp, a2
684; RV32I-NEXT:    lui t2, 1
685; RV32I-NEXT:  .LBB11_1: # =>This Inner Loop Header: Depth=1
686; RV32I-NEXT:    sub sp, sp, t2
687; RV32I-NEXT:    sw zero, 0(sp)
688; RV32I-NEXT:    bne sp, t1, .LBB11_1
689; RV32I-NEXT:  # %bb.2:
690; RV32I-NEXT:    addi sp, sp, -2048
691; RV32I-NEXT:    addi sp, sp, -16
692; RV32I-NEXT:    sw zero, 0(sp)
693; RV32I-NEXT:    srli a2, sp, 15
694; RV32I-NEXT:    slli sp, a2, 15
695; RV32I-NEXT:    mv s1, sp
696; RV32I-NEXT:    slli a1, a1, 2
697; RV32I-NEXT:    lui a2, 8
698; RV32I-NEXT:    add a2, s1, a2
699; RV32I-NEXT:    add a1, a2, a1
700; RV32I-NEXT:    li a2, 1
701; RV32I-NEXT:    addi a0, a0, 15
702; RV32I-NEXT:    andi a0, a0, -16
703; RV32I-NEXT:    sw a2, 0(a1)
704; RV32I-NEXT:    sub a0, sp, a0
705; RV32I-NEXT:    andi a0, a0, -2048
706; RV32I-NEXT:    lui a1, 1
707; RV32I-NEXT:  .LBB11_3: # =>This Inner Loop Header: Depth=1
708; RV32I-NEXT:    sub sp, sp, a1
709; RV32I-NEXT:    sw zero, 0(sp)
710; RV32I-NEXT:    blt a0, sp, .LBB11_3
711; RV32I-NEXT:  # %bb.4:
712; RV32I-NEXT:    mv sp, a0
713; RV32I-NEXT:    lbu zero, 0(a0)
714; RV32I-NEXT:    addi sp, s0, -2032
715; RV32I-NEXT:    .cfi_def_cfa sp, 2032
716; RV32I-NEXT:    lw ra, 2028(sp) # 4-byte Folded Reload
717; RV32I-NEXT:    lw s0, 2024(sp) # 4-byte Folded Reload
718; RV32I-NEXT:    lw s1, 2020(sp) # 4-byte Folded Reload
719; RV32I-NEXT:    .cfi_restore ra
720; RV32I-NEXT:    .cfi_restore s0
721; RV32I-NEXT:    .cfi_restore s1
722; RV32I-NEXT:    addi sp, sp, 2032
723; RV32I-NEXT:    .cfi_def_cfa_offset 0
724; RV32I-NEXT:    ret
725  %a = alloca i32, i32 4096, align 32768
726  %b = getelementptr inbounds i32, ptr %a, i64 %i
727  store volatile i32 1, ptr %b
728  %1 = zext i32 %vla_size to i64
729  %vla = alloca i8, i64 %1, align 2048
730  %2 = load volatile i8, ptr %vla, align 2048
731  ret void
732}
733
734attributes #0 = { "probe-stack"="inline-asm" }
735