xref: /llvm-project/llvm/test/CodeGen/RISCV/ssub_sat.ll (revision 8ed046fc15eae08a9cf7ec02974330d52606c663) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=riscv32 -mattr=+m | FileCheck %s --check-prefixes=RV32,RV32I
3; RUN: llc < %s -mtriple=riscv64 -mattr=+m | FileCheck %s --check-prefixes=RV64,RV64I
4; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+zbb | FileCheck %s --check-prefixes=RV32,RV32IZbb
5; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+zbb | FileCheck %s --check-prefixes=RV64,RV64IZbb
6
7declare i4 @llvm.ssub.sat.i4(i4, i4)
8declare i8 @llvm.ssub.sat.i8(i8, i8)
9declare i16 @llvm.ssub.sat.i16(i16, i16)
10declare i32 @llvm.ssub.sat.i32(i32, i32)
11declare i64 @llvm.ssub.sat.i64(i64, i64)
12
13define signext i32 @func(i32 signext %x, i32 signext %y) nounwind {
14; RV32-LABEL: func:
15; RV32:       # %bb.0:
16; RV32-NEXT:    mv a2, a0
17; RV32-NEXT:    sgtz a3, a1
18; RV32-NEXT:    sub a0, a0, a1
19; RV32-NEXT:    slt a1, a0, a2
20; RV32-NEXT:    beq a3, a1, .LBB0_2
21; RV32-NEXT:  # %bb.1:
22; RV32-NEXT:    srai a0, a0, 31
23; RV32-NEXT:    lui a1, 524288
24; RV32-NEXT:    xor a0, a0, a1
25; RV32-NEXT:  .LBB0_2:
26; RV32-NEXT:    ret
27;
28; RV64I-LABEL: func:
29; RV64I:       # %bb.0:
30; RV64I-NEXT:    sub a2, a0, a1
31; RV64I-NEXT:    subw a0, a0, a1
32; RV64I-NEXT:    beq a0, a2, .LBB0_2
33; RV64I-NEXT:  # %bb.1:
34; RV64I-NEXT:    srli a0, a0, 31
35; RV64I-NEXT:    li a1, 1
36; RV64I-NEXT:    slli a1, a1, 31
37; RV64I-NEXT:    xor a2, a0, a1
38; RV64I-NEXT:  .LBB0_2:
39; RV64I-NEXT:    sext.w a0, a2
40; RV64I-NEXT:    ret
41;
42; RV64IZbb-LABEL: func:
43; RV64IZbb:       # %bb.0:
44; RV64IZbb-NEXT:    sub a0, a0, a1
45; RV64IZbb-NEXT:    lui a1, 524288
46; RV64IZbb-NEXT:    addiw a2, a1, -1
47; RV64IZbb-NEXT:    min a0, a0, a2
48; RV64IZbb-NEXT:    max a0, a0, a1
49; RV64IZbb-NEXT:    ret
50  %tmp = call i32 @llvm.ssub.sat.i32(i32 %x, i32 %y);
51  ret i32 %tmp;
52}
53
54define i64 @func2(i64 %x, i64 %y) nounwind {
55; RV32-LABEL: func2:
56; RV32:       # %bb.0:
57; RV32-NEXT:    mv a4, a1
58; RV32-NEXT:    sltu a1, a0, a2
59; RV32-NEXT:    sub a5, a4, a3
60; RV32-NEXT:    sub a1, a5, a1
61; RV32-NEXT:    xor a5, a4, a1
62; RV32-NEXT:    xor a3, a4, a3
63; RV32-NEXT:    and a3, a3, a5
64; RV32-NEXT:    bltz a3, .LBB1_2
65; RV32-NEXT:  # %bb.1:
66; RV32-NEXT:    sub a0, a0, a2
67; RV32-NEXT:    ret
68; RV32-NEXT:  .LBB1_2:
69; RV32-NEXT:    srai a0, a1, 31
70; RV32-NEXT:    lui a1, 524288
71; RV32-NEXT:    xor a1, a0, a1
72; RV32-NEXT:    ret
73;
74; RV64-LABEL: func2:
75; RV64:       # %bb.0:
76; RV64-NEXT:    mv a2, a0
77; RV64-NEXT:    sgtz a3, a1
78; RV64-NEXT:    sub a0, a0, a1
79; RV64-NEXT:    slt a1, a0, a2
80; RV64-NEXT:    beq a3, a1, .LBB1_2
81; RV64-NEXT:  # %bb.1:
82; RV64-NEXT:    srai a0, a0, 63
83; RV64-NEXT:    li a1, -1
84; RV64-NEXT:    slli a1, a1, 63
85; RV64-NEXT:    xor a0, a0, a1
86; RV64-NEXT:  .LBB1_2:
87; RV64-NEXT:    ret
88  %tmp = call i64 @llvm.ssub.sat.i64(i64 %x, i64 %y);
89  ret i64 %tmp;
90}
91
92define signext i16 @func16(i16 signext %x, i16 signext %y) nounwind {
93; RV32I-LABEL: func16:
94; RV32I:       # %bb.0:
95; RV32I-NEXT:    sub a0, a0, a1
96; RV32I-NEXT:    lui a1, 8
97; RV32I-NEXT:    addi a1, a1, -1
98; RV32I-NEXT:    bge a0, a1, .LBB2_3
99; RV32I-NEXT:  # %bb.1:
100; RV32I-NEXT:    lui a1, 1048568
101; RV32I-NEXT:    bge a1, a0, .LBB2_4
102; RV32I-NEXT:  .LBB2_2:
103; RV32I-NEXT:    ret
104; RV32I-NEXT:  .LBB2_3:
105; RV32I-NEXT:    mv a0, a1
106; RV32I-NEXT:    lui a1, 1048568
107; RV32I-NEXT:    blt a1, a0, .LBB2_2
108; RV32I-NEXT:  .LBB2_4:
109; RV32I-NEXT:    lui a0, 1048568
110; RV32I-NEXT:    ret
111;
112; RV64I-LABEL: func16:
113; RV64I:       # %bb.0:
114; RV64I-NEXT:    sub a0, a0, a1
115; RV64I-NEXT:    lui a1, 8
116; RV64I-NEXT:    addiw a1, a1, -1
117; RV64I-NEXT:    bge a0, a1, .LBB2_3
118; RV64I-NEXT:  # %bb.1:
119; RV64I-NEXT:    lui a1, 1048568
120; RV64I-NEXT:    bge a1, a0, .LBB2_4
121; RV64I-NEXT:  .LBB2_2:
122; RV64I-NEXT:    ret
123; RV64I-NEXT:  .LBB2_3:
124; RV64I-NEXT:    mv a0, a1
125; RV64I-NEXT:    lui a1, 1048568
126; RV64I-NEXT:    blt a1, a0, .LBB2_2
127; RV64I-NEXT:  .LBB2_4:
128; RV64I-NEXT:    lui a0, 1048568
129; RV64I-NEXT:    ret
130;
131; RV32IZbb-LABEL: func16:
132; RV32IZbb:       # %bb.0:
133; RV32IZbb-NEXT:    sub a0, a0, a1
134; RV32IZbb-NEXT:    lui a1, 8
135; RV32IZbb-NEXT:    addi a1, a1, -1
136; RV32IZbb-NEXT:    min a0, a0, a1
137; RV32IZbb-NEXT:    lui a1, 1048568
138; RV32IZbb-NEXT:    max a0, a0, a1
139; RV32IZbb-NEXT:    ret
140;
141; RV64IZbb-LABEL: func16:
142; RV64IZbb:       # %bb.0:
143; RV64IZbb-NEXT:    sub a0, a0, a1
144; RV64IZbb-NEXT:    lui a1, 8
145; RV64IZbb-NEXT:    addiw a1, a1, -1
146; RV64IZbb-NEXT:    min a0, a0, a1
147; RV64IZbb-NEXT:    lui a1, 1048568
148; RV64IZbb-NEXT:    max a0, a0, a1
149; RV64IZbb-NEXT:    ret
150  %tmp = call i16 @llvm.ssub.sat.i16(i16 %x, i16 %y);
151  ret i16 %tmp;
152}
153
154define signext i8 @func8(i8 signext %x, i8 signext %y) nounwind {
155; RV32I-LABEL: func8:
156; RV32I:       # %bb.0:
157; RV32I-NEXT:    sub a0, a0, a1
158; RV32I-NEXT:    li a1, 127
159; RV32I-NEXT:    bge a0, a1, .LBB3_3
160; RV32I-NEXT:  # %bb.1:
161; RV32I-NEXT:    li a1, -128
162; RV32I-NEXT:    bge a1, a0, .LBB3_4
163; RV32I-NEXT:  .LBB3_2:
164; RV32I-NEXT:    ret
165; RV32I-NEXT:  .LBB3_3:
166; RV32I-NEXT:    li a0, 127
167; RV32I-NEXT:    li a1, -128
168; RV32I-NEXT:    blt a1, a0, .LBB3_2
169; RV32I-NEXT:  .LBB3_4:
170; RV32I-NEXT:    li a0, -128
171; RV32I-NEXT:    ret
172;
173; RV64I-LABEL: func8:
174; RV64I:       # %bb.0:
175; RV64I-NEXT:    sub a0, a0, a1
176; RV64I-NEXT:    li a1, 127
177; RV64I-NEXT:    bge a0, a1, .LBB3_3
178; RV64I-NEXT:  # %bb.1:
179; RV64I-NEXT:    li a1, -128
180; RV64I-NEXT:    bge a1, a0, .LBB3_4
181; RV64I-NEXT:  .LBB3_2:
182; RV64I-NEXT:    ret
183; RV64I-NEXT:  .LBB3_3:
184; RV64I-NEXT:    li a0, 127
185; RV64I-NEXT:    li a1, -128
186; RV64I-NEXT:    blt a1, a0, .LBB3_2
187; RV64I-NEXT:  .LBB3_4:
188; RV64I-NEXT:    li a0, -128
189; RV64I-NEXT:    ret
190;
191; RV32IZbb-LABEL: func8:
192; RV32IZbb:       # %bb.0:
193; RV32IZbb-NEXT:    sub a0, a0, a1
194; RV32IZbb-NEXT:    li a1, 127
195; RV32IZbb-NEXT:    min a0, a0, a1
196; RV32IZbb-NEXT:    li a1, -128
197; RV32IZbb-NEXT:    max a0, a0, a1
198; RV32IZbb-NEXT:    ret
199;
200; RV64IZbb-LABEL: func8:
201; RV64IZbb:       # %bb.0:
202; RV64IZbb-NEXT:    sub a0, a0, a1
203; RV64IZbb-NEXT:    li a1, 127
204; RV64IZbb-NEXT:    min a0, a0, a1
205; RV64IZbb-NEXT:    li a1, -128
206; RV64IZbb-NEXT:    max a0, a0, a1
207; RV64IZbb-NEXT:    ret
208  %tmp = call i8 @llvm.ssub.sat.i8(i8 %x, i8 %y);
209  ret i8 %tmp;
210}
211
212define signext i4 @func3(i4 signext %x, i4 signext %y) nounwind {
213; RV32I-LABEL: func3:
214; RV32I:       # %bb.0:
215; RV32I-NEXT:    sub a0, a0, a1
216; RV32I-NEXT:    li a1, 7
217; RV32I-NEXT:    bge a0, a1, .LBB4_3
218; RV32I-NEXT:  # %bb.1:
219; RV32I-NEXT:    li a1, -8
220; RV32I-NEXT:    bge a1, a0, .LBB4_4
221; RV32I-NEXT:  .LBB4_2:
222; RV32I-NEXT:    ret
223; RV32I-NEXT:  .LBB4_3:
224; RV32I-NEXT:    li a0, 7
225; RV32I-NEXT:    li a1, -8
226; RV32I-NEXT:    blt a1, a0, .LBB4_2
227; RV32I-NEXT:  .LBB4_4:
228; RV32I-NEXT:    li a0, -8
229; RV32I-NEXT:    ret
230;
231; RV64I-LABEL: func3:
232; RV64I:       # %bb.0:
233; RV64I-NEXT:    sub a0, a0, a1
234; RV64I-NEXT:    li a1, 7
235; RV64I-NEXT:    bge a0, a1, .LBB4_3
236; RV64I-NEXT:  # %bb.1:
237; RV64I-NEXT:    li a1, -8
238; RV64I-NEXT:    bge a1, a0, .LBB4_4
239; RV64I-NEXT:  .LBB4_2:
240; RV64I-NEXT:    ret
241; RV64I-NEXT:  .LBB4_3:
242; RV64I-NEXT:    li a0, 7
243; RV64I-NEXT:    li a1, -8
244; RV64I-NEXT:    blt a1, a0, .LBB4_2
245; RV64I-NEXT:  .LBB4_4:
246; RV64I-NEXT:    li a0, -8
247; RV64I-NEXT:    ret
248;
249; RV32IZbb-LABEL: func3:
250; RV32IZbb:       # %bb.0:
251; RV32IZbb-NEXT:    sub a0, a0, a1
252; RV32IZbb-NEXT:    li a1, 7
253; RV32IZbb-NEXT:    min a0, a0, a1
254; RV32IZbb-NEXT:    li a1, -8
255; RV32IZbb-NEXT:    max a0, a0, a1
256; RV32IZbb-NEXT:    ret
257;
258; RV64IZbb-LABEL: func3:
259; RV64IZbb:       # %bb.0:
260; RV64IZbb-NEXT:    sub a0, a0, a1
261; RV64IZbb-NEXT:    li a1, 7
262; RV64IZbb-NEXT:    min a0, a0, a1
263; RV64IZbb-NEXT:    li a1, -8
264; RV64IZbb-NEXT:    max a0, a0, a1
265; RV64IZbb-NEXT:    ret
266  %tmp = call i4 @llvm.ssub.sat.i4(i4 %x, i4 %y);
267  ret i4 %tmp;
268}
269