xref: /llvm-project/llvm/test/CodeGen/RISCV/split-urem-by-constant.ll (revision 9122c5235ec85ce0c0ad337e862b006e7b349d84) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: sed 's/iXLen2/i64/g' %s | llc -mtriple=riscv32 -mattr=+m | \
3; RUN:   FileCheck %s --check-prefix=RV32
4; RUN: sed 's/iXLen2/i128/g' %s | llc -mtriple=riscv64 -mattr=+m | \
5; RUN:   FileCheck %s --check-prefix=RV64
6
7define iXLen2 @test_urem_3(iXLen2 %x) nounwind {
8; RV32-LABEL: test_urem_3:
9; RV32:       # %bb.0:
10; RV32-NEXT:    add a1, a0, a1
11; RV32-NEXT:    lui a2, 699051
12; RV32-NEXT:    sltu a0, a1, a0
13; RV32-NEXT:    addi a2, a2, -1365
14; RV32-NEXT:    add a0, a1, a0
15; RV32-NEXT:    mulhu a1, a0, a2
16; RV32-NEXT:    srli a2, a1, 1
17; RV32-NEXT:    andi a1, a1, -2
18; RV32-NEXT:    add a1, a1, a2
19; RV32-NEXT:    sub a0, a0, a1
20; RV32-NEXT:    li a1, 0
21; RV32-NEXT:    ret
22;
23; RV64-LABEL: test_urem_3:
24; RV64:       # %bb.0:
25; RV64-NEXT:    add a1, a0, a1
26; RV64-NEXT:    lui a2, 699051
27; RV64-NEXT:    sltu a0, a1, a0
28; RV64-NEXT:    addiw a2, a2, -1365
29; RV64-NEXT:    add a0, a1, a0
30; RV64-NEXT:    slli a1, a2, 32
31; RV64-NEXT:    add a1, a2, a1
32; RV64-NEXT:    mulhu a1, a0, a1
33; RV64-NEXT:    srli a2, a1, 1
34; RV64-NEXT:    andi a1, a1, -2
35; RV64-NEXT:    add a1, a1, a2
36; RV64-NEXT:    sub a0, a0, a1
37; RV64-NEXT:    li a1, 0
38; RV64-NEXT:    ret
39  %a = urem iXLen2 %x, 3
40  ret iXLen2 %a
41}
42
43define iXLen2 @test_urem_5(iXLen2 %x) nounwind {
44; RV32-LABEL: test_urem_5:
45; RV32:       # %bb.0:
46; RV32-NEXT:    add a1, a0, a1
47; RV32-NEXT:    lui a2, 838861
48; RV32-NEXT:    sltu a0, a1, a0
49; RV32-NEXT:    addi a2, a2, -819
50; RV32-NEXT:    add a0, a1, a0
51; RV32-NEXT:    mulhu a1, a0, a2
52; RV32-NEXT:    srli a2, a1, 2
53; RV32-NEXT:    andi a1, a1, -4
54; RV32-NEXT:    add a1, a1, a2
55; RV32-NEXT:    sub a0, a0, a1
56; RV32-NEXT:    li a1, 0
57; RV32-NEXT:    ret
58;
59; RV64-LABEL: test_urem_5:
60; RV64:       # %bb.0:
61; RV64-NEXT:    add a1, a0, a1
62; RV64-NEXT:    lui a2, 838861
63; RV64-NEXT:    sltu a0, a1, a0
64; RV64-NEXT:    addiw a2, a2, -819
65; RV64-NEXT:    add a0, a1, a0
66; RV64-NEXT:    slli a1, a2, 32
67; RV64-NEXT:    add a1, a2, a1
68; RV64-NEXT:    mulhu a1, a0, a1
69; RV64-NEXT:    srli a2, a1, 2
70; RV64-NEXT:    andi a1, a1, -4
71; RV64-NEXT:    add a1, a1, a2
72; RV64-NEXT:    sub a0, a0, a1
73; RV64-NEXT:    li a1, 0
74; RV64-NEXT:    ret
75  %a = urem iXLen2 %x, 5
76  ret iXLen2 %a
77}
78
79define iXLen2 @test_urem_7(iXLen2 %x) nounwind {
80; RV32-LABEL: test_urem_7:
81; RV32:       # %bb.0:
82; RV32-NEXT:    addi sp, sp, -16
83; RV32-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
84; RV32-NEXT:    li a2, 7
85; RV32-NEXT:    li a3, 0
86; RV32-NEXT:    call __umoddi3
87; RV32-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
88; RV32-NEXT:    addi sp, sp, 16
89; RV32-NEXT:    ret
90;
91; RV64-LABEL: test_urem_7:
92; RV64:       # %bb.0:
93; RV64-NEXT:    addi sp, sp, -16
94; RV64-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
95; RV64-NEXT:    li a2, 7
96; RV64-NEXT:    li a3, 0
97; RV64-NEXT:    call __umodti3
98; RV64-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
99; RV64-NEXT:    addi sp, sp, 16
100; RV64-NEXT:    ret
101  %a = urem iXLen2 %x, 7
102  ret iXLen2 %a
103}
104
105define iXLen2 @test_urem_9(iXLen2 %x) nounwind {
106; RV32-LABEL: test_urem_9:
107; RV32:       # %bb.0:
108; RV32-NEXT:    addi sp, sp, -16
109; RV32-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
110; RV32-NEXT:    li a2, 9
111; RV32-NEXT:    li a3, 0
112; RV32-NEXT:    call __umoddi3
113; RV32-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
114; RV32-NEXT:    addi sp, sp, 16
115; RV32-NEXT:    ret
116;
117; RV64-LABEL: test_urem_9:
118; RV64:       # %bb.0:
119; RV64-NEXT:    addi sp, sp, -16
120; RV64-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
121; RV64-NEXT:    li a2, 9
122; RV64-NEXT:    li a3, 0
123; RV64-NEXT:    call __umodti3
124; RV64-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
125; RV64-NEXT:    addi sp, sp, 16
126; RV64-NEXT:    ret
127  %a = urem iXLen2 %x, 9
128  ret iXLen2 %a
129}
130
131define iXLen2 @test_urem_15(iXLen2 %x) nounwind {
132; RV32-LABEL: test_urem_15:
133; RV32:       # %bb.0:
134; RV32-NEXT:    add a1, a0, a1
135; RV32-NEXT:    lui a2, 559241
136; RV32-NEXT:    sltu a0, a1, a0
137; RV32-NEXT:    add a0, a1, a0
138; RV32-NEXT:    addi a1, a2, -1911
139; RV32-NEXT:    mulhu a1, a0, a1
140; RV32-NEXT:    srli a1, a1, 3
141; RV32-NEXT:    slli a2, a1, 4
142; RV32-NEXT:    sub a1, a1, a2
143; RV32-NEXT:    add a0, a0, a1
144; RV32-NEXT:    li a1, 0
145; RV32-NEXT:    ret
146;
147; RV64-LABEL: test_urem_15:
148; RV64:       # %bb.0:
149; RV64-NEXT:    add a1, a0, a1
150; RV64-NEXT:    lui a2, 559241
151; RV64-NEXT:    sltu a0, a1, a0
152; RV64-NEXT:    addiw a2, a2, -1911
153; RV64-NEXT:    add a0, a1, a0
154; RV64-NEXT:    slli a1, a2, 32
155; RV64-NEXT:    add a1, a2, a1
156; RV64-NEXT:    mulhu a1, a0, a1
157; RV64-NEXT:    srli a1, a1, 3
158; RV64-NEXT:    slli a2, a1, 4
159; RV64-NEXT:    sub a1, a1, a2
160; RV64-NEXT:    add a0, a0, a1
161; RV64-NEXT:    li a1, 0
162; RV64-NEXT:    ret
163  %a = urem iXLen2 %x, 15
164  ret iXLen2 %a
165}
166
167define iXLen2 @test_urem_17(iXLen2 %x) nounwind {
168; RV32-LABEL: test_urem_17:
169; RV32:       # %bb.0:
170; RV32-NEXT:    add a1, a0, a1
171; RV32-NEXT:    lui a2, 986895
172; RV32-NEXT:    sltu a0, a1, a0
173; RV32-NEXT:    addi a2, a2, 241
174; RV32-NEXT:    add a0, a1, a0
175; RV32-NEXT:    mulhu a1, a0, a2
176; RV32-NEXT:    srli a2, a1, 4
177; RV32-NEXT:    andi a1, a1, -16
178; RV32-NEXT:    add a1, a1, a2
179; RV32-NEXT:    sub a0, a0, a1
180; RV32-NEXT:    li a1, 0
181; RV32-NEXT:    ret
182;
183; RV64-LABEL: test_urem_17:
184; RV64:       # %bb.0:
185; RV64-NEXT:    add a1, a0, a1
186; RV64-NEXT:    lui a2, 986895
187; RV64-NEXT:    sltu a0, a1, a0
188; RV64-NEXT:    addiw a2, a2, 241
189; RV64-NEXT:    add a0, a1, a0
190; RV64-NEXT:    slli a1, a2, 32
191; RV64-NEXT:    add a1, a2, a1
192; RV64-NEXT:    mulhu a1, a0, a1
193; RV64-NEXT:    srli a2, a1, 4
194; RV64-NEXT:    andi a1, a1, -16
195; RV64-NEXT:    add a1, a1, a2
196; RV64-NEXT:    sub a0, a0, a1
197; RV64-NEXT:    li a1, 0
198; RV64-NEXT:    ret
199  %a = urem iXLen2 %x, 17
200  ret iXLen2 %a
201}
202
203define iXLen2 @test_urem_255(iXLen2 %x) nounwind {
204; RV32-LABEL: test_urem_255:
205; RV32:       # %bb.0:
206; RV32-NEXT:    add a1, a0, a1
207; RV32-NEXT:    lui a2, 526344
208; RV32-NEXT:    sltu a0, a1, a0
209; RV32-NEXT:    add a0, a1, a0
210; RV32-NEXT:    addi a1, a2, 129
211; RV32-NEXT:    mulhu a1, a0, a1
212; RV32-NEXT:    srli a1, a1, 7
213; RV32-NEXT:    slli a2, a1, 8
214; RV32-NEXT:    sub a1, a1, a2
215; RV32-NEXT:    add a0, a0, a1
216; RV32-NEXT:    li a1, 0
217; RV32-NEXT:    ret
218;
219; RV64-LABEL: test_urem_255:
220; RV64:       # %bb.0:
221; RV64-NEXT:    add a1, a0, a1
222; RV64-NEXT:    lui a2, 526344
223; RV64-NEXT:    sltu a0, a1, a0
224; RV64-NEXT:    addiw a2, a2, 129
225; RV64-NEXT:    add a0, a1, a0
226; RV64-NEXT:    slli a1, a2, 32
227; RV64-NEXT:    add a1, a2, a1
228; RV64-NEXT:    mulhu a1, a0, a1
229; RV64-NEXT:    srli a1, a1, 7
230; RV64-NEXT:    slli a2, a1, 8
231; RV64-NEXT:    sub a1, a1, a2
232; RV64-NEXT:    add a0, a0, a1
233; RV64-NEXT:    li a1, 0
234; RV64-NEXT:    ret
235  %a = urem iXLen2 %x, 255
236  ret iXLen2 %a
237}
238
239define iXLen2 @test_urem_257(iXLen2 %x) nounwind {
240; RV32-LABEL: test_urem_257:
241; RV32:       # %bb.0:
242; RV32-NEXT:    add a1, a0, a1
243; RV32-NEXT:    lui a2, 1044496
244; RV32-NEXT:    sltu a0, a1, a0
245; RV32-NEXT:    addi a2, a2, -255
246; RV32-NEXT:    add a0, a1, a0
247; RV32-NEXT:    mulhu a1, a0, a2
248; RV32-NEXT:    srli a2, a1, 8
249; RV32-NEXT:    andi a1, a1, -256
250; RV32-NEXT:    add a1, a1, a2
251; RV32-NEXT:    sub a0, a0, a1
252; RV32-NEXT:    li a1, 0
253; RV32-NEXT:    ret
254;
255; RV64-LABEL: test_urem_257:
256; RV64:       # %bb.0:
257; RV64-NEXT:    add a1, a0, a1
258; RV64-NEXT:    lui a2, 1044496
259; RV64-NEXT:    sltu a0, a1, a0
260; RV64-NEXT:    addiw a2, a2, -255
261; RV64-NEXT:    add a0, a1, a0
262; RV64-NEXT:    slli a1, a2, 32
263; RV64-NEXT:    add a1, a2, a1
264; RV64-NEXT:    mulhu a1, a0, a1
265; RV64-NEXT:    srli a2, a1, 8
266; RV64-NEXT:    andi a1, a1, -256
267; RV64-NEXT:    add a1, a1, a2
268; RV64-NEXT:    sub a0, a0, a1
269; RV64-NEXT:    li a1, 0
270; RV64-NEXT:    ret
271  %a = urem iXLen2 %x, 257
272  ret iXLen2 %a
273}
274
275define iXLen2 @test_urem_65535(iXLen2 %x) nounwind {
276; RV32-LABEL: test_urem_65535:
277; RV32:       # %bb.0:
278; RV32-NEXT:    add a1, a0, a1
279; RV32-NEXT:    lui a2, 524296
280; RV32-NEXT:    sltu a0, a1, a0
281; RV32-NEXT:    add a0, a1, a0
282; RV32-NEXT:    addi a2, a2, 1
283; RV32-NEXT:    mulhu a1, a0, a2
284; RV32-NEXT:    srli a1, a1, 15
285; RV32-NEXT:    slli a2, a1, 16
286; RV32-NEXT:    sub a1, a1, a2
287; RV32-NEXT:    add a0, a0, a1
288; RV32-NEXT:    li a1, 0
289; RV32-NEXT:    ret
290;
291; RV64-LABEL: test_urem_65535:
292; RV64:       # %bb.0:
293; RV64-NEXT:    add a1, a0, a1
294; RV64-NEXT:    lui a2, 524296
295; RV64-NEXT:    sltu a0, a1, a0
296; RV64-NEXT:    addiw a2, a2, 1
297; RV64-NEXT:    add a0, a1, a0
298; RV64-NEXT:    slli a1, a2, 32
299; RV64-NEXT:    add a1, a2, a1
300; RV64-NEXT:    mulhu a1, a0, a1
301; RV64-NEXT:    srli a1, a1, 15
302; RV64-NEXT:    slli a2, a1, 16
303; RV64-NEXT:    sub a1, a1, a2
304; RV64-NEXT:    add a0, a0, a1
305; RV64-NEXT:    li a1, 0
306; RV64-NEXT:    ret
307  %a = urem iXLen2 %x, 65535
308  ret iXLen2 %a
309}
310
311define iXLen2 @test_urem_65537(iXLen2 %x) nounwind {
312; RV32-LABEL: test_urem_65537:
313; RV32:       # %bb.0:
314; RV32-NEXT:    add a1, a0, a1
315; RV32-NEXT:    lui a2, 1048560
316; RV32-NEXT:    sltu a0, a1, a0
317; RV32-NEXT:    add a0, a1, a0
318; RV32-NEXT:    addi a1, a2, 1
319; RV32-NEXT:    mulhu a1, a0, a1
320; RV32-NEXT:    and a2, a1, a2
321; RV32-NEXT:    srli a1, a1, 16
322; RV32-NEXT:    or a1, a2, a1
323; RV32-NEXT:    sub a0, a0, a1
324; RV32-NEXT:    li a1, 0
325; RV32-NEXT:    ret
326;
327; RV64-LABEL: test_urem_65537:
328; RV64:       # %bb.0:
329; RV64-NEXT:    add a1, a0, a1
330; RV64-NEXT:    lui a2, 1048560
331; RV64-NEXT:    sltu a0, a1, a0
332; RV64-NEXT:    addiw a3, a2, 1
333; RV64-NEXT:    add a0, a1, a0
334; RV64-NEXT:    slli a1, a3, 32
335; RV64-NEXT:    add a1, a3, a1
336; RV64-NEXT:    mulhu a1, a0, a1
337; RV64-NEXT:    and a2, a1, a2
338; RV64-NEXT:    srli a1, a1, 16
339; RV64-NEXT:    add a1, a2, a1
340; RV64-NEXT:    sub a0, a0, a1
341; RV64-NEXT:    li a1, 0
342; RV64-NEXT:    ret
343  %a = urem iXLen2 %x, 65537
344  ret iXLen2 %a
345}
346
347define iXLen2 @test_urem_12(iXLen2 %x) nounwind {
348; RV32-LABEL: test_urem_12:
349; RV32:       # %bb.0:
350; RV32-NEXT:    slli a2, a1, 30
351; RV32-NEXT:    srli a3, a0, 2
352; RV32-NEXT:    srli a1, a1, 2
353; RV32-NEXT:    or a2, a3, a2
354; RV32-NEXT:    lui a3, 699051
355; RV32-NEXT:    addi a3, a3, -1365
356; RV32-NEXT:    add a1, a2, a1
357; RV32-NEXT:    sltu a2, a1, a2
358; RV32-NEXT:    add a1, a1, a2
359; RV32-NEXT:    mulhu a2, a1, a3
360; RV32-NEXT:    srli a3, a2, 1
361; RV32-NEXT:    andi a2, a2, -2
362; RV32-NEXT:    add a2, a2, a3
363; RV32-NEXT:    sub a1, a1, a2
364; RV32-NEXT:    slli a1, a1, 2
365; RV32-NEXT:    andi a0, a0, 3
366; RV32-NEXT:    or a0, a1, a0
367; RV32-NEXT:    li a1, 0
368; RV32-NEXT:    ret
369;
370; RV64-LABEL: test_urem_12:
371; RV64:       # %bb.0:
372; RV64-NEXT:    slli a2, a1, 62
373; RV64-NEXT:    srli a3, a0, 2
374; RV64-NEXT:    lui a4, 699051
375; RV64-NEXT:    or a2, a3, a2
376; RV64-NEXT:    addiw a3, a4, -1365
377; RV64-NEXT:    slli a4, a3, 32
378; RV64-NEXT:    add a3, a3, a4
379; RV64-NEXT:    srli a1, a1, 2
380; RV64-NEXT:    add a1, a2, a1
381; RV64-NEXT:    sltu a2, a1, a2
382; RV64-NEXT:    add a1, a1, a2
383; RV64-NEXT:    mulhu a2, a1, a3
384; RV64-NEXT:    srli a3, a2, 1
385; RV64-NEXT:    andi a2, a2, -2
386; RV64-NEXT:    add a2, a2, a3
387; RV64-NEXT:    sub a1, a1, a2
388; RV64-NEXT:    slli a1, a1, 2
389; RV64-NEXT:    andi a0, a0, 3
390; RV64-NEXT:    or a0, a1, a0
391; RV64-NEXT:    li a1, 0
392; RV64-NEXT:    ret
393  %a = urem iXLen2 %x, 12
394  ret iXLen2 %a
395}
396