xref: /llvm-project/llvm/test/CodeGen/RISCV/split-store.ll (revision 2967e5f8007d873a3e9d97870d2461d0827a3976) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
3; RUN:   | FileCheck %s -check-prefixes=RV32-RV64,RV32
4; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \
5; RUN:   | FileCheck %s -check-prefixes=RV32D-RV64D,RV32D
6; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
7; RUN:   | FileCheck %s -check-prefixes=RV32-RV64,RV64
8; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \
9; RUN:   | FileCheck %s -check-prefixes=RV32D-RV64D,RV64D
10
11define void @int32_float_pair(i32 %tmp1, float %tmp2, ptr %ref.tmp) {
12; RV32-RV64-LABEL: int32_float_pair:
13; RV32-RV64:       # %bb.0:
14; RV32-RV64-NEXT:    sw a0, 0(a2)
15; RV32-RV64-NEXT:    sw a1, 4(a2)
16; RV32-RV64-NEXT:    ret
17;
18; RV32D-RV64D-LABEL: int32_float_pair:
19; RV32D-RV64D:       # %bb.0:
20; RV32D-RV64D-NEXT:    sw a0, 0(a1)
21; RV32D-RV64D-NEXT:    fsw fa0, 4(a1)
22; RV32D-RV64D-NEXT:    ret
23  %t0 = bitcast float %tmp2 to i32
24  %t1 = zext i32 %t0 to i64
25  %t2 = shl nuw i64 %t1, 32
26  %t3 = zext i32 %tmp1 to i64
27  %t4 = or i64 %t2, %t3
28  store i64 %t4, ptr %ref.tmp, align 8
29  ret void
30}
31
32define void @float_int32_pair(float %tmp1, i32 %tmp2, ptr %ref.tmp) {
33; RV32-RV64-LABEL: float_int32_pair:
34; RV32-RV64:       # %bb.0:
35; RV32-RV64-NEXT:    sw a0, 0(a2)
36; RV32-RV64-NEXT:    sw a1, 4(a2)
37; RV32-RV64-NEXT:    ret
38;
39; RV32D-RV64D-LABEL: float_int32_pair:
40; RV32D-RV64D:       # %bb.0:
41; RV32D-RV64D-NEXT:    fsw fa0, 0(a1)
42; RV32D-RV64D-NEXT:    sw a0, 4(a1)
43; RV32D-RV64D-NEXT:    ret
44  %t0 = bitcast float %tmp1 to i32
45  %t1 = zext i32 %tmp2 to i64
46  %t2 = shl nuw i64 %t1, 32
47  %t3 = zext i32 %t0 to i64
48  %t4 = or i64 %t2, %t3
49  store i64 %t4, ptr %ref.tmp, align 8
50  ret void
51}
52
53define void @int16_float_pair(i16 signext %tmp1, float %tmp2, ptr %ref.tmp) {
54; RV32-LABEL: int16_float_pair:
55; RV32:       # %bb.0:
56; RV32-NEXT:    slli a0, a0, 16
57; RV32-NEXT:    srli a0, a0, 16
58; RV32-NEXT:    sw a0, 0(a2)
59; RV32-NEXT:    sw a1, 4(a2)
60; RV32-NEXT:    ret
61;
62; RV32D-LABEL: int16_float_pair:
63; RV32D:       # %bb.0:
64; RV32D-NEXT:    slli a0, a0, 16
65; RV32D-NEXT:    srli a0, a0, 16
66; RV32D-NEXT:    sw a0, 0(a1)
67; RV32D-NEXT:    fsw fa0, 4(a1)
68; RV32D-NEXT:    ret
69;
70; RV64-LABEL: int16_float_pair:
71; RV64:       # %bb.0:
72; RV64-NEXT:    slli a0, a0, 48
73; RV64-NEXT:    srli a0, a0, 48
74; RV64-NEXT:    sw a0, 0(a2)
75; RV64-NEXT:    sw a1, 4(a2)
76; RV64-NEXT:    ret
77;
78; RV64D-LABEL: int16_float_pair:
79; RV64D:       # %bb.0:
80; RV64D-NEXT:    slli a0, a0, 48
81; RV64D-NEXT:    srli a0, a0, 48
82; RV64D-NEXT:    sw a0, 0(a1)
83; RV64D-NEXT:    fsw fa0, 4(a1)
84; RV64D-NEXT:    ret
85  %t0 = bitcast float %tmp2 to i32
86  %t1 = zext i32 %t0 to i64
87  %t2 = shl nuw i64 %t1, 32
88  %t3 = zext i16 %tmp1 to i64
89  %t4 = or i64 %t2, %t3
90  store i64 %t4, ptr %ref.tmp, align 8
91  ret void
92}
93
94define void @int8_float_pair(i8 signext %tmp1, float %tmp2, ptr %ref.tmp) {
95; RV32-RV64-LABEL: int8_float_pair:
96; RV32-RV64:       # %bb.0:
97; RV32-RV64-NEXT:    andi a0, a0, 255
98; RV32-RV64-NEXT:    sw a0, 0(a2)
99; RV32-RV64-NEXT:    sw a1, 4(a2)
100; RV32-RV64-NEXT:    ret
101;
102; RV32D-RV64D-LABEL: int8_float_pair:
103; RV32D-RV64D:       # %bb.0:
104; RV32D-RV64D-NEXT:    andi a0, a0, 255
105; RV32D-RV64D-NEXT:    sw a0, 0(a1)
106; RV32D-RV64D-NEXT:    fsw fa0, 4(a1)
107; RV32D-RV64D-NEXT:    ret
108  %t0 = bitcast float %tmp2 to i32
109  %t1 = zext i32 %t0 to i64
110  %t2 = shl nuw i64 %t1, 32
111  %t3 = zext i8 %tmp1 to i64
112  %t4 = or i64 %t2, %t3
113  store i64 %t4, ptr %ref.tmp, align 8
114  ret void
115}
116
117define void @int32_int32_pair(i32 %tmp1, i32 %tmp2, ptr %ref.tmp) {
118; RV32-LABEL: int32_int32_pair:
119; RV32:       # %bb.0:
120; RV32-NEXT:    sw a0, 0(a2)
121; RV32-NEXT:    sw a1, 4(a2)
122; RV32-NEXT:    ret
123;
124; RV32D-LABEL: int32_int32_pair:
125; RV32D:       # %bb.0:
126; RV32D-NEXT:    sw a0, 0(a2)
127; RV32D-NEXT:    sw a1, 4(a2)
128; RV32D-NEXT:    ret
129;
130; RV64-LABEL: int32_int32_pair:
131; RV64:       # %bb.0:
132; RV64-NEXT:    slli a1, a1, 32
133; RV64-NEXT:    slli a0, a0, 32
134; RV64-NEXT:    srli a0, a0, 32
135; RV64-NEXT:    or a0, a1, a0
136; RV64-NEXT:    sd a0, 0(a2)
137; RV64-NEXT:    ret
138;
139; RV64D-LABEL: int32_int32_pair:
140; RV64D:       # %bb.0:
141; RV64D-NEXT:    slli a1, a1, 32
142; RV64D-NEXT:    slli a0, a0, 32
143; RV64D-NEXT:    srli a0, a0, 32
144; RV64D-NEXT:    or a0, a1, a0
145; RV64D-NEXT:    sd a0, 0(a2)
146; RV64D-NEXT:    ret
147  %t1 = zext i32 %tmp2 to i64
148  %t2 = shl nuw i64 %t1, 32
149  %t3 = zext i32 %tmp1 to i64
150  %t4 = or i64 %t2, %t3
151  store i64 %t4, ptr %ref.tmp, align 8
152  ret void
153}
154
155define void @mbb_int32_float_pair(i32 %tmp1, float %tmp2, ptr %ref.tmp) {
156; RV32-RV64-LABEL: mbb_int32_float_pair:
157; RV32-RV64:       # %bb.0: # %entry
158; RV32-RV64-NEXT:    sw a0, 0(a2)
159; RV32-RV64-NEXT:    sw a1, 4(a2)
160; RV32-RV64-NEXT:    ret
161;
162; RV32D-RV64D-LABEL: mbb_int32_float_pair:
163; RV32D-RV64D:       # %bb.0: # %entry
164; RV32D-RV64D-NEXT:    sw a0, 0(a1)
165; RV32D-RV64D-NEXT:    fsw fa0, 4(a1)
166; RV32D-RV64D-NEXT:    ret
167entry:
168  %t0 = bitcast float %tmp2 to i32
169  br label %next
170next:
171  %t1 = zext i32 %t0 to i64
172  %t2 = shl nuw i64 %t1, 32
173  %t3 = zext i32 %tmp1 to i64
174  %t4 = or i64 %t2, %t3
175  store i64 %t4, ptr %ref.tmp, align 8
176  ret void
177}
178
179define void @mbb_int32_float_multi_stores(i32 %tmp1, float %tmp2, ptr %ref.tmp, ptr %ref.tmp1, i1 %cmp) {
180; RV32-RV64-LABEL: mbb_int32_float_multi_stores:
181; RV32-RV64:       # %bb.0: # %entry
182; RV32-RV64-NEXT:    andi a4, a4, 1
183; RV32-RV64-NEXT:    sw a0, 0(a2)
184; RV32-RV64-NEXT:    sw a1, 4(a2)
185; RV32-RV64-NEXT:    beqz a4, .LBB6_2
186; RV32-RV64-NEXT:  # %bb.1: # %bb2
187; RV32-RV64-NEXT:    sw a0, 0(a3)
188; RV32-RV64-NEXT:    sw a1, 4(a3)
189; RV32-RV64-NEXT:  .LBB6_2: # %exitbb
190; RV32-RV64-NEXT:    ret
191;
192; RV32D-RV64D-LABEL: mbb_int32_float_multi_stores:
193; RV32D-RV64D:       # %bb.0: # %entry
194; RV32D-RV64D-NEXT:    andi a3, a3, 1
195; RV32D-RV64D-NEXT:    sw a0, 0(a1)
196; RV32D-RV64D-NEXT:    fsw fa0, 4(a1)
197; RV32D-RV64D-NEXT:    beqz a3, .LBB6_2
198; RV32D-RV64D-NEXT:  # %bb.1: # %bb2
199; RV32D-RV64D-NEXT:    sw a0, 0(a2)
200; RV32D-RV64D-NEXT:    fsw fa0, 4(a2)
201; RV32D-RV64D-NEXT:  .LBB6_2: # %exitbb
202; RV32D-RV64D-NEXT:    ret
203entry:
204  %t0 = bitcast float %tmp2 to i32
205  br label %bb1
206bb1:
207  %t1 = zext i32 %t0 to i64
208  %t2 = shl nuw i64 %t1, 32
209  %t3 = zext i32 %tmp1 to i64
210  %t4 = or i64 %t2, %t3
211  store i64 %t4, ptr %ref.tmp, align 8
212  br i1 %cmp, label %bb2, label %exitbb
213bb2:
214  store i64 %t4, ptr %ref.tmp1, align 8
215  br label %exitbb
216exitbb:
217  ret void
218}
219