xref: /llvm-project/llvm/test/CodeGen/RISCV/signbit-test.ll (revision 7d40ea85d5ea5cc837536f61e3b4f80ea69f14d0) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s | FileCheck -check-prefixes=RV32 %s
3; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s | FileCheck -check-prefixes=RV64 %s
4
5define i64 @test_clear_mask_i64_i32(i64 %x) nounwind {
6; RV32-LABEL: test_clear_mask_i64_i32:
7; RV32:       # %bb.0: # %entry
8; RV32-NEXT:    bltz a0, .LBB0_2
9; RV32-NEXT:  # %bb.1: # %t
10; RV32-NEXT:    li a1, 0
11; RV32-NEXT:    li a0, 42
12; RV32-NEXT:  .LBB0_2: # %f
13; RV32-NEXT:    ret
14;
15; RV64-LABEL: test_clear_mask_i64_i32:
16; RV64:       # %bb.0: # %entry
17; RV64-NEXT:    slli a1, a0, 32
18; RV64-NEXT:    bltz a1, .LBB0_2
19; RV64-NEXT:  # %bb.1: # %t
20; RV64-NEXT:    li a0, 42
21; RV64-NEXT:  .LBB0_2: # %f
22; RV64-NEXT:    ret
23entry:
24  %a = and i64 %x, 2147483648
25  %r = icmp eq i64 %a, 0
26  br i1 %r, label %t, label %f
27t:
28  br label %f
29f:
30  %ret = phi i64 [ %x, %entry], [ 42, %t]
31  ret i64 %ret
32}
33
34define i64 @test_set_mask_i64_i32(i64 %x) nounwind {
35; RV32-LABEL: test_set_mask_i64_i32:
36; RV32:       # %bb.0: # %entry
37; RV32-NEXT:    bgez a0, .LBB1_2
38; RV32-NEXT:  # %bb.1: # %t
39; RV32-NEXT:    li a1, 0
40; RV32-NEXT:    li a0, 42
41; RV32-NEXT:  .LBB1_2: # %f
42; RV32-NEXT:    ret
43;
44; RV64-LABEL: test_set_mask_i64_i32:
45; RV64:       # %bb.0: # %entry
46; RV64-NEXT:    slli a1, a0, 32
47; RV64-NEXT:    bgez a1, .LBB1_2
48; RV64-NEXT:  # %bb.1: # %t
49; RV64-NEXT:    li a0, 42
50; RV64-NEXT:  .LBB1_2: # %f
51; RV64-NEXT:    ret
52entry:
53  %a = and i64 %x, 2147483648
54  %r = icmp ne i64 %a, 0
55  br i1 %r, label %t, label %f
56t:
57  br label %f
58f:
59  %ret = phi i64 [ %x, %entry], [ 42, %t]
60  ret i64 %ret
61}
62
63define i64 @test_clear_mask_i64_i16(i64 %x) nounwind {
64; RV32-LABEL: test_clear_mask_i64_i16:
65; RV32:       # %bb.0: # %entry
66; RV32-NEXT:    slli a2, a0, 16
67; RV32-NEXT:    bltz a2, .LBB2_2
68; RV32-NEXT:  # %bb.1: # %t
69; RV32-NEXT:    li a1, 0
70; RV32-NEXT:    li a0, 42
71; RV32-NEXT:  .LBB2_2: # %f
72; RV32-NEXT:    ret
73;
74; RV64-LABEL: test_clear_mask_i64_i16:
75; RV64:       # %bb.0: # %entry
76; RV64-NEXT:    slli a1, a0, 48
77; RV64-NEXT:    bltz a1, .LBB2_2
78; RV64-NEXT:  # %bb.1: # %t
79; RV64-NEXT:    li a0, 42
80; RV64-NEXT:  .LBB2_2: # %f
81; RV64-NEXT:    ret
82entry:
83  %a = and i64 %x, 32768
84  %r = icmp eq i64 %a, 0
85  br i1 %r, label %t, label %f
86t:
87  br label %f
88f:
89  %ret = phi i64 [ %x, %entry], [ 42, %t]
90  ret i64 %ret
91}
92
93define i64 @test_set_mask_i64_i16(i64 %x) nounwind {
94; RV32-LABEL: test_set_mask_i64_i16:
95; RV32:       # %bb.0: # %entry
96; RV32-NEXT:    slli a2, a0, 16
97; RV32-NEXT:    bgez a2, .LBB3_2
98; RV32-NEXT:  # %bb.1: # %t
99; RV32-NEXT:    li a1, 0
100; RV32-NEXT:    li a0, 42
101; RV32-NEXT:  .LBB3_2: # %f
102; RV32-NEXT:    ret
103;
104; RV64-LABEL: test_set_mask_i64_i16:
105; RV64:       # %bb.0: # %entry
106; RV64-NEXT:    slli a1, a0, 48
107; RV64-NEXT:    bgez a1, .LBB3_2
108; RV64-NEXT:  # %bb.1: # %t
109; RV64-NEXT:    li a0, 42
110; RV64-NEXT:  .LBB3_2: # %f
111; RV64-NEXT:    ret
112entry:
113  %a = and i64 %x, 32768
114  %r = icmp ne i64 %a, 0
115  br i1 %r, label %t, label %f
116t:
117  br label %f
118f:
119  %ret = phi i64 [ %x, %entry], [ 42, %t]
120  ret i64 %ret
121}
122
123define i64 @test_clear_mask_i64_i8(i64 %x) nounwind {
124; RV32-LABEL: test_clear_mask_i64_i8:
125; RV32:       # %bb.0: # %entry
126; RV32-NEXT:    andi a2, a0, 128
127; RV32-NEXT:    bnez a2, .LBB4_2
128; RV32-NEXT:  # %bb.1: # %t
129; RV32-NEXT:    li a1, 0
130; RV32-NEXT:    li a0, 42
131; RV32-NEXT:  .LBB4_2: # %f
132; RV32-NEXT:    ret
133;
134; RV64-LABEL: test_clear_mask_i64_i8:
135; RV64:       # %bb.0: # %entry
136; RV64-NEXT:    andi a1, a0, 128
137; RV64-NEXT:    bnez a1, .LBB4_2
138; RV64-NEXT:  # %bb.1: # %t
139; RV64-NEXT:    li a0, 42
140; RV64-NEXT:  .LBB4_2: # %f
141; RV64-NEXT:    ret
142entry:
143  %a = and i64 %x, 128
144  %r = icmp eq i64 %a, 0
145  br i1 %r, label %t, label %f
146t:
147  br label %f
148f:
149  %ret = phi i64 [ %x, %entry], [ 42, %t]
150  ret i64 %ret
151}
152
153define i64 @test_set_mask_i64_i8(i64 %x) nounwind {
154; RV32-LABEL: test_set_mask_i64_i8:
155; RV32:       # %bb.0: # %entry
156; RV32-NEXT:    andi a2, a0, 128
157; RV32-NEXT:    beqz a2, .LBB5_2
158; RV32-NEXT:  # %bb.1: # %t
159; RV32-NEXT:    li a1, 0
160; RV32-NEXT:    li a0, 42
161; RV32-NEXT:  .LBB5_2: # %f
162; RV32-NEXT:    ret
163;
164; RV64-LABEL: test_set_mask_i64_i8:
165; RV64:       # %bb.0: # %entry
166; RV64-NEXT:    andi a1, a0, 128
167; RV64-NEXT:    beqz a1, .LBB5_2
168; RV64-NEXT:  # %bb.1: # %t
169; RV64-NEXT:    li a0, 42
170; RV64-NEXT:  .LBB5_2: # %f
171; RV64-NEXT:    ret
172entry:
173  %a = and i64 %x, 128
174  %r = icmp ne i64 %a, 0
175  br i1 %r, label %t, label %f
176t:
177  br label %f
178f:
179  %ret = phi i64 [ %x, %entry], [ 42, %t]
180  ret i64 %ret
181}
182
183define i32 @test_clear_mask_i32_i16(i32 %x) nounwind {
184; RV32-LABEL: test_clear_mask_i32_i16:
185; RV32:       # %bb.0: # %entry
186; RV32-NEXT:    slli a1, a0, 16
187; RV32-NEXT:    bltz a1, .LBB6_2
188; RV32-NEXT:  # %bb.1: # %t
189; RV32-NEXT:    li a0, 42
190; RV32-NEXT:  .LBB6_2: # %f
191; RV32-NEXT:    ret
192;
193; RV64-LABEL: test_clear_mask_i32_i16:
194; RV64:       # %bb.0: # %entry
195; RV64-NEXT:    slli a1, a0, 48
196; RV64-NEXT:    bltz a1, .LBB6_2
197; RV64-NEXT:  # %bb.1: # %t
198; RV64-NEXT:    li a0, 42
199; RV64-NEXT:  .LBB6_2: # %f
200; RV64-NEXT:    ret
201entry:
202  %a = and i32 %x, 32768
203  %r = icmp eq i32 %a, 0
204  br i1 %r, label %t, label %f
205t:
206  br label %f
207f:
208  %ret = phi i32 [ %x, %entry], [ 42, %t]
209  ret i32 %ret
210}
211
212define i32 @test_set_mask_i32_i16(i32 %x) nounwind {
213; RV32-LABEL: test_set_mask_i32_i16:
214; RV32:       # %bb.0: # %entry
215; RV32-NEXT:    slli a1, a0, 16
216; RV32-NEXT:    bgez a1, .LBB7_2
217; RV32-NEXT:  # %bb.1: # %t
218; RV32-NEXT:    li a0, 42
219; RV32-NEXT:  .LBB7_2: # %f
220; RV32-NEXT:    ret
221;
222; RV64-LABEL: test_set_mask_i32_i16:
223; RV64:       # %bb.0: # %entry
224; RV64-NEXT:    slli a1, a0, 48
225; RV64-NEXT:    bgez a1, .LBB7_2
226; RV64-NEXT:  # %bb.1: # %t
227; RV64-NEXT:    li a0, 42
228; RV64-NEXT:  .LBB7_2: # %f
229; RV64-NEXT:    ret
230entry:
231  %a = and i32 %x, 32768
232  %r = icmp ne i32 %a, 0
233  br i1 %r, label %t, label %f
234t:
235  br label %f
236f:
237  %ret = phi i32 [ %x, %entry], [ 42, %t]
238  ret i32 %ret
239}
240
241define i32 @test_clear_mask_i32_i8(i32 %x) nounwind {
242; RV32-LABEL: test_clear_mask_i32_i8:
243; RV32:       # %bb.0: # %entry
244; RV32-NEXT:    andi a1, a0, 128
245; RV32-NEXT:    bnez a1, .LBB8_2
246; RV32-NEXT:  # %bb.1: # %t
247; RV32-NEXT:    li a0, 42
248; RV32-NEXT:  .LBB8_2: # %f
249; RV32-NEXT:    ret
250;
251; RV64-LABEL: test_clear_mask_i32_i8:
252; RV64:       # %bb.0: # %entry
253; RV64-NEXT:    andi a1, a0, 128
254; RV64-NEXT:    bnez a1, .LBB8_2
255; RV64-NEXT:  # %bb.1: # %t
256; RV64-NEXT:    li a0, 42
257; RV64-NEXT:  .LBB8_2: # %f
258; RV64-NEXT:    ret
259entry:
260  %a = and i32 %x, 128
261  %r = icmp eq i32 %a, 0
262  br i1 %r, label %t, label %f
263t:
264  br label %f
265f:
266  %ret = phi i32 [ %x, %entry], [ 42, %t]
267  ret i32 %ret
268}
269
270define i32 @test_set_mask_i32_i8(i32 %x) nounwind {
271; RV32-LABEL: test_set_mask_i32_i8:
272; RV32:       # %bb.0: # %entry
273; RV32-NEXT:    andi a1, a0, 128
274; RV32-NEXT:    beqz a1, .LBB9_2
275; RV32-NEXT:  # %bb.1: # %t
276; RV32-NEXT:    li a0, 42
277; RV32-NEXT:  .LBB9_2: # %f
278; RV32-NEXT:    ret
279;
280; RV64-LABEL: test_set_mask_i32_i8:
281; RV64:       # %bb.0: # %entry
282; RV64-NEXT:    andi a1, a0, 128
283; RV64-NEXT:    beqz a1, .LBB9_2
284; RV64-NEXT:  # %bb.1: # %t
285; RV64-NEXT:    li a0, 42
286; RV64-NEXT:  .LBB9_2: # %f
287; RV64-NEXT:    ret
288entry:
289  %a = and i32 %x, 128
290  %r = icmp ne i32 %a, 0
291  br i1 %r, label %t, label %f
292t:
293  br label %f
294f:
295  %ret = phi i32 [ %x, %entry], [ 42, %t]
296  ret i32 %ret
297}
298
299define i16 @test_clear_mask_i16_i8(i16 %x) nounwind {
300; RV32-LABEL: test_clear_mask_i16_i8:
301; RV32:       # %bb.0: # %entry
302; RV32-NEXT:    andi a1, a0, 128
303; RV32-NEXT:    bnez a1, .LBB10_2
304; RV32-NEXT:  # %bb.1: # %t
305; RV32-NEXT:    li a0, 42
306; RV32-NEXT:    ret
307; RV32-NEXT:  .LBB10_2:
308; RV32-NEXT:    slli a0, a0, 16
309; RV32-NEXT:    srli a0, a0, 16
310; RV32-NEXT:    ret
311;
312; RV64-LABEL: test_clear_mask_i16_i8:
313; RV64:       # %bb.0: # %entry
314; RV64-NEXT:    andi a1, a0, 128
315; RV64-NEXT:    bnez a1, .LBB10_2
316; RV64-NEXT:  # %bb.1: # %t
317; RV64-NEXT:    li a0, 42
318; RV64-NEXT:    ret
319; RV64-NEXT:  .LBB10_2:
320; RV64-NEXT:    slli a0, a0, 48
321; RV64-NEXT:    srli a0, a0, 48
322; RV64-NEXT:    ret
323entry:
324  %a = and i16 %x, 128
325  %r = icmp eq i16 %a, 0
326  br i1 %r, label %t, label %f
327t:
328  br label %f
329f:
330  %ret = phi i16 [ %x, %entry], [ 42, %t]
331  ret i16 %ret
332}
333
334define i16 @test_set_mask_i16_i8(i16 %x) nounwind {
335; RV32-LABEL: test_set_mask_i16_i8:
336; RV32:       # %bb.0: # %entry
337; RV32-NEXT:    andi a1, a0, 128
338; RV32-NEXT:    beqz a1, .LBB11_2
339; RV32-NEXT:  # %bb.1: # %t
340; RV32-NEXT:    li a0, 42
341; RV32-NEXT:    ret
342; RV32-NEXT:  .LBB11_2:
343; RV32-NEXT:    slli a0, a0, 16
344; RV32-NEXT:    srli a0, a0, 16
345; RV32-NEXT:    ret
346;
347; RV64-LABEL: test_set_mask_i16_i8:
348; RV64:       # %bb.0: # %entry
349; RV64-NEXT:    andi a1, a0, 128
350; RV64-NEXT:    beqz a1, .LBB11_2
351; RV64-NEXT:  # %bb.1: # %t
352; RV64-NEXT:    li a0, 42
353; RV64-NEXT:    ret
354; RV64-NEXT:  .LBB11_2:
355; RV64-NEXT:    slli a0, a0, 48
356; RV64-NEXT:    srli a0, a0, 48
357; RV64-NEXT:    ret
358entry:
359  %a = and i16 %x, 128
360  %r = icmp ne i16 %a, 0
361  br i1 %r, label %t, label %f
362t:
363  br label %f
364f:
365  %ret = phi i16 [ %x, %entry], [ 42, %t]
366  ret i16 %ret
367}
368
369define i16 @test_set_mask_i16_i7(i16 %x) nounwind {
370; RV32-LABEL: test_set_mask_i16_i7:
371; RV32:       # %bb.0: # %entry
372; RV32-NEXT:    andi a1, a0, 64
373; RV32-NEXT:    beqz a1, .LBB12_2
374; RV32-NEXT:  # %bb.1: # %t
375; RV32-NEXT:    li a0, 42
376; RV32-NEXT:    ret
377; RV32-NEXT:  .LBB12_2:
378; RV32-NEXT:    slli a0, a0, 16
379; RV32-NEXT:    srli a0, a0, 16
380; RV32-NEXT:    ret
381;
382; RV64-LABEL: test_set_mask_i16_i7:
383; RV64:       # %bb.0: # %entry
384; RV64-NEXT:    andi a1, a0, 64
385; RV64-NEXT:    beqz a1, .LBB12_2
386; RV64-NEXT:  # %bb.1: # %t
387; RV64-NEXT:    li a0, 42
388; RV64-NEXT:    ret
389; RV64-NEXT:  .LBB12_2:
390; RV64-NEXT:    slli a0, a0, 48
391; RV64-NEXT:    srli a0, a0, 48
392; RV64-NEXT:    ret
393entry:
394  %a = and i16 %x, 64
395  %r = icmp ne i16 %a, 0
396  br i1 %r, label %t, label %f
397t:
398  br label %f
399f:
400  %ret = phi i16 [ %x, %entry], [ 42, %t]
401  ret i16 %ret
402}
403