xref: /llvm-project/llvm/test/CodeGen/RISCV/shlimm-addimm.ll (revision 9122c5235ec85ce0c0ad337e862b006e7b349d84) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2
3; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
4; RUN:   | FileCheck -check-prefix=RV32I %s
5; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
6; RUN:   | FileCheck -check-prefix=RV64I %s
7
8;; Test that (add (shl x, c0), c1) can be transformed to
9;; (add (shl (add x, c1>>c0), c0), c1-(c1>>c0<<c0)) or
10;; (shl (add x, c1>>c0), c0) if profitable.
11
12define i32 @shl5_add1184_a(i32 %x) {
13; RV32I-LABEL: shl5_add1184_a:
14; RV32I:       # %bb.0:
15; RV32I-NEXT:    slli a0, a0, 5
16; RV32I-NEXT:    addi a0, a0, 1184
17; RV32I-NEXT:    ret
18;
19; RV64I-LABEL: shl5_add1184_a:
20; RV64I:       # %bb.0:
21; RV64I-NEXT:    slli a0, a0, 5
22; RV64I-NEXT:    addiw a0, a0, 1184
23; RV64I-NEXT:    ret
24  %tmp0 = shl i32 %x, 5
25  %tmp1 = add i32 %tmp0, 1184
26  ret i32 %tmp1
27}
28
29define signext i32 @shl5_add1184_b(i32 signext %x) {
30; RV32I-LABEL: shl5_add1184_b:
31; RV32I:       # %bb.0:
32; RV32I-NEXT:    slli a0, a0, 5
33; RV32I-NEXT:    addi a0, a0, 1184
34; RV32I-NEXT:    ret
35;
36; RV64I-LABEL: shl5_add1184_b:
37; RV64I:       # %bb.0:
38; RV64I-NEXT:    slli a0, a0, 5
39; RV64I-NEXT:    addiw a0, a0, 1184
40; RV64I-NEXT:    ret
41  %tmp0 = shl i32 %x, 5
42  %tmp1 = add i32 %tmp0, 1184
43  ret i32 %tmp1
44}
45
46define i64 @shl5_add1184_c(i64 %x) {
47; RV32I-LABEL: shl5_add1184_c:
48; RV32I:       # %bb.0:
49; RV32I-NEXT:    srli a2, a0, 27
50; RV32I-NEXT:    slli a1, a1, 5
51; RV32I-NEXT:    slli a3, a0, 5
52; RV32I-NEXT:    or a1, a1, a2
53; RV32I-NEXT:    addi a0, a3, 1184
54; RV32I-NEXT:    sltu a2, a0, a3
55; RV32I-NEXT:    add a1, a1, a2
56; RV32I-NEXT:    ret
57;
58; RV64I-LABEL: shl5_add1184_c:
59; RV64I:       # %bb.0:
60; RV64I-NEXT:    slli a0, a0, 5
61; RV64I-NEXT:    addi a0, a0, 1184
62; RV64I-NEXT:    ret
63  %tmp0 = shl i64 %x, 5
64  %tmp1 = add i64 %tmp0, 1184
65  ret i64 %tmp1
66}
67
68define i32 @shl5_add101024_a(i32 %x) {
69; RV32I-LABEL: shl5_add101024_a:
70; RV32I:       # %bb.0:
71; RV32I-NEXT:    slli a0, a0, 5
72; RV32I-NEXT:    lui a1, 25
73; RV32I-NEXT:    addi a1, a1, -1376
74; RV32I-NEXT:    add a0, a0, a1
75; RV32I-NEXT:    ret
76;
77; RV64I-LABEL: shl5_add101024_a:
78; RV64I:       # %bb.0:
79; RV64I-NEXT:    slli a0, a0, 5
80; RV64I-NEXT:    lui a1, 25
81; RV64I-NEXT:    addi a1, a1, -1376
82; RV64I-NEXT:    addw a0, a0, a1
83; RV64I-NEXT:    ret
84  %tmp0 = shl i32 %x, 5
85  %tmp1 = add i32 %tmp0, 101024
86  ret i32 %tmp1
87}
88
89define signext i32 @shl5_add101024_b(i32 signext %x) {
90; RV32I-LABEL: shl5_add101024_b:
91; RV32I:       # %bb.0:
92; RV32I-NEXT:    slli a0, a0, 5
93; RV32I-NEXT:    lui a1, 25
94; RV32I-NEXT:    addi a1, a1, -1376
95; RV32I-NEXT:    add a0, a0, a1
96; RV32I-NEXT:    ret
97;
98; RV64I-LABEL: shl5_add101024_b:
99; RV64I:       # %bb.0:
100; RV64I-NEXT:    slli a0, a0, 5
101; RV64I-NEXT:    lui a1, 25
102; RV64I-NEXT:    addi a1, a1, -1376
103; RV64I-NEXT:    addw a0, a0, a1
104; RV64I-NEXT:    ret
105  %tmp0 = shl i32 %x, 5
106  %tmp1 = add i32 %tmp0, 101024
107  ret i32 %tmp1
108}
109
110define i64 @shl5_add101024_c(i64 %x) {
111; RV32I-LABEL: shl5_add101024_c:
112; RV32I:       # %bb.0:
113; RV32I-NEXT:    srli a2, a0, 27
114; RV32I-NEXT:    slli a1, a1, 5
115; RV32I-NEXT:    slli a3, a0, 5
116; RV32I-NEXT:    or a1, a1, a2
117; RV32I-NEXT:    lui a0, 25
118; RV32I-NEXT:    addi a0, a0, -1376
119; RV32I-NEXT:    add a0, a3, a0
120; RV32I-NEXT:    sltu a2, a0, a3
121; RV32I-NEXT:    add a1, a1, a2
122; RV32I-NEXT:    ret
123;
124; RV64I-LABEL: shl5_add101024_c:
125; RV64I:       # %bb.0:
126; RV64I-NEXT:    slli a0, a0, 5
127; RV64I-NEXT:    lui a1, 25
128; RV64I-NEXT:    addiw a1, a1, -1376
129; RV64I-NEXT:    add a0, a0, a1
130; RV64I-NEXT:    ret
131  %tmp0 = shl i64 %x, 5
132  %tmp1 = add i64 %tmp0, 101024
133  ret i64 %tmp1
134}
135
136define i32 @shl5_add47968_a(i32 %x) {
137; RV32I-LABEL: shl5_add47968_a:
138; RV32I:       # %bb.0:
139; RV32I-NEXT:    slli a0, a0, 5
140; RV32I-NEXT:    lui a1, 12
141; RV32I-NEXT:    addi a1, a1, -1184
142; RV32I-NEXT:    add a0, a0, a1
143; RV32I-NEXT:    ret
144;
145; RV64I-LABEL: shl5_add47968_a:
146; RV64I:       # %bb.0:
147; RV64I-NEXT:    slli a0, a0, 5
148; RV64I-NEXT:    lui a1, 12
149; RV64I-NEXT:    addi a1, a1, -1184
150; RV64I-NEXT:    addw a0, a0, a1
151; RV64I-NEXT:    ret
152  %tmp0 = shl i32 %x, 5
153  %tmp1 = add i32 %tmp0, 47968
154  ret i32 %tmp1
155}
156
157define signext i32 @shl5_add47968_b(i32 signext %x) {
158; RV32I-LABEL: shl5_add47968_b:
159; RV32I:       # %bb.0:
160; RV32I-NEXT:    slli a0, a0, 5
161; RV32I-NEXT:    lui a1, 12
162; RV32I-NEXT:    addi a1, a1, -1184
163; RV32I-NEXT:    add a0, a0, a1
164; RV32I-NEXT:    ret
165;
166; RV64I-LABEL: shl5_add47968_b:
167; RV64I:       # %bb.0:
168; RV64I-NEXT:    slli a0, a0, 5
169; RV64I-NEXT:    lui a1, 12
170; RV64I-NEXT:    addi a1, a1, -1184
171; RV64I-NEXT:    addw a0, a0, a1
172; RV64I-NEXT:    ret
173  %tmp0 = shl i32 %x, 5
174  %tmp1 = add i32 %tmp0, 47968
175  ret i32 %tmp1
176}
177
178define i64 @shl5_add47968_c(i64 %x) {
179; RV32I-LABEL: shl5_add47968_c:
180; RV32I:       # %bb.0:
181; RV32I-NEXT:    srli a2, a0, 27
182; RV32I-NEXT:    slli a1, a1, 5
183; RV32I-NEXT:    slli a3, a0, 5
184; RV32I-NEXT:    or a1, a1, a2
185; RV32I-NEXT:    lui a0, 12
186; RV32I-NEXT:    addi a0, a0, -1184
187; RV32I-NEXT:    add a0, a3, a0
188; RV32I-NEXT:    sltu a2, a0, a3
189; RV32I-NEXT:    add a1, a1, a2
190; RV32I-NEXT:    ret
191;
192; RV64I-LABEL: shl5_add47968_c:
193; RV64I:       # %bb.0:
194; RV64I-NEXT:    slli a0, a0, 5
195; RV64I-NEXT:    lui a1, 12
196; RV64I-NEXT:    addiw a1, a1, -1184
197; RV64I-NEXT:    add a0, a0, a1
198; RV64I-NEXT:    ret
199  %tmp0 = shl i64 %x, 5
200  %tmp1 = add i64 %tmp0, 47968
201  ret i64 %tmp1
202}
203
204define i32 @shl5_add47969_a(i32 %x) {
205; RV32I-LABEL: shl5_add47969_a:
206; RV32I:       # %bb.0:
207; RV32I-NEXT:    slli a0, a0, 5
208; RV32I-NEXT:    lui a1, 12
209; RV32I-NEXT:    addi a1, a1, -1183
210; RV32I-NEXT:    add a0, a0, a1
211; RV32I-NEXT:    ret
212;
213; RV64I-LABEL: shl5_add47969_a:
214; RV64I:       # %bb.0:
215; RV64I-NEXT:    slli a0, a0, 5
216; RV64I-NEXT:    lui a1, 12
217; RV64I-NEXT:    addi a1, a1, -1183
218; RV64I-NEXT:    addw a0, a0, a1
219; RV64I-NEXT:    ret
220  %tmp0 = shl i32 %x, 5
221  %tmp1 = add i32 %tmp0, 47969
222  ret i32 %tmp1
223}
224
225define signext i32 @shl5_add47969_b(i32 signext %x) {
226; RV32I-LABEL: shl5_add47969_b:
227; RV32I:       # %bb.0:
228; RV32I-NEXT:    slli a0, a0, 5
229; RV32I-NEXT:    lui a1, 12
230; RV32I-NEXT:    addi a1, a1, -1183
231; RV32I-NEXT:    add a0, a0, a1
232; RV32I-NEXT:    ret
233;
234; RV64I-LABEL: shl5_add47969_b:
235; RV64I:       # %bb.0:
236; RV64I-NEXT:    slli a0, a0, 5
237; RV64I-NEXT:    lui a1, 12
238; RV64I-NEXT:    addi a1, a1, -1183
239; RV64I-NEXT:    addw a0, a0, a1
240; RV64I-NEXT:    ret
241  %tmp0 = shl i32 %x, 5
242  %tmp1 = add i32 %tmp0, 47969
243  ret i32 %tmp1
244}
245
246define i64 @shl5_add47969_c(i64 %x) {
247; RV32I-LABEL: shl5_add47969_c:
248; RV32I:       # %bb.0:
249; RV32I-NEXT:    srli a2, a0, 27
250; RV32I-NEXT:    slli a1, a1, 5
251; RV32I-NEXT:    slli a3, a0, 5
252; RV32I-NEXT:    or a1, a1, a2
253; RV32I-NEXT:    lui a0, 12
254; RV32I-NEXT:    addi a0, a0, -1183
255; RV32I-NEXT:    add a0, a3, a0
256; RV32I-NEXT:    sltu a2, a0, a3
257; RV32I-NEXT:    add a1, a1, a2
258; RV32I-NEXT:    ret
259;
260; RV64I-LABEL: shl5_add47969_c:
261; RV64I:       # %bb.0:
262; RV64I-NEXT:    slli a0, a0, 5
263; RV64I-NEXT:    lui a1, 12
264; RV64I-NEXT:    addiw a1, a1, -1183
265; RV64I-NEXT:    add a0, a0, a1
266; RV64I-NEXT:    ret
267  %tmp0 = shl i64 %x, 5
268  %tmp1 = add i64 %tmp0, 47969
269  ret i64 %tmp1
270}
271
272define i32 @shl5_sub47968_a(i32 %x) {
273; RV32I-LABEL: shl5_sub47968_a:
274; RV32I:       # %bb.0:
275; RV32I-NEXT:    slli a0, a0, 5
276; RV32I-NEXT:    lui a1, 1048564
277; RV32I-NEXT:    addi a1, a1, 1184
278; RV32I-NEXT:    add a0, a0, a1
279; RV32I-NEXT:    ret
280;
281; RV64I-LABEL: shl5_sub47968_a:
282; RV64I:       # %bb.0:
283; RV64I-NEXT:    slli a0, a0, 5
284; RV64I-NEXT:    lui a1, 1048564
285; RV64I-NEXT:    addi a1, a1, 1184
286; RV64I-NEXT:    addw a0, a0, a1
287; RV64I-NEXT:    ret
288  %tmp0 = shl i32 %x, 5
289  %tmp1 = add i32 %tmp0, -47968
290  ret i32 %tmp1
291}
292
293define signext i32 @shl5_sub47968_b(i32 signext %x) {
294; RV32I-LABEL: shl5_sub47968_b:
295; RV32I:       # %bb.0:
296; RV32I-NEXT:    slli a0, a0, 5
297; RV32I-NEXT:    lui a1, 1048564
298; RV32I-NEXT:    addi a1, a1, 1184
299; RV32I-NEXT:    add a0, a0, a1
300; RV32I-NEXT:    ret
301;
302; RV64I-LABEL: shl5_sub47968_b:
303; RV64I:       # %bb.0:
304; RV64I-NEXT:    slli a0, a0, 5
305; RV64I-NEXT:    lui a1, 1048564
306; RV64I-NEXT:    addi a1, a1, 1184
307; RV64I-NEXT:    addw a0, a0, a1
308; RV64I-NEXT:    ret
309  %tmp0 = shl i32 %x, 5
310  %tmp1 = add i32 %tmp0, -47968
311  ret i32 %tmp1
312}
313
314define i64 @shl5_sub47968_c(i64 %x) {
315; RV32I-LABEL: shl5_sub47968_c:
316; RV32I:       # %bb.0:
317; RV32I-NEXT:    srli a2, a0, 27
318; RV32I-NEXT:    slli a1, a1, 5
319; RV32I-NEXT:    slli a3, a0, 5
320; RV32I-NEXT:    or a1, a1, a2
321; RV32I-NEXT:    lui a0, 1048564
322; RV32I-NEXT:    addi a0, a0, 1184
323; RV32I-NEXT:    add a0, a3, a0
324; RV32I-NEXT:    sltu a2, a0, a3
325; RV32I-NEXT:    add a1, a1, a2
326; RV32I-NEXT:    addi a1, a1, -1
327; RV32I-NEXT:    ret
328;
329; RV64I-LABEL: shl5_sub47968_c:
330; RV64I:       # %bb.0:
331; RV64I-NEXT:    slli a0, a0, 5
332; RV64I-NEXT:    lui a1, 1048564
333; RV64I-NEXT:    addiw a1, a1, 1184
334; RV64I-NEXT:    add a0, a0, a1
335; RV64I-NEXT:    ret
336  %tmp0 = shl i64 %x, 5
337  %tmp1 = add i64 %tmp0, -47968
338  ret i64 %tmp1
339}
340
341define i32 @shl5_sub47969_a(i32 %x) {
342; RV32I-LABEL: shl5_sub47969_a:
343; RV32I:       # %bb.0:
344; RV32I-NEXT:    slli a0, a0, 5
345; RV32I-NEXT:    lui a1, 1048564
346; RV32I-NEXT:    addi a1, a1, 1183
347; RV32I-NEXT:    add a0, a0, a1
348; RV32I-NEXT:    ret
349;
350; RV64I-LABEL: shl5_sub47969_a:
351; RV64I:       # %bb.0:
352; RV64I-NEXT:    slli a0, a0, 5
353; RV64I-NEXT:    lui a1, 1048564
354; RV64I-NEXT:    addi a1, a1, 1183
355; RV64I-NEXT:    addw a0, a0, a1
356; RV64I-NEXT:    ret
357  %tmp0 = shl i32 %x, 5
358  %tmp1 = add i32 %tmp0, -47969
359  ret i32 %tmp1
360}
361
362define signext i32 @shl5_sub47969_b(i32 signext %x) {
363; RV32I-LABEL: shl5_sub47969_b:
364; RV32I:       # %bb.0:
365; RV32I-NEXT:    slli a0, a0, 5
366; RV32I-NEXT:    lui a1, 1048564
367; RV32I-NEXT:    addi a1, a1, 1183
368; RV32I-NEXT:    add a0, a0, a1
369; RV32I-NEXT:    ret
370;
371; RV64I-LABEL: shl5_sub47969_b:
372; RV64I:       # %bb.0:
373; RV64I-NEXT:    slli a0, a0, 5
374; RV64I-NEXT:    lui a1, 1048564
375; RV64I-NEXT:    addi a1, a1, 1183
376; RV64I-NEXT:    addw a0, a0, a1
377; RV64I-NEXT:    ret
378  %tmp0 = shl i32 %x, 5
379  %tmp1 = add i32 %tmp0, -47969
380  ret i32 %tmp1
381}
382
383define i64 @shl5_sub47969_c(i64 %x) {
384; RV32I-LABEL: shl5_sub47969_c:
385; RV32I:       # %bb.0:
386; RV32I-NEXT:    srli a2, a0, 27
387; RV32I-NEXT:    slli a1, a1, 5
388; RV32I-NEXT:    slli a3, a0, 5
389; RV32I-NEXT:    or a1, a1, a2
390; RV32I-NEXT:    lui a0, 1048564
391; RV32I-NEXT:    addi a0, a0, 1183
392; RV32I-NEXT:    add a0, a3, a0
393; RV32I-NEXT:    sltu a2, a0, a3
394; RV32I-NEXT:    add a1, a1, a2
395; RV32I-NEXT:    addi a1, a1, -1
396; RV32I-NEXT:    ret
397;
398; RV64I-LABEL: shl5_sub47969_c:
399; RV64I:       # %bb.0:
400; RV64I-NEXT:    slli a0, a0, 5
401; RV64I-NEXT:    lui a1, 1048564
402; RV64I-NEXT:    addiw a1, a1, 1183
403; RV64I-NEXT:    add a0, a0, a1
404; RV64I-NEXT:    ret
405  %tmp0 = shl i64 %x, 5
406  %tmp1 = add i64 %tmp0, -47969
407  ret i64 %tmp1
408}
409