xref: /llvm-project/llvm/test/CodeGen/RISCV/shift-and.ll (revision 9122c5235ec85ce0c0ad337e862b006e7b349d84) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
3; RUN:   | FileCheck %s -check-prefix=RV32I
4; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
5; RUN:   | FileCheck %s -check-prefix=RV64I
6
7; Test for handling of AND with constant followed by a shift by constant. Often
8; we can replace these with a pair of shifts to avoid materializing a constant
9; for the and.
10
11define i32 @test1(i32 %x) {
12; RV32I-LABEL: test1:
13; RV32I:       # %bb.0:
14; RV32I-NEXT:    srli a0, a0, 5
15; RV32I-NEXT:    andi a0, a0, -8
16; RV32I-NEXT:    ret
17;
18; RV64I-LABEL: test1:
19; RV64I:       # %bb.0:
20; RV64I-NEXT:    srliw a0, a0, 8
21; RV64I-NEXT:    slli a0, a0, 3
22; RV64I-NEXT:    ret
23  %a = lshr i32 %x, 5
24  %b = and i32 %a, 134217720
25  ret i32 %b
26}
27
28define i64 @test2(i64 %x) {
29; RV32I-LABEL: test2:
30; RV32I:       # %bb.0:
31; RV32I-NEXT:    slli a2, a1, 27
32; RV32I-NEXT:    srli a0, a0, 5
33; RV32I-NEXT:    or a0, a0, a2
34; RV32I-NEXT:    srli a1, a1, 5
35; RV32I-NEXT:    andi a0, a0, -8
36; RV32I-NEXT:    ret
37;
38; RV64I-LABEL: test2:
39; RV64I:       # %bb.0:
40; RV64I-NEXT:    srli a0, a0, 5
41; RV64I-NEXT:    andi a0, a0, -8
42; RV64I-NEXT:    ret
43  %a = lshr i64 %x, 5
44  %b = and i64 %a, 576460752303423480
45  ret i64 %b
46}
47
48define i32 @test3(i32 %x) {
49; RV32I-LABEL: test3:
50; RV32I:       # %bb.0:
51; RV32I-NEXT:    srli a0, a0, 20
52; RV32I-NEXT:    slli a0, a0, 14
53; RV32I-NEXT:    ret
54;
55; RV64I-LABEL: test3:
56; RV64I:       # %bb.0:
57; RV64I-NEXT:    srliw a0, a0, 20
58; RV64I-NEXT:    slli a0, a0, 14
59; RV64I-NEXT:    ret
60  %a = lshr i32 %x, 6
61  %b = and i32 %a, 67092480
62  ret i32 %b
63}
64
65define i64 @test4(i64 %x) {
66; RV32I-LABEL: test4:
67; RV32I:       # %bb.0:
68; RV32I-NEXT:    slli a2, a1, 26
69; RV32I-NEXT:    srli a0, a0, 6
70; RV32I-NEXT:    srli a1, a1, 6
71; RV32I-NEXT:    or a0, a0, a2
72; RV32I-NEXT:    lui a2, 1048572
73; RV32I-NEXT:    and a0, a0, a2
74; RV32I-NEXT:    ret
75;
76; RV64I-LABEL: test4:
77; RV64I:       # %bb.0:
78; RV64I-NEXT:    srli a0, a0, 20
79; RV64I-NEXT:    slli a0, a0, 14
80; RV64I-NEXT:    ret
81  %a = lshr i64 %x, 6
82  %b = and i64 %a, 288230376151695360
83  ret i64 %b
84}
85
86define i32 @test5(i32 %x) {
87; RV32I-LABEL: test5:
88; RV32I:       # %bb.0:
89; RV32I-NEXT:    srli a0, a0, 10
90; RV32I-NEXT:    slli a0, a0, 16
91; RV32I-NEXT:    ret
92;
93; RV64I-LABEL: test5:
94; RV64I:       # %bb.0:
95; RV64I-NEXT:    andi a0, a0, -1024
96; RV64I-NEXT:    slliw a0, a0, 6
97; RV64I-NEXT:    ret
98  %a = shl i32 %x, 6
99  %b = and i32 %a, -65536
100  ret i32 %b
101}
102
103define i64 @test6(i64 %x) {
104; RV32I-LABEL: test6:
105; RV32I:       # %bb.0:
106; RV32I-NEXT:    srli a2, a0, 26
107; RV32I-NEXT:    slli a1, a1, 6
108; RV32I-NEXT:    srli a0, a0, 10
109; RV32I-NEXT:    or a1, a1, a2
110; RV32I-NEXT:    slli a0, a0, 16
111; RV32I-NEXT:    ret
112;
113; RV64I-LABEL: test6:
114; RV64I:       # %bb.0:
115; RV64I-NEXT:    srli a0, a0, 10
116; RV64I-NEXT:    slli a0, a0, 16
117; RV64I-NEXT:    ret
118  %a = shl i64 %x, 6
119  %b = and i64 %a, -65536
120  ret i64 %b
121}
122