1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ 3; RUN: | FileCheck %s -check-prefix=RV32I 4; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ 5; RUN: | FileCheck %s -check-prefix=RV64I 6 7define i1 @and_icmp_eq(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d) nounwind { 8; RV32I-LABEL: and_icmp_eq: 9; RV32I: # %bb.0: 10; RV32I-NEXT: xor a0, a0, a1 11; RV32I-NEXT: xor a2, a2, a3 12; RV32I-NEXT: or a0, a0, a2 13; RV32I-NEXT: seqz a0, a0 14; RV32I-NEXT: ret 15; 16; RV64I-LABEL: and_icmp_eq: 17; RV64I: # %bb.0: 18; RV64I-NEXT: xor a0, a0, a1 19; RV64I-NEXT: xor a2, a2, a3 20; RV64I-NEXT: or a0, a0, a2 21; RV64I-NEXT: seqz a0, a0 22; RV64I-NEXT: ret 23 %cmp1 = icmp eq i32 %a, %b 24 %cmp2 = icmp eq i32 %c, %d 25 %and = and i1 %cmp1, %cmp2 26 ret i1 %and 27} 28 29define i1 @or_icmp_ne(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d) nounwind { 30; RV32I-LABEL: or_icmp_ne: 31; RV32I: # %bb.0: 32; RV32I-NEXT: xor a0, a0, a1 33; RV32I-NEXT: xor a2, a2, a3 34; RV32I-NEXT: or a0, a0, a2 35; RV32I-NEXT: snez a0, a0 36; RV32I-NEXT: ret 37; 38; RV64I-LABEL: or_icmp_ne: 39; RV64I: # %bb.0: 40; RV64I-NEXT: xor a0, a0, a1 41; RV64I-NEXT: xor a2, a2, a3 42; RV64I-NEXT: or a0, a0, a2 43; RV64I-NEXT: snez a0, a0 44; RV64I-NEXT: ret 45 %cmp1 = icmp ne i32 %a, %b 46 %cmp2 = icmp ne i32 %c, %d 47 %or = or i1 %cmp1, %cmp2 48 ret i1 %or 49} 50 51define i1 @or_icmps_const_1bit_diff(i64 %x) nounwind { 52; RV32I-LABEL: or_icmps_const_1bit_diff: 53; RV32I: # %bb.0: 54; RV32I-NEXT: addi a2, a0, -13 55; RV32I-NEXT: sltu a0, a2, a0 56; RV32I-NEXT: add a0, a1, a0 57; RV32I-NEXT: addi a0, a0, -1 58; RV32I-NEXT: andi a2, a2, -5 59; RV32I-NEXT: or a0, a2, a0 60; RV32I-NEXT: seqz a0, a0 61; RV32I-NEXT: ret 62; 63; RV64I-LABEL: or_icmps_const_1bit_diff: 64; RV64I: # %bb.0: 65; RV64I-NEXT: addi a0, a0, -13 66; RV64I-NEXT: andi a0, a0, -5 67; RV64I-NEXT: seqz a0, a0 68; RV64I-NEXT: ret 69 %a = icmp eq i64 %x, 17 70 %b = icmp eq i64 %x, 13 71 %r = or i1 %a, %b 72 ret i1 %r 73} 74 75define i1 @and_icmps_const_1bit_diff(i32 %x) nounwind { 76; RV32I-LABEL: and_icmps_const_1bit_diff: 77; RV32I: # %bb.0: 78; RV32I-NEXT: addi a0, a0, -44 79; RV32I-NEXT: andi a0, a0, -17 80; RV32I-NEXT: snez a0, a0 81; RV32I-NEXT: ret 82; 83; RV64I-LABEL: and_icmps_const_1bit_diff: 84; RV64I: # %bb.0: 85; RV64I-NEXT: addiw a0, a0, -44 86; RV64I-NEXT: andi a0, a0, -17 87; RV64I-NEXT: snez a0, a0 88; RV64I-NEXT: ret 89 %a = icmp ne i32 %x, 44 90 %b = icmp ne i32 %x, 60 91 %r = and i1 %a, %b 92 ret i1 %r 93} 94 95define i1 @and_icmps_const_not1bit_diff(i32 %x) nounwind { 96; RV32I-LABEL: and_icmps_const_not1bit_diff: 97; RV32I: # %bb.0: 98; RV32I-NEXT: addi a1, a0, -44 99; RV32I-NEXT: addi a0, a0, -92 100; RV32I-NEXT: snez a1, a1 101; RV32I-NEXT: snez a0, a0 102; RV32I-NEXT: and a0, a1, a0 103; RV32I-NEXT: ret 104; 105; RV64I-LABEL: and_icmps_const_not1bit_diff: 106; RV64I: # %bb.0: 107; RV64I-NEXT: sext.w a0, a0 108; RV64I-NEXT: addi a1, a0, -44 109; RV64I-NEXT: addi a0, a0, -92 110; RV64I-NEXT: snez a1, a1 111; RV64I-NEXT: snez a0, a0 112; RV64I-NEXT: and a0, a1, a0 113; RV64I-NEXT: ret 114 %a = icmp ne i32 %x, 44 115 %b = icmp ne i32 %x, 92 116 %r = and i1 %a, %b 117 ret i1 %r 118} 119 120define i1 @and_icmp_sge(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d) nounwind { 121; RV32I-LABEL: and_icmp_sge: 122; RV32I: # %bb.0: 123; RV32I-NEXT: slt a0, a0, a1 124; RV32I-NEXT: slt a1, a2, a3 125; RV32I-NEXT: or a0, a0, a1 126; RV32I-NEXT: xori a0, a0, 1 127; RV32I-NEXT: ret 128; 129; RV64I-LABEL: and_icmp_sge: 130; RV64I: # %bb.0: 131; RV64I-NEXT: slt a0, a0, a1 132; RV64I-NEXT: slt a1, a2, a3 133; RV64I-NEXT: or a0, a0, a1 134; RV64I-NEXT: xori a0, a0, 1 135; RV64I-NEXT: ret 136 %cmp1 = icmp sge i32 %a, %b 137 %cmp2 = icmp sge i32 %c, %d 138 %and = and i1 %cmp1, %cmp2 139 ret i1 %and 140} 141 142define i1 @and_icmp_sle(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d) nounwind { 143; RV32I-LABEL: and_icmp_sle: 144; RV32I: # %bb.0: 145; RV32I-NEXT: slt a0, a1, a0 146; RV32I-NEXT: slt a1, a3, a2 147; RV32I-NEXT: or a0, a0, a1 148; RV32I-NEXT: xori a0, a0, 1 149; RV32I-NEXT: ret 150; 151; RV64I-LABEL: and_icmp_sle: 152; RV64I: # %bb.0: 153; RV64I-NEXT: slt a0, a1, a0 154; RV64I-NEXT: slt a1, a3, a2 155; RV64I-NEXT: or a0, a0, a1 156; RV64I-NEXT: xori a0, a0, 1 157; RV64I-NEXT: ret 158 %cmp1 = icmp sle i32 %a, %b 159 %cmp2 = icmp sle i32 %c, %d 160 %and = and i1 %cmp1, %cmp2 161 ret i1 %and 162} 163 164define i1 @and_icmp_uge(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d) nounwind { 165; RV32I-LABEL: and_icmp_uge: 166; RV32I: # %bb.0: 167; RV32I-NEXT: sltu a0, a0, a1 168; RV32I-NEXT: sltu a1, a2, a3 169; RV32I-NEXT: or a0, a0, a1 170; RV32I-NEXT: xori a0, a0, 1 171; RV32I-NEXT: ret 172; 173; RV64I-LABEL: and_icmp_uge: 174; RV64I: # %bb.0: 175; RV64I-NEXT: sltu a0, a0, a1 176; RV64I-NEXT: sltu a1, a2, a3 177; RV64I-NEXT: or a0, a0, a1 178; RV64I-NEXT: xori a0, a0, 1 179; RV64I-NEXT: ret 180 %cmp1 = icmp uge i32 %a, %b 181 %cmp2 = icmp uge i32 %c, %d 182 %and = and i1 %cmp1, %cmp2 183 ret i1 %and 184} 185 186define i1 @and_icmp_ule(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d) nounwind { 187; RV32I-LABEL: and_icmp_ule: 188; RV32I: # %bb.0: 189; RV32I-NEXT: sltu a0, a1, a0 190; RV32I-NEXT: sltu a1, a3, a2 191; RV32I-NEXT: or a0, a0, a1 192; RV32I-NEXT: xori a0, a0, 1 193; RV32I-NEXT: ret 194; 195; RV64I-LABEL: and_icmp_ule: 196; RV64I: # %bb.0: 197; RV64I-NEXT: sltu a0, a1, a0 198; RV64I-NEXT: sltu a1, a3, a2 199; RV64I-NEXT: or a0, a0, a1 200; RV64I-NEXT: xori a0, a0, 1 201; RV64I-NEXT: ret 202 %cmp1 = icmp ule i32 %a, %b 203 %cmp2 = icmp ule i32 %c, %d 204 %and = and i1 %cmp1, %cmp2 205 ret i1 %and 206} 207 208define i1 @or_icmp_sge(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d) nounwind { 209; RV32I-LABEL: or_icmp_sge: 210; RV32I: # %bb.0: 211; RV32I-NEXT: slt a0, a0, a1 212; RV32I-NEXT: slt a1, a2, a3 213; RV32I-NEXT: and a0, a0, a1 214; RV32I-NEXT: xori a0, a0, 1 215; RV32I-NEXT: ret 216; 217; RV64I-LABEL: or_icmp_sge: 218; RV64I: # %bb.0: 219; RV64I-NEXT: slt a0, a0, a1 220; RV64I-NEXT: slt a1, a2, a3 221; RV64I-NEXT: and a0, a0, a1 222; RV64I-NEXT: xori a0, a0, 1 223; RV64I-NEXT: ret 224 %cmp1 = icmp sge i32 %a, %b 225 %cmp2 = icmp sge i32 %c, %d 226 %and = or i1 %cmp1, %cmp2 227 ret i1 %and 228} 229 230define i1 @or_icmp_sle(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d) nounwind { 231; RV32I-LABEL: or_icmp_sle: 232; RV32I: # %bb.0: 233; RV32I-NEXT: slt a0, a1, a0 234; RV32I-NEXT: slt a1, a3, a2 235; RV32I-NEXT: and a0, a0, a1 236; RV32I-NEXT: xori a0, a0, 1 237; RV32I-NEXT: ret 238; 239; RV64I-LABEL: or_icmp_sle: 240; RV64I: # %bb.0: 241; RV64I-NEXT: slt a0, a1, a0 242; RV64I-NEXT: slt a1, a3, a2 243; RV64I-NEXT: and a0, a0, a1 244; RV64I-NEXT: xori a0, a0, 1 245; RV64I-NEXT: ret 246 %cmp1 = icmp sle i32 %a, %b 247 %cmp2 = icmp sle i32 %c, %d 248 %and = or i1 %cmp1, %cmp2 249 ret i1 %and 250} 251 252define i1 @or_icmp_uge(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d) nounwind { 253; RV32I-LABEL: or_icmp_uge: 254; RV32I: # %bb.0: 255; RV32I-NEXT: sltu a0, a0, a1 256; RV32I-NEXT: sltu a1, a2, a3 257; RV32I-NEXT: and a0, a0, a1 258; RV32I-NEXT: xori a0, a0, 1 259; RV32I-NEXT: ret 260; 261; RV64I-LABEL: or_icmp_uge: 262; RV64I: # %bb.0: 263; RV64I-NEXT: sltu a0, a0, a1 264; RV64I-NEXT: sltu a1, a2, a3 265; RV64I-NEXT: and a0, a0, a1 266; RV64I-NEXT: xori a0, a0, 1 267; RV64I-NEXT: ret 268 %cmp1 = icmp uge i32 %a, %b 269 %cmp2 = icmp uge i32 %c, %d 270 %and = or i1 %cmp1, %cmp2 271 ret i1 %and 272} 273 274define i1 @or_icmp_ule(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d) nounwind { 275; RV32I-LABEL: or_icmp_ule: 276; RV32I: # %bb.0: 277; RV32I-NEXT: sltu a0, a1, a0 278; RV32I-NEXT: sltu a1, a3, a2 279; RV32I-NEXT: and a0, a0, a1 280; RV32I-NEXT: xori a0, a0, 1 281; RV32I-NEXT: ret 282; 283; RV64I-LABEL: or_icmp_ule: 284; RV64I: # %bb.0: 285; RV64I-NEXT: sltu a0, a1, a0 286; RV64I-NEXT: sltu a1, a3, a2 287; RV64I-NEXT: and a0, a0, a1 288; RV64I-NEXT: xori a0, a0, 1 289; RV64I-NEXT: ret 290 %cmp1 = icmp ule i32 %a, %b 291 %cmp2 = icmp ule i32 %c, %d 292 %and = or i1 %cmp1, %cmp2 293 ret i1 %and 294} 295 296declare void @bar(...) 297 298define void @and_sge_eq(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) { 299; RV32I-LABEL: and_sge_eq: 300; RV32I: # %bb.0: 301; RV32I-NEXT: blt a0, a1, .LBB13_3 302; RV32I-NEXT: # %bb.1: 303; RV32I-NEXT: bne a2, a3, .LBB13_3 304; RV32I-NEXT: # %bb.2: 305; RV32I-NEXT: ret 306; RV32I-NEXT: .LBB13_3: 307; RV32I-NEXT: tail bar 308; 309; RV64I-LABEL: and_sge_eq: 310; RV64I: # %bb.0: 311; RV64I-NEXT: blt a0, a1, .LBB13_3 312; RV64I-NEXT: # %bb.1: 313; RV64I-NEXT: bne a2, a3, .LBB13_3 314; RV64I-NEXT: # %bb.2: 315; RV64I-NEXT: ret 316; RV64I-NEXT: .LBB13_3: 317; RV64I-NEXT: tail bar 318 %5 = icmp sge i32 %0, %1 319 %6 = icmp eq i32 %2, %3 320 %7 = and i1 %5, %6 321 br i1 %7, label %9, label %8 322 3238: ; preds = %4 324 tail call void @bar() 325 br label %9 326 3279: ; preds = %8, %4 328 ret void 329} 330 331define void @and_sle_eq(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) { 332; RV32I-LABEL: and_sle_eq: 333; RV32I: # %bb.0: 334; RV32I-NEXT: blt a1, a0, .LBB14_3 335; RV32I-NEXT: # %bb.1: 336; RV32I-NEXT: bne a2, a3, .LBB14_3 337; RV32I-NEXT: # %bb.2: 338; RV32I-NEXT: ret 339; RV32I-NEXT: .LBB14_3: 340; RV32I-NEXT: tail bar 341; 342; RV64I-LABEL: and_sle_eq: 343; RV64I: # %bb.0: 344; RV64I-NEXT: blt a1, a0, .LBB14_3 345; RV64I-NEXT: # %bb.1: 346; RV64I-NEXT: bne a2, a3, .LBB14_3 347; RV64I-NEXT: # %bb.2: 348; RV64I-NEXT: ret 349; RV64I-NEXT: .LBB14_3: 350; RV64I-NEXT: tail bar 351 %5 = icmp sle i32 %0, %1 352 %6 = icmp eq i32 %2, %3 353 %7 = and i1 %5, %6 354 br i1 %7, label %9, label %8 355 3568: ; preds = %4 357 tail call void @bar() 358 br label %9 359 3609: ; preds = %8, %4 361 ret void 362} 363 364define void @and_uge_eq(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) { 365; RV32I-LABEL: and_uge_eq: 366; RV32I: # %bb.0: 367; RV32I-NEXT: bltu a0, a1, .LBB15_3 368; RV32I-NEXT: # %bb.1: 369; RV32I-NEXT: bne a2, a3, .LBB15_3 370; RV32I-NEXT: # %bb.2: 371; RV32I-NEXT: ret 372; RV32I-NEXT: .LBB15_3: 373; RV32I-NEXT: tail bar 374; 375; RV64I-LABEL: and_uge_eq: 376; RV64I: # %bb.0: 377; RV64I-NEXT: bltu a0, a1, .LBB15_3 378; RV64I-NEXT: # %bb.1: 379; RV64I-NEXT: bne a2, a3, .LBB15_3 380; RV64I-NEXT: # %bb.2: 381; RV64I-NEXT: ret 382; RV64I-NEXT: .LBB15_3: 383; RV64I-NEXT: tail bar 384 %5 = icmp uge i32 %0, %1 385 %6 = icmp eq i32 %2, %3 386 %7 = and i1 %5, %6 387 br i1 %7, label %9, label %8 388 3898: ; preds = %4 390 tail call void @bar() 391 br label %9 392 3939: ; preds = %8, %4 394 ret void 395} 396 397define void @and_ule_eq(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) { 398; RV32I-LABEL: and_ule_eq: 399; RV32I: # %bb.0: 400; RV32I-NEXT: bltu a1, a0, .LBB16_3 401; RV32I-NEXT: # %bb.1: 402; RV32I-NEXT: bne a2, a3, .LBB16_3 403; RV32I-NEXT: # %bb.2: 404; RV32I-NEXT: ret 405; RV32I-NEXT: .LBB16_3: 406; RV32I-NEXT: tail bar 407; 408; RV64I-LABEL: and_ule_eq: 409; RV64I: # %bb.0: 410; RV64I-NEXT: bltu a1, a0, .LBB16_3 411; RV64I-NEXT: # %bb.1: 412; RV64I-NEXT: bne a2, a3, .LBB16_3 413; RV64I-NEXT: # %bb.2: 414; RV64I-NEXT: ret 415; RV64I-NEXT: .LBB16_3: 416; RV64I-NEXT: tail bar 417 %5 = icmp ule i32 %0, %1 418 %6 = icmp eq i32 %2, %3 419 %7 = and i1 %5, %6 420 br i1 %7, label %9, label %8 421 4228: ; preds = %4 423 tail call void @bar() 424 br label %9 425 4269: ; preds = %8, %4 427 ret void 428} 429 430define void @and_sge_ne(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) { 431; RV32I-LABEL: and_sge_ne: 432; RV32I: # %bb.0: 433; RV32I-NEXT: blt a0, a1, .LBB17_3 434; RV32I-NEXT: # %bb.1: 435; RV32I-NEXT: beq a2, a3, .LBB17_3 436; RV32I-NEXT: # %bb.2: 437; RV32I-NEXT: ret 438; RV32I-NEXT: .LBB17_3: 439; RV32I-NEXT: tail bar 440; 441; RV64I-LABEL: and_sge_ne: 442; RV64I: # %bb.0: 443; RV64I-NEXT: blt a0, a1, .LBB17_3 444; RV64I-NEXT: # %bb.1: 445; RV64I-NEXT: beq a2, a3, .LBB17_3 446; RV64I-NEXT: # %bb.2: 447; RV64I-NEXT: ret 448; RV64I-NEXT: .LBB17_3: 449; RV64I-NEXT: tail bar 450 %5 = icmp sge i32 %0, %1 451 %6 = icmp ne i32 %2, %3 452 %7 = and i1 %5, %6 453 br i1 %7, label %9, label %8 454 4558: ; preds = %4 456 tail call void @bar() 457 br label %9 458 4599: ; preds = %8, %4 460 ret void 461} 462 463define void @and_sle_ne(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) { 464; RV32I-LABEL: and_sle_ne: 465; RV32I: # %bb.0: 466; RV32I-NEXT: blt a1, a0, .LBB18_3 467; RV32I-NEXT: # %bb.1: 468; RV32I-NEXT: beq a2, a3, .LBB18_3 469; RV32I-NEXT: # %bb.2: 470; RV32I-NEXT: ret 471; RV32I-NEXT: .LBB18_3: 472; RV32I-NEXT: tail bar 473; 474; RV64I-LABEL: and_sle_ne: 475; RV64I: # %bb.0: 476; RV64I-NEXT: blt a1, a0, .LBB18_3 477; RV64I-NEXT: # %bb.1: 478; RV64I-NEXT: beq a2, a3, .LBB18_3 479; RV64I-NEXT: # %bb.2: 480; RV64I-NEXT: ret 481; RV64I-NEXT: .LBB18_3: 482; RV64I-NEXT: tail bar 483 %5 = icmp sle i32 %0, %1 484 %6 = icmp ne i32 %2, %3 485 %7 = and i1 %5, %6 486 br i1 %7, label %9, label %8 487 4888: ; preds = %4 489 tail call void @bar() 490 br label %9 491 4929: ; preds = %8, %4 493 ret void 494} 495 496define void @and_uge_ne(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) { 497; RV32I-LABEL: and_uge_ne: 498; RV32I: # %bb.0: 499; RV32I-NEXT: bltu a0, a1, .LBB19_3 500; RV32I-NEXT: # %bb.1: 501; RV32I-NEXT: beq a2, a3, .LBB19_3 502; RV32I-NEXT: # %bb.2: 503; RV32I-NEXT: ret 504; RV32I-NEXT: .LBB19_3: 505; RV32I-NEXT: tail bar 506; 507; RV64I-LABEL: and_uge_ne: 508; RV64I: # %bb.0: 509; RV64I-NEXT: bltu a0, a1, .LBB19_3 510; RV64I-NEXT: # %bb.1: 511; RV64I-NEXT: beq a2, a3, .LBB19_3 512; RV64I-NEXT: # %bb.2: 513; RV64I-NEXT: ret 514; RV64I-NEXT: .LBB19_3: 515; RV64I-NEXT: tail bar 516 %5 = icmp uge i32 %0, %1 517 %6 = icmp ne i32 %2, %3 518 %7 = and i1 %5, %6 519 br i1 %7, label %9, label %8 520 5218: ; preds = %4 522 tail call void @bar() 523 br label %9 524 5259: ; preds = %8, %4 526 ret void 527} 528 529define void @and_ule_ne(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) { 530; RV32I-LABEL: and_ule_ne: 531; RV32I: # %bb.0: 532; RV32I-NEXT: bltu a1, a0, .LBB20_3 533; RV32I-NEXT: # %bb.1: 534; RV32I-NEXT: beq a2, a3, .LBB20_3 535; RV32I-NEXT: # %bb.2: 536; RV32I-NEXT: ret 537; RV32I-NEXT: .LBB20_3: 538; RV32I-NEXT: tail bar 539; 540; RV64I-LABEL: and_ule_ne: 541; RV64I: # %bb.0: 542; RV64I-NEXT: bltu a1, a0, .LBB20_3 543; RV64I-NEXT: # %bb.1: 544; RV64I-NEXT: beq a2, a3, .LBB20_3 545; RV64I-NEXT: # %bb.2: 546; RV64I-NEXT: ret 547; RV64I-NEXT: .LBB20_3: 548; RV64I-NEXT: tail bar 549 %5 = icmp ule i32 %0, %1 550 %6 = icmp ne i32 %2, %3 551 %7 = and i1 %5, %6 552 br i1 %7, label %9, label %8 553 5548: ; preds = %4 555 tail call void @bar() 556 br label %9 557 5589: ; preds = %8, %4 559 ret void 560} 561 562define void @or_sge_eq(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) { 563; RV32I-LABEL: or_sge_eq: 564; RV32I: # %bb.0: 565; RV32I-NEXT: bge a0, a1, .LBB21_3 566; RV32I-NEXT: # %bb.1: 567; RV32I-NEXT: beq a2, a3, .LBB21_3 568; RV32I-NEXT: # %bb.2: 569; RV32I-NEXT: tail bar 570; RV32I-NEXT: .LBB21_3: 571; RV32I-NEXT: ret 572; 573; RV64I-LABEL: or_sge_eq: 574; RV64I: # %bb.0: 575; RV64I-NEXT: bge a0, a1, .LBB21_3 576; RV64I-NEXT: # %bb.1: 577; RV64I-NEXT: beq a2, a3, .LBB21_3 578; RV64I-NEXT: # %bb.2: 579; RV64I-NEXT: tail bar 580; RV64I-NEXT: .LBB21_3: 581; RV64I-NEXT: ret 582 %5 = icmp sge i32 %0, %1 583 %6 = icmp eq i32 %2, %3 584 %7 = or i1 %5, %6 585 br i1 %7, label %9, label %8 586 5878: ; preds = %4 588 tail call void @bar() 589 br label %9 590 5919: ; preds = %8, %4 592 ret void 593} 594 595define void @or_sle_eq(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) { 596; RV32I-LABEL: or_sle_eq: 597; RV32I: # %bb.0: 598; RV32I-NEXT: bge a1, a0, .LBB22_3 599; RV32I-NEXT: # %bb.1: 600; RV32I-NEXT: beq a2, a3, .LBB22_3 601; RV32I-NEXT: # %bb.2: 602; RV32I-NEXT: tail bar 603; RV32I-NEXT: .LBB22_3: 604; RV32I-NEXT: ret 605; 606; RV64I-LABEL: or_sle_eq: 607; RV64I: # %bb.0: 608; RV64I-NEXT: bge a1, a0, .LBB22_3 609; RV64I-NEXT: # %bb.1: 610; RV64I-NEXT: beq a2, a3, .LBB22_3 611; RV64I-NEXT: # %bb.2: 612; RV64I-NEXT: tail bar 613; RV64I-NEXT: .LBB22_3: 614; RV64I-NEXT: ret 615 %5 = icmp sle i32 %0, %1 616 %6 = icmp eq i32 %2, %3 617 %7 = or i1 %5, %6 618 br i1 %7, label %9, label %8 619 6208: ; preds = %4 621 tail call void @bar() 622 br label %9 623 6249: ; preds = %8, %4 625 ret void 626} 627 628define void @or_uge_eq(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) { 629; RV32I-LABEL: or_uge_eq: 630; RV32I: # %bb.0: 631; RV32I-NEXT: bgeu a0, a1, .LBB23_3 632; RV32I-NEXT: # %bb.1: 633; RV32I-NEXT: beq a2, a3, .LBB23_3 634; RV32I-NEXT: # %bb.2: 635; RV32I-NEXT: tail bar 636; RV32I-NEXT: .LBB23_3: 637; RV32I-NEXT: ret 638; 639; RV64I-LABEL: or_uge_eq: 640; RV64I: # %bb.0: 641; RV64I-NEXT: bgeu a0, a1, .LBB23_3 642; RV64I-NEXT: # %bb.1: 643; RV64I-NEXT: beq a2, a3, .LBB23_3 644; RV64I-NEXT: # %bb.2: 645; RV64I-NEXT: tail bar 646; RV64I-NEXT: .LBB23_3: 647; RV64I-NEXT: ret 648 %5 = icmp uge i32 %0, %1 649 %6 = icmp eq i32 %2, %3 650 %7 = or i1 %5, %6 651 br i1 %7, label %9, label %8 652 6538: ; preds = %4 654 tail call void @bar() 655 br label %9 656 6579: ; preds = %8, %4 658 ret void 659} 660 661define void @or_ule_eq(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) { 662; RV32I-LABEL: or_ule_eq: 663; RV32I: # %bb.0: 664; RV32I-NEXT: bgeu a1, a0, .LBB24_3 665; RV32I-NEXT: # %bb.1: 666; RV32I-NEXT: beq a2, a3, .LBB24_3 667; RV32I-NEXT: # %bb.2: 668; RV32I-NEXT: tail bar 669; RV32I-NEXT: .LBB24_3: 670; RV32I-NEXT: ret 671; 672; RV64I-LABEL: or_ule_eq: 673; RV64I: # %bb.0: 674; RV64I-NEXT: bgeu a1, a0, .LBB24_3 675; RV64I-NEXT: # %bb.1: 676; RV64I-NEXT: beq a2, a3, .LBB24_3 677; RV64I-NEXT: # %bb.2: 678; RV64I-NEXT: tail bar 679; RV64I-NEXT: .LBB24_3: 680; RV64I-NEXT: ret 681 %5 = icmp ule i32 %0, %1 682 %6 = icmp eq i32 %2, %3 683 %7 = or i1 %5, %6 684 br i1 %7, label %9, label %8 685 6868: ; preds = %4 687 tail call void @bar() 688 br label %9 689 6909: ; preds = %8, %4 691 ret void 692} 693 694define void @or_sge_ne(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) { 695; RV32I-LABEL: or_sge_ne: 696; RV32I: # %bb.0: 697; RV32I-NEXT: bge a0, a1, .LBB25_3 698; RV32I-NEXT: # %bb.1: 699; RV32I-NEXT: bne a2, a3, .LBB25_3 700; RV32I-NEXT: # %bb.2: 701; RV32I-NEXT: tail bar 702; RV32I-NEXT: .LBB25_3: 703; RV32I-NEXT: ret 704; 705; RV64I-LABEL: or_sge_ne: 706; RV64I: # %bb.0: 707; RV64I-NEXT: bge a0, a1, .LBB25_3 708; RV64I-NEXT: # %bb.1: 709; RV64I-NEXT: bne a2, a3, .LBB25_3 710; RV64I-NEXT: # %bb.2: 711; RV64I-NEXT: tail bar 712; RV64I-NEXT: .LBB25_3: 713; RV64I-NEXT: ret 714 %5 = icmp sge i32 %0, %1 715 %6 = icmp ne i32 %2, %3 716 %7 = or i1 %5, %6 717 br i1 %7, label %9, label %8 718 7198: ; preds = %4 720 tail call void @bar() 721 br label %9 722 7239: ; preds = %8, %4 724 ret void 725} 726 727define void @or_sle_ne(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) { 728; RV32I-LABEL: or_sle_ne: 729; RV32I: # %bb.0: 730; RV32I-NEXT: bge a1, a0, .LBB26_3 731; RV32I-NEXT: # %bb.1: 732; RV32I-NEXT: bne a2, a3, .LBB26_3 733; RV32I-NEXT: # %bb.2: 734; RV32I-NEXT: tail bar 735; RV32I-NEXT: .LBB26_3: 736; RV32I-NEXT: ret 737; 738; RV64I-LABEL: or_sle_ne: 739; RV64I: # %bb.0: 740; RV64I-NEXT: bge a1, a0, .LBB26_3 741; RV64I-NEXT: # %bb.1: 742; RV64I-NEXT: bne a2, a3, .LBB26_3 743; RV64I-NEXT: # %bb.2: 744; RV64I-NEXT: tail bar 745; RV64I-NEXT: .LBB26_3: 746; RV64I-NEXT: ret 747 %5 = icmp sle i32 %0, %1 748 %6 = icmp ne i32 %2, %3 749 %7 = or i1 %5, %6 750 br i1 %7, label %9, label %8 751 7528: ; preds = %4 753 tail call void @bar() 754 br label %9 755 7569: ; preds = %8, %4 757 ret void 758} 759 760define void @or_uge_ne(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) { 761; RV32I-LABEL: or_uge_ne: 762; RV32I: # %bb.0: 763; RV32I-NEXT: bgeu a0, a1, .LBB27_3 764; RV32I-NEXT: # %bb.1: 765; RV32I-NEXT: bne a2, a3, .LBB27_3 766; RV32I-NEXT: # %bb.2: 767; RV32I-NEXT: tail bar 768; RV32I-NEXT: .LBB27_3: 769; RV32I-NEXT: ret 770; 771; RV64I-LABEL: or_uge_ne: 772; RV64I: # %bb.0: 773; RV64I-NEXT: bgeu a0, a1, .LBB27_3 774; RV64I-NEXT: # %bb.1: 775; RV64I-NEXT: bne a2, a3, .LBB27_3 776; RV64I-NEXT: # %bb.2: 777; RV64I-NEXT: tail bar 778; RV64I-NEXT: .LBB27_3: 779; RV64I-NEXT: ret 780 %5 = icmp uge i32 %0, %1 781 %6 = icmp ne i32 %2, %3 782 %7 = or i1 %5, %6 783 br i1 %7, label %9, label %8 784 7858: ; preds = %4 786 tail call void @bar() 787 br label %9 788 7899: ; preds = %8, %4 790 ret void 791} 792 793define void @or_ule_ne(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) { 794; RV32I-LABEL: or_ule_ne: 795; RV32I: # %bb.0: 796; RV32I-NEXT: bgeu a1, a0, .LBB28_3 797; RV32I-NEXT: # %bb.1: 798; RV32I-NEXT: bne a2, a3, .LBB28_3 799; RV32I-NEXT: # %bb.2: 800; RV32I-NEXT: tail bar 801; RV32I-NEXT: .LBB28_3: 802; RV32I-NEXT: ret 803; 804; RV64I-LABEL: or_ule_ne: 805; RV64I: # %bb.0: 806; RV64I-NEXT: bgeu a1, a0, .LBB28_3 807; RV64I-NEXT: # %bb.1: 808; RV64I-NEXT: bne a2, a3, .LBB28_3 809; RV64I-NEXT: # %bb.2: 810; RV64I-NEXT: tail bar 811; RV64I-NEXT: .LBB28_3: 812; RV64I-NEXT: ret 813 %5 = icmp ule i32 %0, %1 814 %6 = icmp ne i32 %2, %3 815 %7 = or i1 %5, %6 816 br i1 %7, label %9, label %8 817 8188: ; preds = %4 819 tail call void @bar() 820 br label %9 821 8229: ; preds = %8, %4 823 ret void 824} 825 826define void @and_eq_sge(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) { 827; RV32I-LABEL: and_eq_sge: 828; RV32I: # %bb.0: 829; RV32I-NEXT: bne a0, a1, .LBB29_3 830; RV32I-NEXT: # %bb.1: 831; RV32I-NEXT: blt a2, a3, .LBB29_3 832; RV32I-NEXT: # %bb.2: 833; RV32I-NEXT: ret 834; RV32I-NEXT: .LBB29_3: 835; RV32I-NEXT: tail bar 836; 837; RV64I-LABEL: and_eq_sge: 838; RV64I: # %bb.0: 839; RV64I-NEXT: bne a0, a1, .LBB29_3 840; RV64I-NEXT: # %bb.1: 841; RV64I-NEXT: blt a2, a3, .LBB29_3 842; RV64I-NEXT: # %bb.2: 843; RV64I-NEXT: ret 844; RV64I-NEXT: .LBB29_3: 845; RV64I-NEXT: tail bar 846 %5 = icmp eq i32 %0, %1 847 %6 = icmp sge i32 %2, %3 848 %7 = and i1 %5, %6 849 br i1 %7, label %9, label %8 850 8518: ; preds = %4 852 tail call void @bar() 853 br label %9 854 8559: ; preds = %8, %4 856 ret void 857} 858 859define void @and_eq_sle(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) { 860; RV32I-LABEL: and_eq_sle: 861; RV32I: # %bb.0: 862; RV32I-NEXT: bne a0, a1, .LBB30_3 863; RV32I-NEXT: # %bb.1: 864; RV32I-NEXT: blt a3, a2, .LBB30_3 865; RV32I-NEXT: # %bb.2: 866; RV32I-NEXT: ret 867; RV32I-NEXT: .LBB30_3: 868; RV32I-NEXT: tail bar 869; 870; RV64I-LABEL: and_eq_sle: 871; RV64I: # %bb.0: 872; RV64I-NEXT: bne a0, a1, .LBB30_3 873; RV64I-NEXT: # %bb.1: 874; RV64I-NEXT: blt a3, a2, .LBB30_3 875; RV64I-NEXT: # %bb.2: 876; RV64I-NEXT: ret 877; RV64I-NEXT: .LBB30_3: 878; RV64I-NEXT: tail bar 879 %5 = icmp eq i32 %0, %1 880 %6 = icmp sle i32 %2, %3 881 %7 = and i1 %5, %6 882 br i1 %7, label %9, label %8 883 8848: ; preds = %4 885 tail call void @bar() 886 br label %9 887 8889: ; preds = %8, %4 889 ret void 890} 891 892define void @and_eq_uge(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) { 893; RV32I-LABEL: and_eq_uge: 894; RV32I: # %bb.0: 895; RV32I-NEXT: bne a0, a1, .LBB31_3 896; RV32I-NEXT: # %bb.1: 897; RV32I-NEXT: bltu a2, a3, .LBB31_3 898; RV32I-NEXT: # %bb.2: 899; RV32I-NEXT: ret 900; RV32I-NEXT: .LBB31_3: 901; RV32I-NEXT: tail bar 902; 903; RV64I-LABEL: and_eq_uge: 904; RV64I: # %bb.0: 905; RV64I-NEXT: bne a0, a1, .LBB31_3 906; RV64I-NEXT: # %bb.1: 907; RV64I-NEXT: bltu a2, a3, .LBB31_3 908; RV64I-NEXT: # %bb.2: 909; RV64I-NEXT: ret 910; RV64I-NEXT: .LBB31_3: 911; RV64I-NEXT: tail bar 912 %5 = icmp eq i32 %0, %1 913 %6 = icmp uge i32 %2, %3 914 %7 = and i1 %5, %6 915 br i1 %7, label %9, label %8 916 9178: ; preds = %4 918 tail call void @bar() 919 br label %9 920 9219: ; preds = %8, %4 922 ret void 923} 924 925define void @and_eq_ule(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) { 926; RV32I-LABEL: and_eq_ule: 927; RV32I: # %bb.0: 928; RV32I-NEXT: bne a0, a1, .LBB32_3 929; RV32I-NEXT: # %bb.1: 930; RV32I-NEXT: bltu a3, a2, .LBB32_3 931; RV32I-NEXT: # %bb.2: 932; RV32I-NEXT: ret 933; RV32I-NEXT: .LBB32_3: 934; RV32I-NEXT: tail bar 935; 936; RV64I-LABEL: and_eq_ule: 937; RV64I: # %bb.0: 938; RV64I-NEXT: bne a0, a1, .LBB32_3 939; RV64I-NEXT: # %bb.1: 940; RV64I-NEXT: bltu a3, a2, .LBB32_3 941; RV64I-NEXT: # %bb.2: 942; RV64I-NEXT: ret 943; RV64I-NEXT: .LBB32_3: 944; RV64I-NEXT: tail bar 945 %5 = icmp eq i32 %0, %1 946 %6 = icmp ule i32 %2, %3 947 %7 = and i1 %5, %6 948 br i1 %7, label %9, label %8 949 9508: ; preds = %4 951 tail call void @bar() 952 br label %9 953 9549: ; preds = %8, %4 955 ret void 956} 957 958define void @and_ne_sge(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) { 959; RV32I-LABEL: and_ne_sge: 960; RV32I: # %bb.0: 961; RV32I-NEXT: beq a0, a1, .LBB33_3 962; RV32I-NEXT: # %bb.1: 963; RV32I-NEXT: blt a2, a3, .LBB33_3 964; RV32I-NEXT: # %bb.2: 965; RV32I-NEXT: ret 966; RV32I-NEXT: .LBB33_3: 967; RV32I-NEXT: tail bar 968; 969; RV64I-LABEL: and_ne_sge: 970; RV64I: # %bb.0: 971; RV64I-NEXT: beq a0, a1, .LBB33_3 972; RV64I-NEXT: # %bb.1: 973; RV64I-NEXT: blt a2, a3, .LBB33_3 974; RV64I-NEXT: # %bb.2: 975; RV64I-NEXT: ret 976; RV64I-NEXT: .LBB33_3: 977; RV64I-NEXT: tail bar 978 %5 = icmp ne i32 %0, %1 979 %6 = icmp sge i32 %2, %3 980 %7 = and i1 %5, %6 981 br i1 %7, label %9, label %8 982 9838: ; preds = %4 984 tail call void @bar() 985 br label %9 986 9879: ; preds = %8, %4 988 ret void 989} 990 991define void @and_ne_sle(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) { 992; RV32I-LABEL: and_ne_sle: 993; RV32I: # %bb.0: 994; RV32I-NEXT: beq a0, a1, .LBB34_3 995; RV32I-NEXT: # %bb.1: 996; RV32I-NEXT: blt a3, a2, .LBB34_3 997; RV32I-NEXT: # %bb.2: 998; RV32I-NEXT: ret 999; RV32I-NEXT: .LBB34_3: 1000; RV32I-NEXT: tail bar 1001; 1002; RV64I-LABEL: and_ne_sle: 1003; RV64I: # %bb.0: 1004; RV64I-NEXT: beq a0, a1, .LBB34_3 1005; RV64I-NEXT: # %bb.1: 1006; RV64I-NEXT: blt a3, a2, .LBB34_3 1007; RV64I-NEXT: # %bb.2: 1008; RV64I-NEXT: ret 1009; RV64I-NEXT: .LBB34_3: 1010; RV64I-NEXT: tail bar 1011 %5 = icmp ne i32 %0, %1 1012 %6 = icmp sle i32 %2, %3 1013 %7 = and i1 %5, %6 1014 br i1 %7, label %9, label %8 1015 10168: ; preds = %4 1017 tail call void @bar() 1018 br label %9 1019 10209: ; preds = %8, %4 1021 ret void 1022} 1023 1024define void @and_ne_uge(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) { 1025; RV32I-LABEL: and_ne_uge: 1026; RV32I: # %bb.0: 1027; RV32I-NEXT: beq a0, a1, .LBB35_3 1028; RV32I-NEXT: # %bb.1: 1029; RV32I-NEXT: bltu a2, a3, .LBB35_3 1030; RV32I-NEXT: # %bb.2: 1031; RV32I-NEXT: ret 1032; RV32I-NEXT: .LBB35_3: 1033; RV32I-NEXT: tail bar 1034; 1035; RV64I-LABEL: and_ne_uge: 1036; RV64I: # %bb.0: 1037; RV64I-NEXT: beq a0, a1, .LBB35_3 1038; RV64I-NEXT: # %bb.1: 1039; RV64I-NEXT: bltu a2, a3, .LBB35_3 1040; RV64I-NEXT: # %bb.2: 1041; RV64I-NEXT: ret 1042; RV64I-NEXT: .LBB35_3: 1043; RV64I-NEXT: tail bar 1044 %5 = icmp ne i32 %0, %1 1045 %6 = icmp uge i32 %2, %3 1046 %7 = and i1 %5, %6 1047 br i1 %7, label %9, label %8 1048 10498: ; preds = %4 1050 tail call void @bar() 1051 br label %9 1052 10539: ; preds = %8, %4 1054 ret void 1055} 1056 1057define void @and_ne_ule(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) { 1058; RV32I-LABEL: and_ne_ule: 1059; RV32I: # %bb.0: 1060; RV32I-NEXT: beq a0, a1, .LBB36_3 1061; RV32I-NEXT: # %bb.1: 1062; RV32I-NEXT: bltu a3, a2, .LBB36_3 1063; RV32I-NEXT: # %bb.2: 1064; RV32I-NEXT: ret 1065; RV32I-NEXT: .LBB36_3: 1066; RV32I-NEXT: tail bar 1067; 1068; RV64I-LABEL: and_ne_ule: 1069; RV64I: # %bb.0: 1070; RV64I-NEXT: beq a0, a1, .LBB36_3 1071; RV64I-NEXT: # %bb.1: 1072; RV64I-NEXT: bltu a3, a2, .LBB36_3 1073; RV64I-NEXT: # %bb.2: 1074; RV64I-NEXT: ret 1075; RV64I-NEXT: .LBB36_3: 1076; RV64I-NEXT: tail bar 1077 %5 = icmp ne i32 %0, %1 1078 %6 = icmp ule i32 %2, %3 1079 %7 = and i1 %5, %6 1080 br i1 %7, label %9, label %8 1081 10828: ; preds = %4 1083 tail call void @bar() 1084 br label %9 1085 10869: ; preds = %8, %4 1087 ret void 1088} 1089 1090define void @and_sge_gt0(i32 signext %0, i32 signext %1, i32 signext %2) { 1091; RV32I-LABEL: and_sge_gt0: 1092; RV32I: # %bb.0: 1093; RV32I-NEXT: blt a0, a1, .LBB37_3 1094; RV32I-NEXT: # %bb.1: 1095; RV32I-NEXT: blez a2, .LBB37_3 1096; RV32I-NEXT: # %bb.2: 1097; RV32I-NEXT: ret 1098; RV32I-NEXT: .LBB37_3: 1099; RV32I-NEXT: tail bar 1100; 1101; RV64I-LABEL: and_sge_gt0: 1102; RV64I: # %bb.0: 1103; RV64I-NEXT: blt a0, a1, .LBB37_3 1104; RV64I-NEXT: # %bb.1: 1105; RV64I-NEXT: blez a2, .LBB37_3 1106; RV64I-NEXT: # %bb.2: 1107; RV64I-NEXT: ret 1108; RV64I-NEXT: .LBB37_3: 1109; RV64I-NEXT: tail bar 1110 %4 = icmp sge i32 %0, %1 1111 %5 = icmp sgt i32 %2, 0 1112 %6 = and i1 %4, %5 1113 br i1 %6, label %8, label %7 1114 11157: ; preds = %4 1116 tail call void @bar() 1117 br label %8 1118 11198: ; preds = %8, %4 1120 ret void 1121} 1122 1123define void @and_sle_lt1(i32 signext %0, i32 signext %1, i32 signext %2) { 1124; RV32I-LABEL: and_sle_lt1: 1125; RV32I: # %bb.0: 1126; RV32I-NEXT: blt a1, a0, .LBB38_3 1127; RV32I-NEXT: # %bb.1: 1128; RV32I-NEXT: bgtz a2, .LBB38_3 1129; RV32I-NEXT: # %bb.2: 1130; RV32I-NEXT: ret 1131; RV32I-NEXT: .LBB38_3: 1132; RV32I-NEXT: tail bar 1133; 1134; RV64I-LABEL: and_sle_lt1: 1135; RV64I: # %bb.0: 1136; RV64I-NEXT: blt a1, a0, .LBB38_3 1137; RV64I-NEXT: # %bb.1: 1138; RV64I-NEXT: bgtz a2, .LBB38_3 1139; RV64I-NEXT: # %bb.2: 1140; RV64I-NEXT: ret 1141; RV64I-NEXT: .LBB38_3: 1142; RV64I-NEXT: tail bar 1143 %4 = icmp sle i32 %0, %1 1144 %5 = icmp slt i32 %2, 1 1145 %6 = and i1 %4, %5 1146 br i1 %6, label %8, label %7 1147 11487: ; preds = %4 1149 tail call void @bar() 1150 br label %8 1151 11528: ; preds = %8, %4 1153 ret void 1154} 1155 1156define void @or_uge_gt0(i32 signext %0, i32 signext %1, i32 signext %2) { 1157; RV32I-LABEL: or_uge_gt0: 1158; RV32I: # %bb.0: 1159; RV32I-NEXT: bgeu a0, a1, .LBB39_3 1160; RV32I-NEXT: # %bb.1: 1161; RV32I-NEXT: bgtz a2, .LBB39_3 1162; RV32I-NEXT: # %bb.2: 1163; RV32I-NEXT: tail bar 1164; RV32I-NEXT: .LBB39_3: 1165; RV32I-NEXT: ret 1166; 1167; RV64I-LABEL: or_uge_gt0: 1168; RV64I: # %bb.0: 1169; RV64I-NEXT: bgeu a0, a1, .LBB39_3 1170; RV64I-NEXT: # %bb.1: 1171; RV64I-NEXT: bgtz a2, .LBB39_3 1172; RV64I-NEXT: # %bb.2: 1173; RV64I-NEXT: tail bar 1174; RV64I-NEXT: .LBB39_3: 1175; RV64I-NEXT: ret 1176 %4 = icmp uge i32 %0, %1 1177 %5 = icmp sgt i32 %2, 0 1178 %6 = or i1 %4, %5 1179 br i1 %6, label %8, label %7 1180 11817: ; preds = %4 1182 tail call void @bar() 1183 br label %8 1184 11858: ; preds = %8, %4 1186 ret void 1187} 1188 1189define void @or_ule_lt1(i32 signext %0, i32 signext %1, i32 signext %2) { 1190; RV32I-LABEL: or_ule_lt1: 1191; RV32I: # %bb.0: 1192; RV32I-NEXT: bgeu a1, a0, .LBB40_3 1193; RV32I-NEXT: # %bb.1: 1194; RV32I-NEXT: blez a2, .LBB40_3 1195; RV32I-NEXT: # %bb.2: 1196; RV32I-NEXT: tail bar 1197; RV32I-NEXT: .LBB40_3: 1198; RV32I-NEXT: ret 1199; 1200; RV64I-LABEL: or_ule_lt1: 1201; RV64I: # %bb.0: 1202; RV64I-NEXT: bgeu a1, a0, .LBB40_3 1203; RV64I-NEXT: # %bb.1: 1204; RV64I-NEXT: blez a2, .LBB40_3 1205; RV64I-NEXT: # %bb.2: 1206; RV64I-NEXT: tail bar 1207; RV64I-NEXT: .LBB40_3: 1208; RV64I-NEXT: ret 1209 %4 = icmp ule i32 %0, %1 1210 %5 = icmp slt i32 %2, 1 1211 %6 = or i1 %4, %5 1212 br i1 %6, label %8, label %7 1213 12147: ; preds = %4 1215 tail call void @bar() 1216 br label %8 1217 12188: ; preds = %8, %4 1219 ret void 1220} 1221