1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=riscv32 -mattr=+m -verify-machineinstrs < %s | FileCheck --check-prefixes=CHECK,RV32IM %s 3; RUN: llc -mtriple=riscv64 -mattr=+m -verify-machineinstrs < %s | FileCheck --check-prefixes=CHECK,RV64IM %s 4; RUN: llc -mtriple=riscv64 -mattr=+m,+xventanacondops -verify-machineinstrs < %s | FileCheck --check-prefixes=CHECK,RV64IMXVTCONDOPS %s 5; RUN: llc -mtriple=riscv32 -mattr=+m,+zicond -verify-machineinstrs < %s | FileCheck --check-prefixes=CHECK,CHECKZICOND,RV32IMZICOND %s 6; RUN: llc -mtriple=riscv64 -mattr=+m,+zicond -verify-machineinstrs < %s | FileCheck --check-prefixes=CHECK,CHECKZICOND,RV64IMZICOND %s 7 8define i16 @select_xor_1(i16 %A, i8 %cond) { 9; RV32IM-LABEL: select_xor_1: 10; RV32IM: # %bb.0: # %entry 11; RV32IM-NEXT: slli a1, a1, 31 12; RV32IM-NEXT: srai a1, a1, 31 13; RV32IM-NEXT: andi a1, a1, 43 14; RV32IM-NEXT: xor a0, a0, a1 15; RV32IM-NEXT: ret 16; 17; RV64IM-LABEL: select_xor_1: 18; RV64IM: # %bb.0: # %entry 19; RV64IM-NEXT: slli a1, a1, 63 20; RV64IM-NEXT: srai a1, a1, 63 21; RV64IM-NEXT: andi a1, a1, 43 22; RV64IM-NEXT: xor a0, a0, a1 23; RV64IM-NEXT: ret 24; 25; RV64IMXVTCONDOPS-LABEL: select_xor_1: 26; RV64IMXVTCONDOPS: # %bb.0: # %entry 27; RV64IMXVTCONDOPS-NEXT: andi a1, a1, 1 28; RV64IMXVTCONDOPS-NEXT: li a2, 43 29; RV64IMXVTCONDOPS-NEXT: vt.maskc a1, a2, a1 30; RV64IMXVTCONDOPS-NEXT: xor a0, a0, a1 31; RV64IMXVTCONDOPS-NEXT: ret 32; 33; CHECKZICOND-LABEL: select_xor_1: 34; CHECKZICOND: # %bb.0: # %entry 35; CHECKZICOND-NEXT: andi a1, a1, 1 36; CHECKZICOND-NEXT: li a2, 43 37; CHECKZICOND-NEXT: czero.eqz a1, a2, a1 38; CHECKZICOND-NEXT: xor a0, a0, a1 39; CHECKZICOND-NEXT: ret 40entry: 41 %and = and i8 %cond, 1 42 %cmp10 = icmp eq i8 %and, 0 43 %0 = xor i16 %A, 43 44 %1 = select i1 %cmp10, i16 %A, i16 %0 45 ret i16 %1 46} 47 48; Equivalent to above, but with icmp ne (and %cond, 1), 1 instead of 49; icmp eq (and %cond, 1), 0 50define i16 @select_xor_1b(i16 %A, i8 %cond) { 51; RV32IM-LABEL: select_xor_1b: 52; RV32IM: # %bb.0: # %entry 53; RV32IM-NEXT: slli a1, a1, 31 54; RV32IM-NEXT: srai a1, a1, 31 55; RV32IM-NEXT: andi a1, a1, 43 56; RV32IM-NEXT: xor a0, a0, a1 57; RV32IM-NEXT: ret 58; 59; RV64IM-LABEL: select_xor_1b: 60; RV64IM: # %bb.0: # %entry 61; RV64IM-NEXT: slli a1, a1, 63 62; RV64IM-NEXT: srai a1, a1, 63 63; RV64IM-NEXT: andi a1, a1, 43 64; RV64IM-NEXT: xor a0, a0, a1 65; RV64IM-NEXT: ret 66; 67; RV64IMXVTCONDOPS-LABEL: select_xor_1b: 68; RV64IMXVTCONDOPS: # %bb.0: # %entry 69; RV64IMXVTCONDOPS-NEXT: andi a1, a1, 1 70; RV64IMXVTCONDOPS-NEXT: li a2, 43 71; RV64IMXVTCONDOPS-NEXT: vt.maskc a1, a2, a1 72; RV64IMXVTCONDOPS-NEXT: xor a0, a0, a1 73; RV64IMXVTCONDOPS-NEXT: ret 74; 75; CHECKZICOND-LABEL: select_xor_1b: 76; CHECKZICOND: # %bb.0: # %entry 77; CHECKZICOND-NEXT: andi a1, a1, 1 78; CHECKZICOND-NEXT: li a2, 43 79; CHECKZICOND-NEXT: czero.eqz a1, a2, a1 80; CHECKZICOND-NEXT: xor a0, a0, a1 81; CHECKZICOND-NEXT: ret 82entry: 83 %and = and i8 %cond, 1 84 %cmp10 = icmp ne i8 %and, 1 85 %0 = xor i16 %A, 43 86 %1 = select i1 %cmp10, i16 %A, i16 %0 87 ret i16 %1 88} 89 90define i32 @select_xor_2(i32 %A, i32 %B, i8 %cond) { 91; RV32IM-LABEL: select_xor_2: 92; RV32IM: # %bb.0: # %entry 93; RV32IM-NEXT: slli a2, a2, 31 94; RV32IM-NEXT: srai a2, a2, 31 95; RV32IM-NEXT: and a1, a2, a1 96; RV32IM-NEXT: xor a0, a0, a1 97; RV32IM-NEXT: ret 98; 99; RV64IM-LABEL: select_xor_2: 100; RV64IM: # %bb.0: # %entry 101; RV64IM-NEXT: slli a2, a2, 63 102; RV64IM-NEXT: srai a2, a2, 63 103; RV64IM-NEXT: and a1, a2, a1 104; RV64IM-NEXT: xor a0, a0, a1 105; RV64IM-NEXT: ret 106; 107; RV64IMXVTCONDOPS-LABEL: select_xor_2: 108; RV64IMXVTCONDOPS: # %bb.0: # %entry 109; RV64IMXVTCONDOPS-NEXT: andi a2, a2, 1 110; RV64IMXVTCONDOPS-NEXT: vt.maskc a1, a1, a2 111; RV64IMXVTCONDOPS-NEXT: xor a0, a0, a1 112; RV64IMXVTCONDOPS-NEXT: ret 113; 114; CHECKZICOND-LABEL: select_xor_2: 115; CHECKZICOND: # %bb.0: # %entry 116; CHECKZICOND-NEXT: andi a2, a2, 1 117; CHECKZICOND-NEXT: czero.eqz a1, a1, a2 118; CHECKZICOND-NEXT: xor a0, a0, a1 119; CHECKZICOND-NEXT: ret 120entry: 121 %and = and i8 %cond, 1 122 %cmp10 = icmp eq i8 %and, 0 123 %0 = xor i32 %B, %A 124 %1 = select i1 %cmp10, i32 %A, i32 %0 125 ret i32 %1 126} 127 128; Equivalent to above, but with icmp ne (and %cond, 1), 1 instead of 129; icmp eq (and %cond, 1), 0 130define i32 @select_xor_2b(i32 %A, i32 %B, i8 %cond) { 131; RV32IM-LABEL: select_xor_2b: 132; RV32IM: # %bb.0: # %entry 133; RV32IM-NEXT: slli a2, a2, 31 134; RV32IM-NEXT: srai a2, a2, 31 135; RV32IM-NEXT: and a1, a2, a1 136; RV32IM-NEXT: xor a0, a0, a1 137; RV32IM-NEXT: ret 138; 139; RV64IM-LABEL: select_xor_2b: 140; RV64IM: # %bb.0: # %entry 141; RV64IM-NEXT: slli a2, a2, 63 142; RV64IM-NEXT: srai a2, a2, 63 143; RV64IM-NEXT: and a1, a2, a1 144; RV64IM-NEXT: xor a0, a0, a1 145; RV64IM-NEXT: ret 146; 147; RV64IMXVTCONDOPS-LABEL: select_xor_2b: 148; RV64IMXVTCONDOPS: # %bb.0: # %entry 149; RV64IMXVTCONDOPS-NEXT: andi a2, a2, 1 150; RV64IMXVTCONDOPS-NEXT: vt.maskc a1, a1, a2 151; RV64IMXVTCONDOPS-NEXT: xor a0, a0, a1 152; RV64IMXVTCONDOPS-NEXT: ret 153; 154; CHECKZICOND-LABEL: select_xor_2b: 155; CHECKZICOND: # %bb.0: # %entry 156; CHECKZICOND-NEXT: andi a2, a2, 1 157; CHECKZICOND-NEXT: czero.eqz a1, a1, a2 158; CHECKZICOND-NEXT: xor a0, a0, a1 159; CHECKZICOND-NEXT: ret 160entry: 161 %and = and i8 %cond, 1 162 %cmp10 = icmp ne i8 %and, 1 163 %0 = xor i32 %B, %A 164 %1 = select i1 %cmp10, i32 %A, i32 %0 165 ret i32 %1 166} 167 168define i16 @select_xor_3(i16 %A, i8 %cond) { 169; RV32IM-LABEL: select_xor_3: 170; RV32IM: # %bb.0: # %entry 171; RV32IM-NEXT: andi a1, a1, 1 172; RV32IM-NEXT: addi a1, a1, -1 173; RV32IM-NEXT: andi a1, a1, 43 174; RV32IM-NEXT: xor a0, a0, a1 175; RV32IM-NEXT: ret 176; 177; RV64IM-LABEL: select_xor_3: 178; RV64IM: # %bb.0: # %entry 179; RV64IM-NEXT: andi a1, a1, 1 180; RV64IM-NEXT: addi a1, a1, -1 181; RV64IM-NEXT: andi a1, a1, 43 182; RV64IM-NEXT: xor a0, a0, a1 183; RV64IM-NEXT: ret 184; 185; RV64IMXVTCONDOPS-LABEL: select_xor_3: 186; RV64IMXVTCONDOPS: # %bb.0: # %entry 187; RV64IMXVTCONDOPS-NEXT: andi a1, a1, 1 188; RV64IMXVTCONDOPS-NEXT: li a2, 43 189; RV64IMXVTCONDOPS-NEXT: vt.maskcn a1, a2, a1 190; RV64IMXVTCONDOPS-NEXT: xor a0, a0, a1 191; RV64IMXVTCONDOPS-NEXT: ret 192; 193; CHECKZICOND-LABEL: select_xor_3: 194; CHECKZICOND: # %bb.0: # %entry 195; CHECKZICOND-NEXT: andi a1, a1, 1 196; CHECKZICOND-NEXT: li a2, 43 197; CHECKZICOND-NEXT: czero.nez a1, a2, a1 198; CHECKZICOND-NEXT: xor a0, a0, a1 199; CHECKZICOND-NEXT: ret 200entry: 201 %and = and i8 %cond, 1 202 %cmp10 = icmp eq i8 %and, 0 203 %0 = xor i16 %A, 43 204 %1 = select i1 %cmp10, i16 %0, i16 %A 205 ret i16 %1 206} 207 208; Equivalent to above, but with icmp ne (and %cond, 1), 1 instead of 209; icmp eq (and %cond, 1), 0 210define i16 @select_xor_3b(i16 %A, i8 %cond) { 211; RV32IM-LABEL: select_xor_3b: 212; RV32IM: # %bb.0: # %entry 213; RV32IM-NEXT: andi a1, a1, 1 214; RV32IM-NEXT: addi a1, a1, -1 215; RV32IM-NEXT: andi a1, a1, 43 216; RV32IM-NEXT: xor a0, a0, a1 217; RV32IM-NEXT: ret 218; 219; RV64IM-LABEL: select_xor_3b: 220; RV64IM: # %bb.0: # %entry 221; RV64IM-NEXT: andi a1, a1, 1 222; RV64IM-NEXT: addi a1, a1, -1 223; RV64IM-NEXT: andi a1, a1, 43 224; RV64IM-NEXT: xor a0, a0, a1 225; RV64IM-NEXT: ret 226; 227; RV64IMXVTCONDOPS-LABEL: select_xor_3b: 228; RV64IMXVTCONDOPS: # %bb.0: # %entry 229; RV64IMXVTCONDOPS-NEXT: andi a1, a1, 1 230; RV64IMXVTCONDOPS-NEXT: li a2, 43 231; RV64IMXVTCONDOPS-NEXT: vt.maskcn a1, a2, a1 232; RV64IMXVTCONDOPS-NEXT: xor a0, a0, a1 233; RV64IMXVTCONDOPS-NEXT: ret 234; 235; CHECKZICOND-LABEL: select_xor_3b: 236; CHECKZICOND: # %bb.0: # %entry 237; CHECKZICOND-NEXT: andi a1, a1, 1 238; CHECKZICOND-NEXT: li a2, 43 239; CHECKZICOND-NEXT: czero.nez a1, a2, a1 240; CHECKZICOND-NEXT: xor a0, a0, a1 241; CHECKZICOND-NEXT: ret 242entry: 243 %and = and i8 %cond, 1 244 %cmp10 = icmp ne i8 %and, 1 245 %0 = xor i16 %A, 43 246 %1 = select i1 %cmp10, i16 %0, i16 %A 247 ret i16 %1 248} 249 250define i32 @select_xor_4(i32 %A, i32 %B, i8 %cond) { 251; RV32IM-LABEL: select_xor_4: 252; RV32IM: # %bb.0: # %entry 253; RV32IM-NEXT: andi a2, a2, 1 254; RV32IM-NEXT: addi a2, a2, -1 255; RV32IM-NEXT: and a1, a2, a1 256; RV32IM-NEXT: xor a0, a0, a1 257; RV32IM-NEXT: ret 258; 259; RV64IM-LABEL: select_xor_4: 260; RV64IM: # %bb.0: # %entry 261; RV64IM-NEXT: andi a2, a2, 1 262; RV64IM-NEXT: addi a2, a2, -1 263; RV64IM-NEXT: and a1, a2, a1 264; RV64IM-NEXT: xor a0, a0, a1 265; RV64IM-NEXT: ret 266; 267; RV64IMXVTCONDOPS-LABEL: select_xor_4: 268; RV64IMXVTCONDOPS: # %bb.0: # %entry 269; RV64IMXVTCONDOPS-NEXT: andi a2, a2, 1 270; RV64IMXVTCONDOPS-NEXT: vt.maskcn a1, a1, a2 271; RV64IMXVTCONDOPS-NEXT: xor a0, a0, a1 272; RV64IMXVTCONDOPS-NEXT: ret 273; 274; CHECKZICOND-LABEL: select_xor_4: 275; CHECKZICOND: # %bb.0: # %entry 276; CHECKZICOND-NEXT: andi a2, a2, 1 277; CHECKZICOND-NEXT: czero.nez a1, a1, a2 278; CHECKZICOND-NEXT: xor a0, a0, a1 279; CHECKZICOND-NEXT: ret 280entry: 281 %and = and i8 %cond, 1 282 %cmp10 = icmp eq i8 %and, 0 283 %0 = xor i32 %B, %A 284 %1 = select i1 %cmp10, i32 %0, i32 %A 285 ret i32 %1 286} 287 288; Equivalent to above, but with icmp ne (and %cond, 1), 1 instead of 289; icmp eq (and %cond, 1), 0 290define i32 @select_xor_4b(i32 %A, i32 %B, i8 %cond) { 291; RV32IM-LABEL: select_xor_4b: 292; RV32IM: # %bb.0: # %entry 293; RV32IM-NEXT: andi a2, a2, 1 294; RV32IM-NEXT: addi a2, a2, -1 295; RV32IM-NEXT: and a1, a2, a1 296; RV32IM-NEXT: xor a0, a0, a1 297; RV32IM-NEXT: ret 298; 299; RV64IM-LABEL: select_xor_4b: 300; RV64IM: # %bb.0: # %entry 301; RV64IM-NEXT: andi a2, a2, 1 302; RV64IM-NEXT: addi a2, a2, -1 303; RV64IM-NEXT: and a1, a2, a1 304; RV64IM-NEXT: xor a0, a0, a1 305; RV64IM-NEXT: ret 306; 307; RV64IMXVTCONDOPS-LABEL: select_xor_4b: 308; RV64IMXVTCONDOPS: # %bb.0: # %entry 309; RV64IMXVTCONDOPS-NEXT: andi a2, a2, 1 310; RV64IMXVTCONDOPS-NEXT: vt.maskcn a1, a1, a2 311; RV64IMXVTCONDOPS-NEXT: xor a0, a0, a1 312; RV64IMXVTCONDOPS-NEXT: ret 313; 314; CHECKZICOND-LABEL: select_xor_4b: 315; CHECKZICOND: # %bb.0: # %entry 316; CHECKZICOND-NEXT: andi a2, a2, 1 317; CHECKZICOND-NEXT: czero.nez a1, a1, a2 318; CHECKZICOND-NEXT: xor a0, a0, a1 319; CHECKZICOND-NEXT: ret 320entry: 321 %and = and i8 %cond, 1 322 %cmp10 = icmp ne i8 %and, 1 323 %0 = xor i32 %B, %A 324 %1 = select i1 %cmp10, i32 %0, i32 %A 325 ret i32 %1 326} 327 328define i32 @select_or(i32 %A, i32 %B, i8 %cond) { 329; RV32IM-LABEL: select_or: 330; RV32IM: # %bb.0: # %entry 331; RV32IM-NEXT: slli a2, a2, 31 332; RV32IM-NEXT: srai a2, a2, 31 333; RV32IM-NEXT: and a1, a2, a1 334; RV32IM-NEXT: or a0, a0, a1 335; RV32IM-NEXT: ret 336; 337; RV64IM-LABEL: select_or: 338; RV64IM: # %bb.0: # %entry 339; RV64IM-NEXT: slli a2, a2, 63 340; RV64IM-NEXT: srai a2, a2, 63 341; RV64IM-NEXT: and a1, a2, a1 342; RV64IM-NEXT: or a0, a0, a1 343; RV64IM-NEXT: ret 344; 345; RV64IMXVTCONDOPS-LABEL: select_or: 346; RV64IMXVTCONDOPS: # %bb.0: # %entry 347; RV64IMXVTCONDOPS-NEXT: andi a2, a2, 1 348; RV64IMXVTCONDOPS-NEXT: vt.maskc a1, a1, a2 349; RV64IMXVTCONDOPS-NEXT: or a0, a0, a1 350; RV64IMXVTCONDOPS-NEXT: ret 351; 352; CHECKZICOND-LABEL: select_or: 353; CHECKZICOND: # %bb.0: # %entry 354; CHECKZICOND-NEXT: andi a2, a2, 1 355; CHECKZICOND-NEXT: czero.eqz a1, a1, a2 356; CHECKZICOND-NEXT: or a0, a0, a1 357; CHECKZICOND-NEXT: ret 358entry: 359 %and = and i8 %cond, 1 360 %cmp10 = icmp eq i8 %and, 0 361 %0 = or i32 %B, %A 362 %1 = select i1 %cmp10, i32 %A, i32 %0 363 ret i32 %1 364} 365 366; Equivalent to above, but with icmp ne (and %cond, 1), 1 instead of 367; icmp eq (and %cond, 1), 0 368define i32 @select_or_b(i32 %A, i32 %B, i8 %cond) { 369; RV32IM-LABEL: select_or_b: 370; RV32IM: # %bb.0: # %entry 371; RV32IM-NEXT: slli a2, a2, 31 372; RV32IM-NEXT: srai a2, a2, 31 373; RV32IM-NEXT: and a1, a2, a1 374; RV32IM-NEXT: or a0, a0, a1 375; RV32IM-NEXT: ret 376; 377; RV64IM-LABEL: select_or_b: 378; RV64IM: # %bb.0: # %entry 379; RV64IM-NEXT: slli a2, a2, 63 380; RV64IM-NEXT: srai a2, a2, 63 381; RV64IM-NEXT: and a1, a2, a1 382; RV64IM-NEXT: or a0, a0, a1 383; RV64IM-NEXT: ret 384; 385; RV64IMXVTCONDOPS-LABEL: select_or_b: 386; RV64IMXVTCONDOPS: # %bb.0: # %entry 387; RV64IMXVTCONDOPS-NEXT: andi a2, a2, 1 388; RV64IMXVTCONDOPS-NEXT: vt.maskc a1, a1, a2 389; RV64IMXVTCONDOPS-NEXT: or a0, a0, a1 390; RV64IMXVTCONDOPS-NEXT: ret 391; 392; CHECKZICOND-LABEL: select_or_b: 393; CHECKZICOND: # %bb.0: # %entry 394; CHECKZICOND-NEXT: andi a2, a2, 1 395; CHECKZICOND-NEXT: czero.eqz a1, a1, a2 396; CHECKZICOND-NEXT: or a0, a0, a1 397; CHECKZICOND-NEXT: ret 398entry: 399 %and = and i8 %cond, 1 400 %cmp10 = icmp ne i8 %and, 1 401 %0 = or i32 %B, %A 402 %1 = select i1 %cmp10, i32 %A, i32 %0 403 ret i32 %1 404} 405 406define i32 @select_or_1(i32 %A, i32 %B, i32 %cond) { 407; RV32IM-LABEL: select_or_1: 408; RV32IM: # %bb.0: # %entry 409; RV32IM-NEXT: slli a2, a2, 31 410; RV32IM-NEXT: srai a2, a2, 31 411; RV32IM-NEXT: and a1, a2, a1 412; RV32IM-NEXT: or a0, a0, a1 413; RV32IM-NEXT: ret 414; 415; RV64IM-LABEL: select_or_1: 416; RV64IM: # %bb.0: # %entry 417; RV64IM-NEXT: slli a2, a2, 63 418; RV64IM-NEXT: srai a2, a2, 63 419; RV64IM-NEXT: and a1, a2, a1 420; RV64IM-NEXT: or a0, a0, a1 421; RV64IM-NEXT: ret 422; 423; RV64IMXVTCONDOPS-LABEL: select_or_1: 424; RV64IMXVTCONDOPS: # %bb.0: # %entry 425; RV64IMXVTCONDOPS-NEXT: andi a2, a2, 1 426; RV64IMXVTCONDOPS-NEXT: vt.maskc a1, a1, a2 427; RV64IMXVTCONDOPS-NEXT: or a0, a0, a1 428; RV64IMXVTCONDOPS-NEXT: ret 429; 430; CHECKZICOND-LABEL: select_or_1: 431; CHECKZICOND: # %bb.0: # %entry 432; CHECKZICOND-NEXT: andi a2, a2, 1 433; CHECKZICOND-NEXT: czero.eqz a1, a1, a2 434; CHECKZICOND-NEXT: or a0, a0, a1 435; CHECKZICOND-NEXT: ret 436entry: 437 %and = and i32 %cond, 1 438 %cmp10 = icmp eq i32 %and, 0 439 %0 = or i32 %B, %A 440 %1 = select i1 %cmp10, i32 %A, i32 %0 441 ret i32 %1 442} 443 444; Equivalent to above, but with icmp ne (and %cond, 1), 1 instead of 445; icmp eq (and %cond, 1), 0 446define i32 @select_or_1b(i32 %A, i32 %B, i32 %cond) { 447; RV32IM-LABEL: select_or_1b: 448; RV32IM: # %bb.0: # %entry 449; RV32IM-NEXT: slli a2, a2, 31 450; RV32IM-NEXT: srai a2, a2, 31 451; RV32IM-NEXT: and a1, a2, a1 452; RV32IM-NEXT: or a0, a0, a1 453; RV32IM-NEXT: ret 454; 455; RV64IM-LABEL: select_or_1b: 456; RV64IM: # %bb.0: # %entry 457; RV64IM-NEXT: slli a2, a2, 63 458; RV64IM-NEXT: srai a2, a2, 63 459; RV64IM-NEXT: and a1, a2, a1 460; RV64IM-NEXT: or a0, a0, a1 461; RV64IM-NEXT: ret 462; 463; RV64IMXVTCONDOPS-LABEL: select_or_1b: 464; RV64IMXVTCONDOPS: # %bb.0: # %entry 465; RV64IMXVTCONDOPS-NEXT: andi a2, a2, 1 466; RV64IMXVTCONDOPS-NEXT: vt.maskc a1, a1, a2 467; RV64IMXVTCONDOPS-NEXT: or a0, a0, a1 468; RV64IMXVTCONDOPS-NEXT: ret 469; 470; CHECKZICOND-LABEL: select_or_1b: 471; CHECKZICOND: # %bb.0: # %entry 472; CHECKZICOND-NEXT: andi a2, a2, 1 473; CHECKZICOND-NEXT: czero.eqz a1, a1, a2 474; CHECKZICOND-NEXT: or a0, a0, a1 475; CHECKZICOND-NEXT: ret 476entry: 477 %and = and i32 %cond, 1 478 %cmp10 = icmp ne i32 %and, 1 479 %0 = or i32 %B, %A 480 %1 = select i1 %cmp10, i32 %A, i32 %0 481 ret i32 %1 482} 483 484define i32 @select_or_2(i32 %A, i32 %B, i8 %cond) { 485; RV32IM-LABEL: select_or_2: 486; RV32IM: # %bb.0: # %entry 487; RV32IM-NEXT: andi a2, a2, 1 488; RV32IM-NEXT: addi a2, a2, -1 489; RV32IM-NEXT: and a1, a2, a1 490; RV32IM-NEXT: or a0, a0, a1 491; RV32IM-NEXT: ret 492; 493; RV64IM-LABEL: select_or_2: 494; RV64IM: # %bb.0: # %entry 495; RV64IM-NEXT: andi a2, a2, 1 496; RV64IM-NEXT: addi a2, a2, -1 497; RV64IM-NEXT: and a1, a2, a1 498; RV64IM-NEXT: or a0, a0, a1 499; RV64IM-NEXT: ret 500; 501; RV64IMXVTCONDOPS-LABEL: select_or_2: 502; RV64IMXVTCONDOPS: # %bb.0: # %entry 503; RV64IMXVTCONDOPS-NEXT: andi a2, a2, 1 504; RV64IMXVTCONDOPS-NEXT: vt.maskcn a1, a1, a2 505; RV64IMXVTCONDOPS-NEXT: or a0, a0, a1 506; RV64IMXVTCONDOPS-NEXT: ret 507; 508; CHECKZICOND-LABEL: select_or_2: 509; CHECKZICOND: # %bb.0: # %entry 510; CHECKZICOND-NEXT: andi a2, a2, 1 511; CHECKZICOND-NEXT: czero.nez a1, a1, a2 512; CHECKZICOND-NEXT: or a0, a0, a1 513; CHECKZICOND-NEXT: ret 514entry: 515 %and = and i8 %cond, 1 516 %cmp10 = icmp eq i8 %and, 0 517 %0 = or i32 %B, %A 518 %1 = select i1 %cmp10, i32 %0, i32 %A 519 ret i32 %1 520} 521 522; Equivalent to above, but with icmp ne (and %cond, 1), 1 instead of 523; icmp eq (and %cond, 1), 0 524define i32 @select_or_2b(i32 %A, i32 %B, i8 %cond) { 525; RV32IM-LABEL: select_or_2b: 526; RV32IM: # %bb.0: # %entry 527; RV32IM-NEXT: andi a2, a2, 1 528; RV32IM-NEXT: addi a2, a2, -1 529; RV32IM-NEXT: and a1, a2, a1 530; RV32IM-NEXT: or a0, a0, a1 531; RV32IM-NEXT: ret 532; 533; RV64IM-LABEL: select_or_2b: 534; RV64IM: # %bb.0: # %entry 535; RV64IM-NEXT: andi a2, a2, 1 536; RV64IM-NEXT: addi a2, a2, -1 537; RV64IM-NEXT: and a1, a2, a1 538; RV64IM-NEXT: or a0, a0, a1 539; RV64IM-NEXT: ret 540; 541; RV64IMXVTCONDOPS-LABEL: select_or_2b: 542; RV64IMXVTCONDOPS: # %bb.0: # %entry 543; RV64IMXVTCONDOPS-NEXT: andi a2, a2, 1 544; RV64IMXVTCONDOPS-NEXT: vt.maskcn a1, a1, a2 545; RV64IMXVTCONDOPS-NEXT: or a0, a0, a1 546; RV64IMXVTCONDOPS-NEXT: ret 547; 548; CHECKZICOND-LABEL: select_or_2b: 549; CHECKZICOND: # %bb.0: # %entry 550; CHECKZICOND-NEXT: andi a2, a2, 1 551; CHECKZICOND-NEXT: czero.nez a1, a1, a2 552; CHECKZICOND-NEXT: or a0, a0, a1 553; CHECKZICOND-NEXT: ret 554entry: 555 %and = and i8 %cond, 1 556 %cmp10 = icmp ne i8 %and, 1 557 %0 = or i32 %B, %A 558 %1 = select i1 %cmp10, i32 %0, i32 %A 559 ret i32 %1 560} 561 562define i32 @select_or_3(i32 %A, i32 %B, i32 %cond) { 563; RV32IM-LABEL: select_or_3: 564; RV32IM: # %bb.0: # %entry 565; RV32IM-NEXT: andi a2, a2, 1 566; RV32IM-NEXT: addi a2, a2, -1 567; RV32IM-NEXT: and a1, a2, a1 568; RV32IM-NEXT: or a0, a0, a1 569; RV32IM-NEXT: ret 570; 571; RV64IM-LABEL: select_or_3: 572; RV64IM: # %bb.0: # %entry 573; RV64IM-NEXT: andi a2, a2, 1 574; RV64IM-NEXT: addi a2, a2, -1 575; RV64IM-NEXT: and a1, a2, a1 576; RV64IM-NEXT: or a0, a0, a1 577; RV64IM-NEXT: ret 578; 579; RV64IMXVTCONDOPS-LABEL: select_or_3: 580; RV64IMXVTCONDOPS: # %bb.0: # %entry 581; RV64IMXVTCONDOPS-NEXT: andi a2, a2, 1 582; RV64IMXVTCONDOPS-NEXT: vt.maskcn a1, a1, a2 583; RV64IMXVTCONDOPS-NEXT: or a0, a0, a1 584; RV64IMXVTCONDOPS-NEXT: ret 585; 586; CHECKZICOND-LABEL: select_or_3: 587; CHECKZICOND: # %bb.0: # %entry 588; CHECKZICOND-NEXT: andi a2, a2, 1 589; CHECKZICOND-NEXT: czero.nez a1, a1, a2 590; CHECKZICOND-NEXT: or a0, a0, a1 591; CHECKZICOND-NEXT: ret 592entry: 593 %and = and i32 %cond, 1 594 %cmp10 = icmp eq i32 %and, 0 595 %0 = or i32 %B, %A 596 %1 = select i1 %cmp10, i32 %0, i32 %A 597 ret i32 %1 598} 599 600; Equivalent to above, but with icmp ne (and %cond, 1), 1 instead of 601; icmp eq (and %cond, 1), 0 602define i32 @select_or_3b(i32 %A, i32 %B, i32 %cond) { 603; RV32IM-LABEL: select_or_3b: 604; RV32IM: # %bb.0: # %entry 605; RV32IM-NEXT: andi a2, a2, 1 606; RV32IM-NEXT: addi a2, a2, -1 607; RV32IM-NEXT: and a1, a2, a1 608; RV32IM-NEXT: or a0, a0, a1 609; RV32IM-NEXT: ret 610; 611; RV64IM-LABEL: select_or_3b: 612; RV64IM: # %bb.0: # %entry 613; RV64IM-NEXT: andi a2, a2, 1 614; RV64IM-NEXT: addi a2, a2, -1 615; RV64IM-NEXT: and a1, a2, a1 616; RV64IM-NEXT: or a0, a0, a1 617; RV64IM-NEXT: ret 618; 619; RV64IMXVTCONDOPS-LABEL: select_or_3b: 620; RV64IMXVTCONDOPS: # %bb.0: # %entry 621; RV64IMXVTCONDOPS-NEXT: andi a2, a2, 1 622; RV64IMXVTCONDOPS-NEXT: vt.maskcn a1, a1, a2 623; RV64IMXVTCONDOPS-NEXT: or a0, a0, a1 624; RV64IMXVTCONDOPS-NEXT: ret 625; 626; CHECKZICOND-LABEL: select_or_3b: 627; CHECKZICOND: # %bb.0: # %entry 628; CHECKZICOND-NEXT: andi a2, a2, 1 629; CHECKZICOND-NEXT: czero.nez a1, a1, a2 630; CHECKZICOND-NEXT: or a0, a0, a1 631; CHECKZICOND-NEXT: ret 632entry: 633 %and = and i32 %cond, 1 634 %cmp10 = icmp ne i32 %and, 1 635 %0 = or i32 %B, %A 636 %1 = select i1 %cmp10, i32 %0, i32 %A 637 ret i32 %1 638} 639 640define i32 @select_add_1(i1 zeroext %cond, i32 %a, i32 %b) { 641; RV32IM-LABEL: select_add_1: 642; RV32IM: # %bb.0: # %entry 643; RV32IM-NEXT: neg a0, a0 644; RV32IM-NEXT: and a0, a0, a1 645; RV32IM-NEXT: add a0, a2, a0 646; RV32IM-NEXT: ret 647; 648; RV64IM-LABEL: select_add_1: 649; RV64IM: # %bb.0: # %entry 650; RV64IM-NEXT: negw a0, a0 651; RV64IM-NEXT: and a0, a0, a1 652; RV64IM-NEXT: addw a0, a2, a0 653; RV64IM-NEXT: ret 654; 655; RV64IMXVTCONDOPS-LABEL: select_add_1: 656; RV64IMXVTCONDOPS: # %bb.0: # %entry 657; RV64IMXVTCONDOPS-NEXT: vt.maskc a0, a1, a0 658; RV64IMXVTCONDOPS-NEXT: addw a0, a2, a0 659; RV64IMXVTCONDOPS-NEXT: ret 660; 661; RV32IMZICOND-LABEL: select_add_1: 662; RV32IMZICOND: # %bb.0: # %entry 663; RV32IMZICOND-NEXT: czero.eqz a0, a1, a0 664; RV32IMZICOND-NEXT: add a0, a2, a0 665; RV32IMZICOND-NEXT: ret 666; 667; RV64IMZICOND-LABEL: select_add_1: 668; RV64IMZICOND: # %bb.0: # %entry 669; RV64IMZICOND-NEXT: czero.eqz a0, a1, a0 670; RV64IMZICOND-NEXT: addw a0, a2, a0 671; RV64IMZICOND-NEXT: ret 672entry: 673 %c = add i32 %a, %b 674 %res = select i1 %cond, i32 %c, i32 %b 675 ret i32 %res 676} 677 678define i32 @select_add_2(i1 zeroext %cond, i32 %a, i32 %b) { 679; RV32IM-LABEL: select_add_2: 680; RV32IM: # %bb.0: # %entry 681; RV32IM-NEXT: addi a0, a0, -1 682; RV32IM-NEXT: and a0, a0, a2 683; RV32IM-NEXT: add a0, a1, a0 684; RV32IM-NEXT: ret 685; 686; RV64IM-LABEL: select_add_2: 687; RV64IM: # %bb.0: # %entry 688; RV64IM-NEXT: addi a0, a0, -1 689; RV64IM-NEXT: and a0, a0, a2 690; RV64IM-NEXT: addw a0, a1, a0 691; RV64IM-NEXT: ret 692; 693; RV64IMXVTCONDOPS-LABEL: select_add_2: 694; RV64IMXVTCONDOPS: # %bb.0: # %entry 695; RV64IMXVTCONDOPS-NEXT: vt.maskcn a0, a2, a0 696; RV64IMXVTCONDOPS-NEXT: addw a0, a1, a0 697; RV64IMXVTCONDOPS-NEXT: ret 698; 699; RV32IMZICOND-LABEL: select_add_2: 700; RV32IMZICOND: # %bb.0: # %entry 701; RV32IMZICOND-NEXT: czero.nez a0, a2, a0 702; RV32IMZICOND-NEXT: add a0, a1, a0 703; RV32IMZICOND-NEXT: ret 704; 705; RV64IMZICOND-LABEL: select_add_2: 706; RV64IMZICOND: # %bb.0: # %entry 707; RV64IMZICOND-NEXT: czero.nez a0, a2, a0 708; RV64IMZICOND-NEXT: addw a0, a1, a0 709; RV64IMZICOND-NEXT: ret 710entry: 711 %c = add i32 %a, %b 712 %res = select i1 %cond, i32 %a, i32 %c 713 ret i32 %res 714} 715 716define i32 @select_add_3(i1 zeroext %cond, i32 %a) { 717; RV32IM-LABEL: select_add_3: 718; RV32IM: # %bb.0: # %entry 719; RV32IM-NEXT: addi a0, a0, -1 720; RV32IM-NEXT: andi a0, a0, 42 721; RV32IM-NEXT: add a0, a1, a0 722; RV32IM-NEXT: ret 723; 724; RV64IM-LABEL: select_add_3: 725; RV64IM: # %bb.0: # %entry 726; RV64IM-NEXT: addi a0, a0, -1 727; RV64IM-NEXT: andi a0, a0, 42 728; RV64IM-NEXT: addw a0, a1, a0 729; RV64IM-NEXT: ret 730; 731; RV64IMXVTCONDOPS-LABEL: select_add_3: 732; RV64IMXVTCONDOPS: # %bb.0: # %entry 733; RV64IMXVTCONDOPS-NEXT: li a2, 42 734; RV64IMXVTCONDOPS-NEXT: vt.maskcn a0, a2, a0 735; RV64IMXVTCONDOPS-NEXT: addw a0, a1, a0 736; RV64IMXVTCONDOPS-NEXT: ret 737; 738; RV32IMZICOND-LABEL: select_add_3: 739; RV32IMZICOND: # %bb.0: # %entry 740; RV32IMZICOND-NEXT: li a2, 42 741; RV32IMZICOND-NEXT: czero.nez a0, a2, a0 742; RV32IMZICOND-NEXT: add a0, a1, a0 743; RV32IMZICOND-NEXT: ret 744; 745; RV64IMZICOND-LABEL: select_add_3: 746; RV64IMZICOND: # %bb.0: # %entry 747; RV64IMZICOND-NEXT: li a2, 42 748; RV64IMZICOND-NEXT: czero.nez a0, a2, a0 749; RV64IMZICOND-NEXT: addw a0, a1, a0 750; RV64IMZICOND-NEXT: ret 751entry: 752 %c = add i32 %a, 42 753 %res = select i1 %cond, i32 %a, i32 %c 754 ret i32 %res 755} 756 757define i32 @select_sub_1(i1 zeroext %cond, i32 %a, i32 %b) { 758; RV32IM-LABEL: select_sub_1: 759; RV32IM: # %bb.0: # %entry 760; RV32IM-NEXT: beqz a0, .LBB19_2 761; RV32IM-NEXT: # %bb.1: 762; RV32IM-NEXT: sub a2, a1, a2 763; RV32IM-NEXT: .LBB19_2: # %entry 764; RV32IM-NEXT: mv a0, a2 765; RV32IM-NEXT: ret 766; 767; RV64IM-LABEL: select_sub_1: 768; RV64IM: # %bb.0: # %entry 769; RV64IM-NEXT: beqz a0, .LBB19_2 770; RV64IM-NEXT: # %bb.1: 771; RV64IM-NEXT: subw a2, a1, a2 772; RV64IM-NEXT: .LBB19_2: # %entry 773; RV64IM-NEXT: mv a0, a2 774; RV64IM-NEXT: ret 775; 776; RV64IMXVTCONDOPS-LABEL: select_sub_1: 777; RV64IMXVTCONDOPS: # %bb.0: # %entry 778; RV64IMXVTCONDOPS-NEXT: subw a1, a1, a2 779; RV64IMXVTCONDOPS-NEXT: vt.maskcn a2, a2, a0 780; RV64IMXVTCONDOPS-NEXT: vt.maskc a0, a1, a0 781; RV64IMXVTCONDOPS-NEXT: or a0, a0, a2 782; RV64IMXVTCONDOPS-NEXT: ret 783; 784; RV32IMZICOND-LABEL: select_sub_1: 785; RV32IMZICOND: # %bb.0: # %entry 786; RV32IMZICOND-NEXT: sub a1, a1, a2 787; RV32IMZICOND-NEXT: czero.nez a2, a2, a0 788; RV32IMZICOND-NEXT: czero.eqz a0, a1, a0 789; RV32IMZICOND-NEXT: or a0, a0, a2 790; RV32IMZICOND-NEXT: ret 791; 792; RV64IMZICOND-LABEL: select_sub_1: 793; RV64IMZICOND: # %bb.0: # %entry 794; RV64IMZICOND-NEXT: subw a1, a1, a2 795; RV64IMZICOND-NEXT: czero.nez a2, a2, a0 796; RV64IMZICOND-NEXT: czero.eqz a0, a1, a0 797; RV64IMZICOND-NEXT: or a0, a0, a2 798; RV64IMZICOND-NEXT: ret 799entry: 800 %c = sub i32 %a, %b 801 %res = select i1 %cond, i32 %c, i32 %b 802 ret i32 %res 803} 804 805define i32 @select_sub_2(i1 zeroext %cond, i32 %a, i32 %b) { 806; RV32IM-LABEL: select_sub_2: 807; RV32IM: # %bb.0: # %entry 808; RV32IM-NEXT: addi a0, a0, -1 809; RV32IM-NEXT: and a0, a0, a2 810; RV32IM-NEXT: sub a0, a1, a0 811; RV32IM-NEXT: ret 812; 813; RV64IM-LABEL: select_sub_2: 814; RV64IM: # %bb.0: # %entry 815; RV64IM-NEXT: addi a0, a0, -1 816; RV64IM-NEXT: and a0, a0, a2 817; RV64IM-NEXT: subw a0, a1, a0 818; RV64IM-NEXT: ret 819; 820; RV64IMXVTCONDOPS-LABEL: select_sub_2: 821; RV64IMXVTCONDOPS: # %bb.0: # %entry 822; RV64IMXVTCONDOPS-NEXT: vt.maskcn a0, a2, a0 823; RV64IMXVTCONDOPS-NEXT: subw a0, a1, a0 824; RV64IMXVTCONDOPS-NEXT: ret 825; 826; RV32IMZICOND-LABEL: select_sub_2: 827; RV32IMZICOND: # %bb.0: # %entry 828; RV32IMZICOND-NEXT: czero.nez a0, a2, a0 829; RV32IMZICOND-NEXT: sub a0, a1, a0 830; RV32IMZICOND-NEXT: ret 831; 832; RV64IMZICOND-LABEL: select_sub_2: 833; RV64IMZICOND: # %bb.0: # %entry 834; RV64IMZICOND-NEXT: czero.nez a0, a2, a0 835; RV64IMZICOND-NEXT: subw a0, a1, a0 836; RV64IMZICOND-NEXT: ret 837entry: 838 %c = sub i32 %a, %b 839 %res = select i1 %cond, i32 %a, i32 %c 840 ret i32 %res 841} 842 843define i32 @select_sub_3(i1 zeroext %cond, i32 %a) { 844; RV32IM-LABEL: select_sub_3: 845; RV32IM: # %bb.0: # %entry 846; RV32IM-NEXT: addi a0, a0, -1 847; RV32IM-NEXT: andi a0, a0, 42 848; RV32IM-NEXT: sub a0, a1, a0 849; RV32IM-NEXT: ret 850; 851; RV64IM-LABEL: select_sub_3: 852; RV64IM: # %bb.0: # %entry 853; RV64IM-NEXT: addi a0, a0, -1 854; RV64IM-NEXT: andi a0, a0, 42 855; RV64IM-NEXT: subw a0, a1, a0 856; RV64IM-NEXT: ret 857; 858; RV64IMXVTCONDOPS-LABEL: select_sub_3: 859; RV64IMXVTCONDOPS: # %bb.0: # %entry 860; RV64IMXVTCONDOPS-NEXT: li a2, 42 861; RV64IMXVTCONDOPS-NEXT: vt.maskcn a0, a2, a0 862; RV64IMXVTCONDOPS-NEXT: subw a0, a1, a0 863; RV64IMXVTCONDOPS-NEXT: ret 864; 865; RV32IMZICOND-LABEL: select_sub_3: 866; RV32IMZICOND: # %bb.0: # %entry 867; RV32IMZICOND-NEXT: li a2, 42 868; RV32IMZICOND-NEXT: czero.nez a0, a2, a0 869; RV32IMZICOND-NEXT: sub a0, a1, a0 870; RV32IMZICOND-NEXT: ret 871; 872; RV64IMZICOND-LABEL: select_sub_3: 873; RV64IMZICOND: # %bb.0: # %entry 874; RV64IMZICOND-NEXT: li a2, 42 875; RV64IMZICOND-NEXT: czero.nez a0, a2, a0 876; RV64IMZICOND-NEXT: subw a0, a1, a0 877; RV64IMZICOND-NEXT: ret 878entry: 879 %c = sub i32 %a, 42 880 %res = select i1 %cond, i32 %a, i32 %c 881 ret i32 %res 882} 883 884define i32 @select_and_1(i1 zeroext %cond, i32 %a, i32 %b) { 885; RV32IM-LABEL: select_and_1: 886; RV32IM: # %bb.0: # %entry 887; RV32IM-NEXT: beqz a0, .LBB22_2 888; RV32IM-NEXT: # %bb.1: 889; RV32IM-NEXT: and a2, a1, a2 890; RV32IM-NEXT: .LBB22_2: # %entry 891; RV32IM-NEXT: mv a0, a2 892; RV32IM-NEXT: ret 893; 894; RV64IM-LABEL: select_and_1: 895; RV64IM: # %bb.0: # %entry 896; RV64IM-NEXT: beqz a0, .LBB22_2 897; RV64IM-NEXT: # %bb.1: 898; RV64IM-NEXT: and a2, a1, a2 899; RV64IM-NEXT: .LBB22_2: # %entry 900; RV64IM-NEXT: mv a0, a2 901; RV64IM-NEXT: ret 902; 903; RV64IMXVTCONDOPS-LABEL: select_and_1: 904; RV64IMXVTCONDOPS: # %bb.0: # %entry 905; RV64IMXVTCONDOPS-NEXT: and a1, a1, a2 906; RV64IMXVTCONDOPS-NEXT: vt.maskcn a0, a2, a0 907; RV64IMXVTCONDOPS-NEXT: or a0, a1, a0 908; RV64IMXVTCONDOPS-NEXT: ret 909; 910; CHECKZICOND-LABEL: select_and_1: 911; CHECKZICOND: # %bb.0: # %entry 912; CHECKZICOND-NEXT: and a1, a1, a2 913; CHECKZICOND-NEXT: czero.nez a0, a2, a0 914; CHECKZICOND-NEXT: or a0, a1, a0 915; CHECKZICOND-NEXT: ret 916entry: 917 %c = and i32 %a, %b 918 %res = select i1 %cond, i32 %c, i32 %b 919 ret i32 %res 920} 921 922define i32 @select_and_2(i1 zeroext %cond, i32 %a, i32 %b) { 923; RV32IM-LABEL: select_and_2: 924; RV32IM: # %bb.0: # %entry 925; RV32IM-NEXT: bnez a0, .LBB23_2 926; RV32IM-NEXT: # %bb.1: # %entry 927; RV32IM-NEXT: and a1, a1, a2 928; RV32IM-NEXT: .LBB23_2: # %entry 929; RV32IM-NEXT: mv a0, a1 930; RV32IM-NEXT: ret 931; 932; RV64IM-LABEL: select_and_2: 933; RV64IM: # %bb.0: # %entry 934; RV64IM-NEXT: bnez a0, .LBB23_2 935; RV64IM-NEXT: # %bb.1: # %entry 936; RV64IM-NEXT: and a1, a1, a2 937; RV64IM-NEXT: .LBB23_2: # %entry 938; RV64IM-NEXT: mv a0, a1 939; RV64IM-NEXT: ret 940; 941; RV64IMXVTCONDOPS-LABEL: select_and_2: 942; RV64IMXVTCONDOPS: # %bb.0: # %entry 943; RV64IMXVTCONDOPS-NEXT: and a2, a1, a2 944; RV64IMXVTCONDOPS-NEXT: vt.maskc a0, a1, a0 945; RV64IMXVTCONDOPS-NEXT: or a0, a2, a0 946; RV64IMXVTCONDOPS-NEXT: ret 947; 948; CHECKZICOND-LABEL: select_and_2: 949; CHECKZICOND: # %bb.0: # %entry 950; CHECKZICOND-NEXT: and a2, a1, a2 951; CHECKZICOND-NEXT: czero.eqz a0, a1, a0 952; CHECKZICOND-NEXT: or a0, a2, a0 953; CHECKZICOND-NEXT: ret 954entry: 955 %c = and i32 %a, %b 956 %res = select i1 %cond, i32 %a, i32 %c 957 ret i32 %res 958} 959 960define i32 @select_and_3(i1 zeroext %cond, i32 %a) { 961; RV32IM-LABEL: select_and_3: 962; RV32IM: # %bb.0: # %entry 963; RV32IM-NEXT: bnez a0, .LBB24_2 964; RV32IM-NEXT: # %bb.1: # %entry 965; RV32IM-NEXT: andi a1, a1, 42 966; RV32IM-NEXT: .LBB24_2: # %entry 967; RV32IM-NEXT: mv a0, a1 968; RV32IM-NEXT: ret 969; 970; RV64IM-LABEL: select_and_3: 971; RV64IM: # %bb.0: # %entry 972; RV64IM-NEXT: bnez a0, .LBB24_2 973; RV64IM-NEXT: # %bb.1: # %entry 974; RV64IM-NEXT: andi a1, a1, 42 975; RV64IM-NEXT: .LBB24_2: # %entry 976; RV64IM-NEXT: mv a0, a1 977; RV64IM-NEXT: ret 978; 979; RV64IMXVTCONDOPS-LABEL: select_and_3: 980; RV64IMXVTCONDOPS: # %bb.0: # %entry 981; RV64IMXVTCONDOPS-NEXT: andi a2, a1, 42 982; RV64IMXVTCONDOPS-NEXT: vt.maskc a0, a1, a0 983; RV64IMXVTCONDOPS-NEXT: or a0, a2, a0 984; RV64IMXVTCONDOPS-NEXT: ret 985; 986; CHECKZICOND-LABEL: select_and_3: 987; CHECKZICOND: # %bb.0: # %entry 988; CHECKZICOND-NEXT: andi a2, a1, 42 989; CHECKZICOND-NEXT: czero.eqz a0, a1, a0 990; CHECKZICOND-NEXT: or a0, a2, a0 991; CHECKZICOND-NEXT: ret 992entry: 993 %c = and i32 %a, 42 994 %res = select i1 %cond, i32 %a, i32 %c 995 ret i32 %res 996} 997 998define i32 @select_udiv_1(i1 zeroext %cond, i32 %a, i32 %b) { 999; RV32IM-LABEL: select_udiv_1: 1000; RV32IM: # %bb.0: # %entry 1001; RV32IM-NEXT: beqz a0, .LBB25_2 1002; RV32IM-NEXT: # %bb.1: 1003; RV32IM-NEXT: divu a2, a1, a2 1004; RV32IM-NEXT: .LBB25_2: # %entry 1005; RV32IM-NEXT: mv a0, a2 1006; RV32IM-NEXT: ret 1007; 1008; RV64IM-LABEL: select_udiv_1: 1009; RV64IM: # %bb.0: # %entry 1010; RV64IM-NEXT: beqz a0, .LBB25_2 1011; RV64IM-NEXT: # %bb.1: 1012; RV64IM-NEXT: divuw a2, a1, a2 1013; RV64IM-NEXT: .LBB25_2: # %entry 1014; RV64IM-NEXT: mv a0, a2 1015; RV64IM-NEXT: ret 1016; 1017; RV64IMXVTCONDOPS-LABEL: select_udiv_1: 1018; RV64IMXVTCONDOPS: # %bb.0: # %entry 1019; RV64IMXVTCONDOPS-NEXT: divuw a1, a1, a2 1020; RV64IMXVTCONDOPS-NEXT: vt.maskcn a2, a2, a0 1021; RV64IMXVTCONDOPS-NEXT: vt.maskc a0, a1, a0 1022; RV64IMXVTCONDOPS-NEXT: or a0, a0, a2 1023; RV64IMXVTCONDOPS-NEXT: ret 1024; 1025; RV32IMZICOND-LABEL: select_udiv_1: 1026; RV32IMZICOND: # %bb.0: # %entry 1027; RV32IMZICOND-NEXT: divu a1, a1, a2 1028; RV32IMZICOND-NEXT: czero.nez a2, a2, a0 1029; RV32IMZICOND-NEXT: czero.eqz a0, a1, a0 1030; RV32IMZICOND-NEXT: or a0, a0, a2 1031; RV32IMZICOND-NEXT: ret 1032; 1033; RV64IMZICOND-LABEL: select_udiv_1: 1034; RV64IMZICOND: # %bb.0: # %entry 1035; RV64IMZICOND-NEXT: divuw a1, a1, a2 1036; RV64IMZICOND-NEXT: czero.nez a2, a2, a0 1037; RV64IMZICOND-NEXT: czero.eqz a0, a1, a0 1038; RV64IMZICOND-NEXT: or a0, a0, a2 1039; RV64IMZICOND-NEXT: ret 1040entry: 1041 %c = udiv i32 %a, %b 1042 %res = select i1 %cond, i32 %c, i32 %b 1043 ret i32 %res 1044} 1045 1046define i32 @select_udiv_2(i1 zeroext %cond, i32 %a, i32 %b) { 1047; RV32IM-LABEL: select_udiv_2: 1048; RV32IM: # %bb.0: # %entry 1049; RV32IM-NEXT: bnez a0, .LBB26_2 1050; RV32IM-NEXT: # %bb.1: # %entry 1051; RV32IM-NEXT: divu a1, a1, a2 1052; RV32IM-NEXT: .LBB26_2: # %entry 1053; RV32IM-NEXT: mv a0, a1 1054; RV32IM-NEXT: ret 1055; 1056; RV64IM-LABEL: select_udiv_2: 1057; RV64IM: # %bb.0: # %entry 1058; RV64IM-NEXT: bnez a0, .LBB26_2 1059; RV64IM-NEXT: # %bb.1: # %entry 1060; RV64IM-NEXT: divuw a1, a1, a2 1061; RV64IM-NEXT: .LBB26_2: # %entry 1062; RV64IM-NEXT: mv a0, a1 1063; RV64IM-NEXT: ret 1064; 1065; RV64IMXVTCONDOPS-LABEL: select_udiv_2: 1066; RV64IMXVTCONDOPS: # %bb.0: # %entry 1067; RV64IMXVTCONDOPS-NEXT: divuw a2, a1, a2 1068; RV64IMXVTCONDOPS-NEXT: vt.maskc a1, a1, a0 1069; RV64IMXVTCONDOPS-NEXT: vt.maskcn a0, a2, a0 1070; RV64IMXVTCONDOPS-NEXT: or a0, a1, a0 1071; RV64IMXVTCONDOPS-NEXT: ret 1072; 1073; RV32IMZICOND-LABEL: select_udiv_2: 1074; RV32IMZICOND: # %bb.0: # %entry 1075; RV32IMZICOND-NEXT: divu a2, a1, a2 1076; RV32IMZICOND-NEXT: czero.eqz a1, a1, a0 1077; RV32IMZICOND-NEXT: czero.nez a0, a2, a0 1078; RV32IMZICOND-NEXT: or a0, a1, a0 1079; RV32IMZICOND-NEXT: ret 1080; 1081; RV64IMZICOND-LABEL: select_udiv_2: 1082; RV64IMZICOND: # %bb.0: # %entry 1083; RV64IMZICOND-NEXT: divuw a2, a1, a2 1084; RV64IMZICOND-NEXT: czero.eqz a1, a1, a0 1085; RV64IMZICOND-NEXT: czero.nez a0, a2, a0 1086; RV64IMZICOND-NEXT: or a0, a1, a0 1087; RV64IMZICOND-NEXT: ret 1088entry: 1089 %c = udiv i32 %a, %b 1090 %res = select i1 %cond, i32 %a, i32 %c 1091 ret i32 %res 1092} 1093 1094define i32 @select_udiv_3(i1 zeroext %cond, i32 %a) { 1095; RV32IM-LABEL: select_udiv_3: 1096; RV32IM: # %bb.0: # %entry 1097; RV32IM-NEXT: bnez a0, .LBB27_2 1098; RV32IM-NEXT: # %bb.1: # %entry 1099; RV32IM-NEXT: srli a1, a1, 1 1100; RV32IM-NEXT: lui a0, 199729 1101; RV32IM-NEXT: addi a0, a0, -975 1102; RV32IM-NEXT: mulhu a1, a1, a0 1103; RV32IM-NEXT: srli a1, a1, 2 1104; RV32IM-NEXT: .LBB27_2: # %entry 1105; RV32IM-NEXT: mv a0, a1 1106; RV32IM-NEXT: ret 1107; 1108; RV64IM-LABEL: select_udiv_3: 1109; RV64IM: # %bb.0: # %entry 1110; RV64IM-NEXT: bnez a0, .LBB27_2 1111; RV64IM-NEXT: # %bb.1: # %entry 1112; RV64IM-NEXT: srliw a0, a1, 1 1113; RV64IM-NEXT: lui a1, 199729 1114; RV64IM-NEXT: addiw a1, a1, -975 1115; RV64IM-NEXT: mul a1, a0, a1 1116; RV64IM-NEXT: srli a1, a1, 34 1117; RV64IM-NEXT: .LBB27_2: # %entry 1118; RV64IM-NEXT: mv a0, a1 1119; RV64IM-NEXT: ret 1120; 1121; RV64IMXVTCONDOPS-LABEL: select_udiv_3: 1122; RV64IMXVTCONDOPS: # %bb.0: # %entry 1123; RV64IMXVTCONDOPS-NEXT: srliw a2, a1, 1 1124; RV64IMXVTCONDOPS-NEXT: lui a3, 199729 1125; RV64IMXVTCONDOPS-NEXT: addiw a3, a3, -975 1126; RV64IMXVTCONDOPS-NEXT: mul a2, a2, a3 1127; RV64IMXVTCONDOPS-NEXT: srli a2, a2, 34 1128; RV64IMXVTCONDOPS-NEXT: vt.maskc a1, a1, a0 1129; RV64IMXVTCONDOPS-NEXT: vt.maskcn a0, a2, a0 1130; RV64IMXVTCONDOPS-NEXT: or a0, a1, a0 1131; RV64IMXVTCONDOPS-NEXT: ret 1132; 1133; RV32IMZICOND-LABEL: select_udiv_3: 1134; RV32IMZICOND: # %bb.0: # %entry 1135; RV32IMZICOND-NEXT: srli a2, a1, 1 1136; RV32IMZICOND-NEXT: lui a3, 199729 1137; RV32IMZICOND-NEXT: addi a3, a3, -975 1138; RV32IMZICOND-NEXT: mulhu a2, a2, a3 1139; RV32IMZICOND-NEXT: srli a2, a2, 2 1140; RV32IMZICOND-NEXT: czero.eqz a1, a1, a0 1141; RV32IMZICOND-NEXT: czero.nez a0, a2, a0 1142; RV32IMZICOND-NEXT: or a0, a1, a0 1143; RV32IMZICOND-NEXT: ret 1144; 1145; RV64IMZICOND-LABEL: select_udiv_3: 1146; RV64IMZICOND: # %bb.0: # %entry 1147; RV64IMZICOND-NEXT: srliw a2, a1, 1 1148; RV64IMZICOND-NEXT: lui a3, 199729 1149; RV64IMZICOND-NEXT: addiw a3, a3, -975 1150; RV64IMZICOND-NEXT: mul a2, a2, a3 1151; RV64IMZICOND-NEXT: srli a2, a2, 34 1152; RV64IMZICOND-NEXT: czero.eqz a1, a1, a0 1153; RV64IMZICOND-NEXT: czero.nez a0, a2, a0 1154; RV64IMZICOND-NEXT: or a0, a1, a0 1155; RV64IMZICOND-NEXT: ret 1156entry: 1157 %c = udiv i32 %a, 42 1158 %res = select i1 %cond, i32 %a, i32 %c 1159 ret i32 %res 1160} 1161 1162define i32 @select_shl_1(i1 zeroext %cond, i32 %a, i32 %b) { 1163; RV32IM-LABEL: select_shl_1: 1164; RV32IM: # %bb.0: # %entry 1165; RV32IM-NEXT: beqz a0, .LBB28_2 1166; RV32IM-NEXT: # %bb.1: 1167; RV32IM-NEXT: sll a2, a1, a2 1168; RV32IM-NEXT: .LBB28_2: # %entry 1169; RV32IM-NEXT: mv a0, a2 1170; RV32IM-NEXT: ret 1171; 1172; RV64IM-LABEL: select_shl_1: 1173; RV64IM: # %bb.0: # %entry 1174; RV64IM-NEXT: beqz a0, .LBB28_2 1175; RV64IM-NEXT: # %bb.1: 1176; RV64IM-NEXT: sllw a2, a1, a2 1177; RV64IM-NEXT: .LBB28_2: # %entry 1178; RV64IM-NEXT: mv a0, a2 1179; RV64IM-NEXT: ret 1180; 1181; RV64IMXVTCONDOPS-LABEL: select_shl_1: 1182; RV64IMXVTCONDOPS: # %bb.0: # %entry 1183; RV64IMXVTCONDOPS-NEXT: sllw a1, a1, a2 1184; RV64IMXVTCONDOPS-NEXT: vt.maskcn a2, a2, a0 1185; RV64IMXVTCONDOPS-NEXT: vt.maskc a0, a1, a0 1186; RV64IMXVTCONDOPS-NEXT: or a0, a0, a2 1187; RV64IMXVTCONDOPS-NEXT: ret 1188; 1189; RV32IMZICOND-LABEL: select_shl_1: 1190; RV32IMZICOND: # %bb.0: # %entry 1191; RV32IMZICOND-NEXT: sll a1, a1, a2 1192; RV32IMZICOND-NEXT: czero.nez a2, a2, a0 1193; RV32IMZICOND-NEXT: czero.eqz a0, a1, a0 1194; RV32IMZICOND-NEXT: or a0, a0, a2 1195; RV32IMZICOND-NEXT: ret 1196; 1197; RV64IMZICOND-LABEL: select_shl_1: 1198; RV64IMZICOND: # %bb.0: # %entry 1199; RV64IMZICOND-NEXT: sllw a1, a1, a2 1200; RV64IMZICOND-NEXT: czero.nez a2, a2, a0 1201; RV64IMZICOND-NEXT: czero.eqz a0, a1, a0 1202; RV64IMZICOND-NEXT: or a0, a0, a2 1203; RV64IMZICOND-NEXT: ret 1204entry: 1205 %c = shl i32 %a, %b 1206 %res = select i1 %cond, i32 %c, i32 %b 1207 ret i32 %res 1208} 1209 1210define i32 @select_shl_2(i1 zeroext %cond, i32 %a, i32 %b) { 1211; RV32IM-LABEL: select_shl_2: 1212; RV32IM: # %bb.0: # %entry 1213; RV32IM-NEXT: addi a0, a0, -1 1214; RV32IM-NEXT: and a0, a0, a2 1215; RV32IM-NEXT: sll a0, a1, a0 1216; RV32IM-NEXT: ret 1217; 1218; RV64IM-LABEL: select_shl_2: 1219; RV64IM: # %bb.0: # %entry 1220; RV64IM-NEXT: addi a0, a0, -1 1221; RV64IM-NEXT: and a0, a0, a2 1222; RV64IM-NEXT: sllw a0, a1, a0 1223; RV64IM-NEXT: ret 1224; 1225; RV64IMXVTCONDOPS-LABEL: select_shl_2: 1226; RV64IMXVTCONDOPS: # %bb.0: # %entry 1227; RV64IMXVTCONDOPS-NEXT: vt.maskcn a0, a2, a0 1228; RV64IMXVTCONDOPS-NEXT: sllw a0, a1, a0 1229; RV64IMXVTCONDOPS-NEXT: ret 1230; 1231; RV32IMZICOND-LABEL: select_shl_2: 1232; RV32IMZICOND: # %bb.0: # %entry 1233; RV32IMZICOND-NEXT: czero.nez a0, a2, a0 1234; RV32IMZICOND-NEXT: sll a0, a1, a0 1235; RV32IMZICOND-NEXT: ret 1236; 1237; RV64IMZICOND-LABEL: select_shl_2: 1238; RV64IMZICOND: # %bb.0: # %entry 1239; RV64IMZICOND-NEXT: czero.nez a0, a2, a0 1240; RV64IMZICOND-NEXT: sllw a0, a1, a0 1241; RV64IMZICOND-NEXT: ret 1242entry: 1243 %c = shl i32 %a, %b 1244 %res = select i1 %cond, i32 %a, i32 %c 1245 ret i32 %res 1246} 1247 1248define i32 @select_shl_3(i1 zeroext %cond, i32 %a) { 1249; CHECK-LABEL: select_shl_3: 1250; CHECK: # %bb.0: # %entry 1251; CHECK-NEXT: mv a0, a1 1252; CHECK-NEXT: ret 1253entry: 1254 %c = shl i32 %a, 42 1255 %res = select i1 %cond, i32 %a, i32 %c 1256 ret i32 %res 1257} 1258 1259define i32 @select_ashr_1(i1 zeroext %cond, i32 %a, i32 %b) { 1260; RV32IM-LABEL: select_ashr_1: 1261; RV32IM: # %bb.0: # %entry 1262; RV32IM-NEXT: beqz a0, .LBB31_2 1263; RV32IM-NEXT: # %bb.1: 1264; RV32IM-NEXT: sra a2, a1, a2 1265; RV32IM-NEXT: .LBB31_2: # %entry 1266; RV32IM-NEXT: mv a0, a2 1267; RV32IM-NEXT: ret 1268; 1269; RV64IM-LABEL: select_ashr_1: 1270; RV64IM: # %bb.0: # %entry 1271; RV64IM-NEXT: beqz a0, .LBB31_2 1272; RV64IM-NEXT: # %bb.1: 1273; RV64IM-NEXT: sraw a2, a1, a2 1274; RV64IM-NEXT: .LBB31_2: # %entry 1275; RV64IM-NEXT: mv a0, a2 1276; RV64IM-NEXT: ret 1277; 1278; RV64IMXVTCONDOPS-LABEL: select_ashr_1: 1279; RV64IMXVTCONDOPS: # %bb.0: # %entry 1280; RV64IMXVTCONDOPS-NEXT: sraw a1, a1, a2 1281; RV64IMXVTCONDOPS-NEXT: vt.maskcn a2, a2, a0 1282; RV64IMXVTCONDOPS-NEXT: vt.maskc a0, a1, a0 1283; RV64IMXVTCONDOPS-NEXT: or a0, a0, a2 1284; RV64IMXVTCONDOPS-NEXT: ret 1285; 1286; RV32IMZICOND-LABEL: select_ashr_1: 1287; RV32IMZICOND: # %bb.0: # %entry 1288; RV32IMZICOND-NEXT: sra a1, a1, a2 1289; RV32IMZICOND-NEXT: czero.nez a2, a2, a0 1290; RV32IMZICOND-NEXT: czero.eqz a0, a1, a0 1291; RV32IMZICOND-NEXT: or a0, a0, a2 1292; RV32IMZICOND-NEXT: ret 1293; 1294; RV64IMZICOND-LABEL: select_ashr_1: 1295; RV64IMZICOND: # %bb.0: # %entry 1296; RV64IMZICOND-NEXT: sraw a1, a1, a2 1297; RV64IMZICOND-NEXT: czero.nez a2, a2, a0 1298; RV64IMZICOND-NEXT: czero.eqz a0, a1, a0 1299; RV64IMZICOND-NEXT: or a0, a0, a2 1300; RV64IMZICOND-NEXT: ret 1301entry: 1302 %c = ashr i32 %a, %b 1303 %res = select i1 %cond, i32 %c, i32 %b 1304 ret i32 %res 1305} 1306 1307define i32 @select_ashr_2(i1 zeroext %cond, i32 %a, i32 %b) { 1308; RV32IM-LABEL: select_ashr_2: 1309; RV32IM: # %bb.0: # %entry 1310; RV32IM-NEXT: addi a0, a0, -1 1311; RV32IM-NEXT: and a0, a0, a2 1312; RV32IM-NEXT: sra a0, a1, a0 1313; RV32IM-NEXT: ret 1314; 1315; RV64IM-LABEL: select_ashr_2: 1316; RV64IM: # %bb.0: # %entry 1317; RV64IM-NEXT: addi a0, a0, -1 1318; RV64IM-NEXT: and a0, a0, a2 1319; RV64IM-NEXT: sraw a0, a1, a0 1320; RV64IM-NEXT: ret 1321; 1322; RV64IMXVTCONDOPS-LABEL: select_ashr_2: 1323; RV64IMXVTCONDOPS: # %bb.0: # %entry 1324; RV64IMXVTCONDOPS-NEXT: vt.maskcn a0, a2, a0 1325; RV64IMXVTCONDOPS-NEXT: sraw a0, a1, a0 1326; RV64IMXVTCONDOPS-NEXT: ret 1327; 1328; RV32IMZICOND-LABEL: select_ashr_2: 1329; RV32IMZICOND: # %bb.0: # %entry 1330; RV32IMZICOND-NEXT: czero.nez a0, a2, a0 1331; RV32IMZICOND-NEXT: sra a0, a1, a0 1332; RV32IMZICOND-NEXT: ret 1333; 1334; RV64IMZICOND-LABEL: select_ashr_2: 1335; RV64IMZICOND: # %bb.0: # %entry 1336; RV64IMZICOND-NEXT: czero.nez a0, a2, a0 1337; RV64IMZICOND-NEXT: sraw a0, a1, a0 1338; RV64IMZICOND-NEXT: ret 1339entry: 1340 %c = ashr i32 %a, %b 1341 %res = select i1 %cond, i32 %a, i32 %c 1342 ret i32 %res 1343} 1344 1345define i32 @select_ashr_3(i1 zeroext %cond, i32 %a) { 1346; CHECK-LABEL: select_ashr_3: 1347; CHECK: # %bb.0: # %entry 1348; CHECK-NEXT: mv a0, a1 1349; CHECK-NEXT: ret 1350entry: 1351 %c = ashr i32 %a, 42 1352 %res = select i1 %cond, i32 %a, i32 %c 1353 ret i32 %res 1354} 1355 1356define i32 @select_lshr_1(i1 zeroext %cond, i32 %a, i32 %b) { 1357; RV32IM-LABEL: select_lshr_1: 1358; RV32IM: # %bb.0: # %entry 1359; RV32IM-NEXT: beqz a0, .LBB34_2 1360; RV32IM-NEXT: # %bb.1: 1361; RV32IM-NEXT: srl a2, a1, a2 1362; RV32IM-NEXT: .LBB34_2: # %entry 1363; RV32IM-NEXT: mv a0, a2 1364; RV32IM-NEXT: ret 1365; 1366; RV64IM-LABEL: select_lshr_1: 1367; RV64IM: # %bb.0: # %entry 1368; RV64IM-NEXT: beqz a0, .LBB34_2 1369; RV64IM-NEXT: # %bb.1: 1370; RV64IM-NEXT: srlw a2, a1, a2 1371; RV64IM-NEXT: .LBB34_2: # %entry 1372; RV64IM-NEXT: mv a0, a2 1373; RV64IM-NEXT: ret 1374; 1375; RV64IMXVTCONDOPS-LABEL: select_lshr_1: 1376; RV64IMXVTCONDOPS: # %bb.0: # %entry 1377; RV64IMXVTCONDOPS-NEXT: srlw a1, a1, a2 1378; RV64IMXVTCONDOPS-NEXT: vt.maskcn a2, a2, a0 1379; RV64IMXVTCONDOPS-NEXT: vt.maskc a0, a1, a0 1380; RV64IMXVTCONDOPS-NEXT: or a0, a0, a2 1381; RV64IMXVTCONDOPS-NEXT: ret 1382; 1383; RV32IMZICOND-LABEL: select_lshr_1: 1384; RV32IMZICOND: # %bb.0: # %entry 1385; RV32IMZICOND-NEXT: srl a1, a1, a2 1386; RV32IMZICOND-NEXT: czero.nez a2, a2, a0 1387; RV32IMZICOND-NEXT: czero.eqz a0, a1, a0 1388; RV32IMZICOND-NEXT: or a0, a0, a2 1389; RV32IMZICOND-NEXT: ret 1390; 1391; RV64IMZICOND-LABEL: select_lshr_1: 1392; RV64IMZICOND: # %bb.0: # %entry 1393; RV64IMZICOND-NEXT: srlw a1, a1, a2 1394; RV64IMZICOND-NEXT: czero.nez a2, a2, a0 1395; RV64IMZICOND-NEXT: czero.eqz a0, a1, a0 1396; RV64IMZICOND-NEXT: or a0, a0, a2 1397; RV64IMZICOND-NEXT: ret 1398entry: 1399 %c = lshr i32 %a, %b 1400 %res = select i1 %cond, i32 %c, i32 %b 1401 ret i32 %res 1402} 1403 1404define i32 @select_lshr_2(i1 zeroext %cond, i32 %a, i32 %b) { 1405; RV32IM-LABEL: select_lshr_2: 1406; RV32IM: # %bb.0: # %entry 1407; RV32IM-NEXT: addi a0, a0, -1 1408; RV32IM-NEXT: and a0, a0, a2 1409; RV32IM-NEXT: srl a0, a1, a0 1410; RV32IM-NEXT: ret 1411; 1412; RV64IM-LABEL: select_lshr_2: 1413; RV64IM: # %bb.0: # %entry 1414; RV64IM-NEXT: addi a0, a0, -1 1415; RV64IM-NEXT: and a0, a0, a2 1416; RV64IM-NEXT: srlw a0, a1, a0 1417; RV64IM-NEXT: ret 1418; 1419; RV64IMXVTCONDOPS-LABEL: select_lshr_2: 1420; RV64IMXVTCONDOPS: # %bb.0: # %entry 1421; RV64IMXVTCONDOPS-NEXT: vt.maskcn a0, a2, a0 1422; RV64IMXVTCONDOPS-NEXT: srlw a0, a1, a0 1423; RV64IMXVTCONDOPS-NEXT: ret 1424; 1425; RV32IMZICOND-LABEL: select_lshr_2: 1426; RV32IMZICOND: # %bb.0: # %entry 1427; RV32IMZICOND-NEXT: czero.nez a0, a2, a0 1428; RV32IMZICOND-NEXT: srl a0, a1, a0 1429; RV32IMZICOND-NEXT: ret 1430; 1431; RV64IMZICOND-LABEL: select_lshr_2: 1432; RV64IMZICOND: # %bb.0: # %entry 1433; RV64IMZICOND-NEXT: czero.nez a0, a2, a0 1434; RV64IMZICOND-NEXT: srlw a0, a1, a0 1435; RV64IMZICOND-NEXT: ret 1436entry: 1437 %c = lshr i32 %a, %b 1438 %res = select i1 %cond, i32 %a, i32 %c 1439 ret i32 %res 1440} 1441 1442define i32 @select_lshr_3(i1 zeroext %cond, i32 %a) { 1443; CHECK-LABEL: select_lshr_3: 1444; CHECK: # %bb.0: # %entry 1445; CHECK-NEXT: mv a0, a1 1446; CHECK-NEXT: ret 1447entry: 1448 %c = lshr i32 %a, 42 1449 %res = select i1 %cond, i32 %a, i32 %c 1450 ret i32 %res 1451} 1452 1453define i32 @select_cst_not1(i32 signext %a, i32 signext %b) { 1454; CHECK-LABEL: select_cst_not1: 1455; CHECK: # %bb.0: 1456; CHECK-NEXT: slt a0, a0, a1 1457; CHECK-NEXT: neg a0, a0 1458; CHECK-NEXT: xori a0, a0, -6 1459; CHECK-NEXT: ret 1460 %cond = icmp slt i32 %a, %b 1461 %ret = select i1 %cond, i32 5, i32 -6 1462 ret i32 %ret 1463} 1464 1465define i32 @select_cst_not2(i32 signext %a) { 1466; CHECK-LABEL: select_cst_not2: 1467; CHECK: # %bb.0: 1468; CHECK-NEXT: srai a0, a0, 31 1469; CHECK-NEXT: xori a0, a0, -6 1470; CHECK-NEXT: ret 1471 %cond = icmp slt i32 %a, 0 1472 %ret = select i1 %cond, i32 5, i32 -6 1473 ret i32 %ret 1474} 1475 1476define i32 @select_cst_not3(i32 signext %a) { 1477; CHECK-LABEL: select_cst_not3: 1478; CHECK: # %bb.0: 1479; CHECK-NEXT: srai a0, a0, 31 1480; CHECK-NEXT: xori a0, a0, 5 1481; CHECK-NEXT: ret 1482 %cond = icmp sgt i32 %a, -1 1483 %ret = select i1 %cond, i32 5, i32 -6 1484 ret i32 %ret 1485} 1486 1487define i32 @select_cst_not4(i32 signext %a, i32 signext %b) { 1488; RV32IM-LABEL: select_cst_not4: 1489; RV32IM: # %bb.0: 1490; RV32IM-NEXT: slt a0, a0, a1 1491; RV32IM-NEXT: lui a1, 524288 1492; RV32IM-NEXT: addi a1, a1, -1 1493; RV32IM-NEXT: add a0, a0, a1 1494; RV32IM-NEXT: ret 1495; 1496; RV64IM-LABEL: select_cst_not4: 1497; RV64IM: # %bb.0: 1498; RV64IM-NEXT: slt a0, a0, a1 1499; RV64IM-NEXT: lui a1, 524288 1500; RV64IM-NEXT: neg a0, a0 1501; RV64IM-NEXT: addiw a1, a1, -1 1502; RV64IM-NEXT: xor a0, a0, a1 1503; RV64IM-NEXT: ret 1504; 1505; RV64IMXVTCONDOPS-LABEL: select_cst_not4: 1506; RV64IMXVTCONDOPS: # %bb.0: 1507; RV64IMXVTCONDOPS-NEXT: slt a0, a0, a1 1508; RV64IMXVTCONDOPS-NEXT: lui a1, 524288 1509; RV64IMXVTCONDOPS-NEXT: neg a0, a0 1510; RV64IMXVTCONDOPS-NEXT: addiw a1, a1, -1 1511; RV64IMXVTCONDOPS-NEXT: xor a0, a0, a1 1512; RV64IMXVTCONDOPS-NEXT: ret 1513; 1514; RV32IMZICOND-LABEL: select_cst_not4: 1515; RV32IMZICOND: # %bb.0: 1516; RV32IMZICOND-NEXT: slt a0, a0, a1 1517; RV32IMZICOND-NEXT: lui a1, 524288 1518; RV32IMZICOND-NEXT: addi a1, a1, -1 1519; RV32IMZICOND-NEXT: add a0, a0, a1 1520; RV32IMZICOND-NEXT: ret 1521; 1522; RV64IMZICOND-LABEL: select_cst_not4: 1523; RV64IMZICOND: # %bb.0: 1524; RV64IMZICOND-NEXT: slt a0, a0, a1 1525; RV64IMZICOND-NEXT: lui a1, 524288 1526; RV64IMZICOND-NEXT: neg a0, a0 1527; RV64IMZICOND-NEXT: addiw a1, a1, -1 1528; RV64IMZICOND-NEXT: xor a0, a0, a1 1529; RV64IMZICOND-NEXT: ret 1530 %cond = icmp slt i32 %a, %b 1531 %ret = select i1 %cond, i32 -2147483648, i32 2147483647 1532 ret i32 %ret 1533} 1534 1535define i32 @select_cst_not5(i32 signext %a, i32 signext %b) { 1536; RV32IM-LABEL: select_cst_not5: 1537; RV32IM: # %bb.0: 1538; RV32IM-NEXT: slt a0, a0, a1 1539; RV32IM-NEXT: lui a1, 16 1540; RV32IM-NEXT: neg a0, a0 1541; RV32IM-NEXT: addi a1, a1, -5 1542; RV32IM-NEXT: xor a0, a0, a1 1543; RV32IM-NEXT: ret 1544; 1545; RV64IM-LABEL: select_cst_not5: 1546; RV64IM: # %bb.0: 1547; RV64IM-NEXT: slt a0, a0, a1 1548; RV64IM-NEXT: lui a1, 16 1549; RV64IM-NEXT: neg a0, a0 1550; RV64IM-NEXT: addiw a1, a1, -5 1551; RV64IM-NEXT: xor a0, a0, a1 1552; RV64IM-NEXT: ret 1553; 1554; RV64IMXVTCONDOPS-LABEL: select_cst_not5: 1555; RV64IMXVTCONDOPS: # %bb.0: 1556; RV64IMXVTCONDOPS-NEXT: slt a0, a0, a1 1557; RV64IMXVTCONDOPS-NEXT: lui a1, 16 1558; RV64IMXVTCONDOPS-NEXT: neg a0, a0 1559; RV64IMXVTCONDOPS-NEXT: addiw a1, a1, -5 1560; RV64IMXVTCONDOPS-NEXT: xor a0, a0, a1 1561; RV64IMXVTCONDOPS-NEXT: ret 1562; 1563; RV32IMZICOND-LABEL: select_cst_not5: 1564; RV32IMZICOND: # %bb.0: 1565; RV32IMZICOND-NEXT: slt a0, a0, a1 1566; RV32IMZICOND-NEXT: lui a1, 16 1567; RV32IMZICOND-NEXT: neg a0, a0 1568; RV32IMZICOND-NEXT: addi a1, a1, -5 1569; RV32IMZICOND-NEXT: xor a0, a0, a1 1570; RV32IMZICOND-NEXT: ret 1571; 1572; RV64IMZICOND-LABEL: select_cst_not5: 1573; RV64IMZICOND: # %bb.0: 1574; RV64IMZICOND-NEXT: slt a0, a0, a1 1575; RV64IMZICOND-NEXT: lui a1, 16 1576; RV64IMZICOND-NEXT: neg a0, a0 1577; RV64IMZICOND-NEXT: addiw a1, a1, -5 1578; RV64IMZICOND-NEXT: xor a0, a0, a1 1579; RV64IMZICOND-NEXT: ret 1580 %cond = icmp slt i32 %a, %b 1581 %ret = select i1 %cond, i32 -65532, i32 65531 1582 ret i32 %ret 1583} 1584 1585define i32 @select_cst_unknown(i32 signext %a, i32 signext %b) { 1586; RV32IM-LABEL: select_cst_unknown: 1587; RV32IM: # %bb.0: 1588; RV32IM-NEXT: blt a0, a1, .LBB42_2 1589; RV32IM-NEXT: # %bb.1: 1590; RV32IM-NEXT: li a0, -7 1591; RV32IM-NEXT: ret 1592; RV32IM-NEXT: .LBB42_2: 1593; RV32IM-NEXT: li a0, 5 1594; RV32IM-NEXT: ret 1595; 1596; RV64IM-LABEL: select_cst_unknown: 1597; RV64IM: # %bb.0: 1598; RV64IM-NEXT: blt a0, a1, .LBB42_2 1599; RV64IM-NEXT: # %bb.1: 1600; RV64IM-NEXT: li a0, -7 1601; RV64IM-NEXT: ret 1602; RV64IM-NEXT: .LBB42_2: 1603; RV64IM-NEXT: li a0, 5 1604; RV64IM-NEXT: ret 1605; 1606; RV64IMXVTCONDOPS-LABEL: select_cst_unknown: 1607; RV64IMXVTCONDOPS: # %bb.0: 1608; RV64IMXVTCONDOPS-NEXT: slt a0, a0, a1 1609; RV64IMXVTCONDOPS-NEXT: li a1, -12 1610; RV64IMXVTCONDOPS-NEXT: vt.maskcn a0, a1, a0 1611; RV64IMXVTCONDOPS-NEXT: addi a0, a0, 5 1612; RV64IMXVTCONDOPS-NEXT: ret 1613; 1614; CHECKZICOND-LABEL: select_cst_unknown: 1615; CHECKZICOND: # %bb.0: 1616; CHECKZICOND-NEXT: slt a0, a0, a1 1617; CHECKZICOND-NEXT: li a1, -12 1618; CHECKZICOND-NEXT: czero.nez a0, a1, a0 1619; CHECKZICOND-NEXT: addi a0, a0, 5 1620; CHECKZICOND-NEXT: ret 1621 %cond = icmp slt i32 %a, %b 1622 %ret = select i1 %cond, i32 5, i32 -7 1623 ret i32 %ret 1624} 1625 1626define i32 @select_cst1(i1 zeroext %cond) { 1627; RV32IM-LABEL: select_cst1: 1628; RV32IM: # %bb.0: 1629; RV32IM-NEXT: bnez a0, .LBB43_2 1630; RV32IM-NEXT: # %bb.1: 1631; RV32IM-NEXT: li a0, 20 1632; RV32IM-NEXT: ret 1633; RV32IM-NEXT: .LBB43_2: 1634; RV32IM-NEXT: li a0, 10 1635; RV32IM-NEXT: ret 1636; 1637; RV64IM-LABEL: select_cst1: 1638; RV64IM: # %bb.0: 1639; RV64IM-NEXT: bnez a0, .LBB43_2 1640; RV64IM-NEXT: # %bb.1: 1641; RV64IM-NEXT: li a0, 20 1642; RV64IM-NEXT: ret 1643; RV64IM-NEXT: .LBB43_2: 1644; RV64IM-NEXT: li a0, 10 1645; RV64IM-NEXT: ret 1646; 1647; RV64IMXVTCONDOPS-LABEL: select_cst1: 1648; RV64IMXVTCONDOPS: # %bb.0: 1649; RV64IMXVTCONDOPS-NEXT: li a1, 10 1650; RV64IMXVTCONDOPS-NEXT: vt.maskcn a0, a1, a0 1651; RV64IMXVTCONDOPS-NEXT: addi a0, a0, 10 1652; RV64IMXVTCONDOPS-NEXT: ret 1653; 1654; CHECKZICOND-LABEL: select_cst1: 1655; CHECKZICOND: # %bb.0: 1656; CHECKZICOND-NEXT: li a1, 10 1657; CHECKZICOND-NEXT: czero.nez a0, a1, a0 1658; CHECKZICOND-NEXT: addi a0, a0, 10 1659; CHECKZICOND-NEXT: ret 1660 %ret = select i1 %cond, i32 10, i32 20 1661 ret i32 %ret 1662} 1663 1664define i32 @select_cst2(i1 zeroext %cond) { 1665; RV32IM-LABEL: select_cst2: 1666; RV32IM: # %bb.0: 1667; RV32IM-NEXT: bnez a0, .LBB44_2 1668; RV32IM-NEXT: # %bb.1: 1669; RV32IM-NEXT: lui a0, 5 1670; RV32IM-NEXT: addi a0, a0, -480 1671; RV32IM-NEXT: ret 1672; RV32IM-NEXT: .LBB44_2: 1673; RV32IM-NEXT: li a0, 10 1674; RV32IM-NEXT: ret 1675; 1676; RV64IM-LABEL: select_cst2: 1677; RV64IM: # %bb.0: 1678; RV64IM-NEXT: bnez a0, .LBB44_2 1679; RV64IM-NEXT: # %bb.1: 1680; RV64IM-NEXT: lui a0, 5 1681; RV64IM-NEXT: addiw a0, a0, -480 1682; RV64IM-NEXT: ret 1683; RV64IM-NEXT: .LBB44_2: 1684; RV64IM-NEXT: li a0, 10 1685; RV64IM-NEXT: ret 1686; 1687; RV64IMXVTCONDOPS-LABEL: select_cst2: 1688; RV64IMXVTCONDOPS: # %bb.0: 1689; RV64IMXVTCONDOPS-NEXT: lui a1, 5 1690; RV64IMXVTCONDOPS-NEXT: addiw a1, a1, -490 1691; RV64IMXVTCONDOPS-NEXT: vt.maskcn a0, a1, a0 1692; RV64IMXVTCONDOPS-NEXT: addi a0, a0, 10 1693; RV64IMXVTCONDOPS-NEXT: ret 1694; 1695; RV32IMZICOND-LABEL: select_cst2: 1696; RV32IMZICOND: # %bb.0: 1697; RV32IMZICOND-NEXT: lui a1, 5 1698; RV32IMZICOND-NEXT: addi a1, a1, -490 1699; RV32IMZICOND-NEXT: czero.nez a0, a1, a0 1700; RV32IMZICOND-NEXT: addi a0, a0, 10 1701; RV32IMZICOND-NEXT: ret 1702; 1703; RV64IMZICOND-LABEL: select_cst2: 1704; RV64IMZICOND: # %bb.0: 1705; RV64IMZICOND-NEXT: lui a1, 5 1706; RV64IMZICOND-NEXT: addiw a1, a1, -490 1707; RV64IMZICOND-NEXT: czero.nez a0, a1, a0 1708; RV64IMZICOND-NEXT: addi a0, a0, 10 1709; RV64IMZICOND-NEXT: ret 1710 %ret = select i1 %cond, i32 10, i32 20000 1711 ret i32 %ret 1712} 1713 1714define i32 @select_cst3(i1 zeroext %cond) { 1715; RV32IM-LABEL: select_cst3: 1716; RV32IM: # %bb.0: 1717; RV32IM-NEXT: bnez a0, .LBB45_2 1718; RV32IM-NEXT: # %bb.1: 1719; RV32IM-NEXT: lui a0, 5 1720; RV32IM-NEXT: addi a0, a0, -480 1721; RV32IM-NEXT: ret 1722; RV32IM-NEXT: .LBB45_2: 1723; RV32IM-NEXT: lui a0, 7 1724; RV32IM-NEXT: addi a0, a0, 1328 1725; RV32IM-NEXT: ret 1726; 1727; RV64IM-LABEL: select_cst3: 1728; RV64IM: # %bb.0: 1729; RV64IM-NEXT: bnez a0, .LBB45_2 1730; RV64IM-NEXT: # %bb.1: 1731; RV64IM-NEXT: lui a0, 5 1732; RV64IM-NEXT: addiw a0, a0, -480 1733; RV64IM-NEXT: ret 1734; RV64IM-NEXT: .LBB45_2: 1735; RV64IM-NEXT: lui a0, 7 1736; RV64IM-NEXT: addiw a0, a0, 1328 1737; RV64IM-NEXT: ret 1738; 1739; RV64IMXVTCONDOPS-LABEL: select_cst3: 1740; RV64IMXVTCONDOPS: # %bb.0: 1741; RV64IMXVTCONDOPS-NEXT: lui a1, 1048574 1742; RV64IMXVTCONDOPS-NEXT: addiw a1, a1, -1808 1743; RV64IMXVTCONDOPS-NEXT: vt.maskcn a0, a1, a0 1744; RV64IMXVTCONDOPS-NEXT: lui a1, 7 1745; RV64IMXVTCONDOPS-NEXT: addiw a1, a1, 1328 1746; RV64IMXVTCONDOPS-NEXT: add a0, a0, a1 1747; RV64IMXVTCONDOPS-NEXT: ret 1748; 1749; RV32IMZICOND-LABEL: select_cst3: 1750; RV32IMZICOND: # %bb.0: 1751; RV32IMZICOND-NEXT: lui a1, 1048574 1752; RV32IMZICOND-NEXT: addi a1, a1, -1808 1753; RV32IMZICOND-NEXT: czero.nez a0, a1, a0 1754; RV32IMZICOND-NEXT: lui a1, 7 1755; RV32IMZICOND-NEXT: addi a1, a1, 1328 1756; RV32IMZICOND-NEXT: add a0, a0, a1 1757; RV32IMZICOND-NEXT: ret 1758; 1759; RV64IMZICOND-LABEL: select_cst3: 1760; RV64IMZICOND: # %bb.0: 1761; RV64IMZICOND-NEXT: lui a1, 1048574 1762; RV64IMZICOND-NEXT: addiw a1, a1, -1808 1763; RV64IMZICOND-NEXT: czero.nez a0, a1, a0 1764; RV64IMZICOND-NEXT: lui a1, 7 1765; RV64IMZICOND-NEXT: addiw a1, a1, 1328 1766; RV64IMZICOND-NEXT: add a0, a0, a1 1767; RV64IMZICOND-NEXT: ret 1768 %ret = select i1 %cond, i32 30000, i32 20000 1769 ret i32 %ret 1770} 1771 1772define i32 @select_cst4(i1 zeroext %cond) { 1773; CHECK-LABEL: select_cst4: 1774; CHECK: # %bb.0: 1775; CHECK-NEXT: neg a0, a0 1776; CHECK-NEXT: xori a0, a0, 2047 1777; CHECK-NEXT: ret 1778 %ret = select i1 %cond, i32 -2048, i32 2047 1779 ret i32 %ret 1780} 1781 1782define i32 @select_cst5(i1 zeroext %cond) { 1783; RV32IM-LABEL: select_cst5: 1784; RV32IM: # %bb.0: 1785; RV32IM-NEXT: bnez a0, .LBB47_2 1786; RV32IM-NEXT: # %bb.1: 1787; RV32IM-NEXT: lui a0, 1 1788; RV32IM-NEXT: addi a0, a0, -2047 1789; RV32IM-NEXT: ret 1790; RV32IM-NEXT: .LBB47_2: 1791; RV32IM-NEXT: li a0, 2047 1792; RV32IM-NEXT: ret 1793; 1794; RV64IM-LABEL: select_cst5: 1795; RV64IM: # %bb.0: 1796; RV64IM-NEXT: bnez a0, .LBB47_2 1797; RV64IM-NEXT: # %bb.1: 1798; RV64IM-NEXT: lui a0, 1 1799; RV64IM-NEXT: addiw a0, a0, -2047 1800; RV64IM-NEXT: ret 1801; RV64IM-NEXT: .LBB47_2: 1802; RV64IM-NEXT: li a0, 2047 1803; RV64IM-NEXT: ret 1804; 1805; RV64IMXVTCONDOPS-LABEL: select_cst5: 1806; RV64IMXVTCONDOPS: # %bb.0: 1807; RV64IMXVTCONDOPS-NEXT: li a1, 2 1808; RV64IMXVTCONDOPS-NEXT: vt.maskcn a0, a1, a0 1809; RV64IMXVTCONDOPS-NEXT: addi a0, a0, 2047 1810; RV64IMXVTCONDOPS-NEXT: ret 1811; 1812; CHECKZICOND-LABEL: select_cst5: 1813; CHECKZICOND: # %bb.0: 1814; CHECKZICOND-NEXT: li a1, 2 1815; CHECKZICOND-NEXT: czero.nez a0, a1, a0 1816; CHECKZICOND-NEXT: addi a0, a0, 2047 1817; CHECKZICOND-NEXT: ret 1818 %ret = select i1 %cond, i32 2047, i32 2049 1819 ret i32 %ret 1820} 1821 1822define i32 @select_cst5_invert(i1 zeroext %cond) { 1823; RV32IM-LABEL: select_cst5_invert: 1824; RV32IM: # %bb.0: 1825; RV32IM-NEXT: bnez a0, .LBB48_2 1826; RV32IM-NEXT: # %bb.1: 1827; RV32IM-NEXT: li a0, 2047 1828; RV32IM-NEXT: ret 1829; RV32IM-NEXT: .LBB48_2: 1830; RV32IM-NEXT: lui a0, 1 1831; RV32IM-NEXT: addi a0, a0, -2047 1832; RV32IM-NEXT: ret 1833; 1834; RV64IM-LABEL: select_cst5_invert: 1835; RV64IM: # %bb.0: 1836; RV64IM-NEXT: bnez a0, .LBB48_2 1837; RV64IM-NEXT: # %bb.1: 1838; RV64IM-NEXT: li a0, 2047 1839; RV64IM-NEXT: ret 1840; RV64IM-NEXT: .LBB48_2: 1841; RV64IM-NEXT: lui a0, 1 1842; RV64IM-NEXT: addiw a0, a0, -2047 1843; RV64IM-NEXT: ret 1844; 1845; RV64IMXVTCONDOPS-LABEL: select_cst5_invert: 1846; RV64IMXVTCONDOPS: # %bb.0: 1847; RV64IMXVTCONDOPS-NEXT: li a1, 2 1848; RV64IMXVTCONDOPS-NEXT: vt.maskc a0, a1, a0 1849; RV64IMXVTCONDOPS-NEXT: addi a0, a0, 2047 1850; RV64IMXVTCONDOPS-NEXT: ret 1851; 1852; CHECKZICOND-LABEL: select_cst5_invert: 1853; CHECKZICOND: # %bb.0: 1854; CHECKZICOND-NEXT: li a1, 2 1855; CHECKZICOND-NEXT: czero.eqz a0, a1, a0 1856; CHECKZICOND-NEXT: addi a0, a0, 2047 1857; CHECKZICOND-NEXT: ret 1858 %ret = select i1 %cond, i32 2049, i32 2047 1859 ret i32 %ret 1860} 1861 1862define i32 @select_cst_diff2(i1 zeroext %cond) { 1863; RV32IM-LABEL: select_cst_diff2: 1864; RV32IM: # %bb.0: 1865; RV32IM-NEXT: bnez a0, .LBB49_2 1866; RV32IM-NEXT: # %bb.1: 1867; RV32IM-NEXT: li a0, 122 1868; RV32IM-NEXT: ret 1869; RV32IM-NEXT: .LBB49_2: 1870; RV32IM-NEXT: li a0, 120 1871; RV32IM-NEXT: ret 1872; 1873; RV64IM-LABEL: select_cst_diff2: 1874; RV64IM: # %bb.0: 1875; RV64IM-NEXT: bnez a0, .LBB49_2 1876; RV64IM-NEXT: # %bb.1: 1877; RV64IM-NEXT: li a0, 122 1878; RV64IM-NEXT: ret 1879; RV64IM-NEXT: .LBB49_2: 1880; RV64IM-NEXT: li a0, 120 1881; RV64IM-NEXT: ret 1882; 1883; RV64IMXVTCONDOPS-LABEL: select_cst_diff2: 1884; RV64IMXVTCONDOPS: # %bb.0: 1885; RV64IMXVTCONDOPS-NEXT: li a1, 2 1886; RV64IMXVTCONDOPS-NEXT: vt.maskcn a0, a1, a0 1887; RV64IMXVTCONDOPS-NEXT: addi a0, a0, 120 1888; RV64IMXVTCONDOPS-NEXT: ret 1889; 1890; CHECKZICOND-LABEL: select_cst_diff2: 1891; CHECKZICOND: # %bb.0: 1892; CHECKZICOND-NEXT: li a1, 2 1893; CHECKZICOND-NEXT: czero.nez a0, a1, a0 1894; CHECKZICOND-NEXT: addi a0, a0, 120 1895; CHECKZICOND-NEXT: ret 1896 %ret = select i1 %cond, i32 120, i32 122 1897 ret i32 %ret 1898} 1899 1900define i32 @select_cst_diff2_invert(i1 zeroext %cond) { 1901; RV32IM-LABEL: select_cst_diff2_invert: 1902; RV32IM: # %bb.0: 1903; RV32IM-NEXT: bnez a0, .LBB50_2 1904; RV32IM-NEXT: # %bb.1: 1905; RV32IM-NEXT: li a0, 120 1906; RV32IM-NEXT: ret 1907; RV32IM-NEXT: .LBB50_2: 1908; RV32IM-NEXT: li a0, 122 1909; RV32IM-NEXT: ret 1910; 1911; RV64IM-LABEL: select_cst_diff2_invert: 1912; RV64IM: # %bb.0: 1913; RV64IM-NEXT: bnez a0, .LBB50_2 1914; RV64IM-NEXT: # %bb.1: 1915; RV64IM-NEXT: li a0, 120 1916; RV64IM-NEXT: ret 1917; RV64IM-NEXT: .LBB50_2: 1918; RV64IM-NEXT: li a0, 122 1919; RV64IM-NEXT: ret 1920; 1921; RV64IMXVTCONDOPS-LABEL: select_cst_diff2_invert: 1922; RV64IMXVTCONDOPS: # %bb.0: 1923; RV64IMXVTCONDOPS-NEXT: li a1, -2 1924; RV64IMXVTCONDOPS-NEXT: vt.maskcn a0, a1, a0 1925; RV64IMXVTCONDOPS-NEXT: addi a0, a0, 122 1926; RV64IMXVTCONDOPS-NEXT: ret 1927; 1928; CHECKZICOND-LABEL: select_cst_diff2_invert: 1929; CHECKZICOND: # %bb.0: 1930; CHECKZICOND-NEXT: li a1, -2 1931; CHECKZICOND-NEXT: czero.nez a0, a1, a0 1932; CHECKZICOND-NEXT: addi a0, a0, 122 1933; CHECKZICOND-NEXT: ret 1934 %ret = select i1 %cond, i32 122, i32 120 1935 ret i32 %ret 1936} 1937 1938define i32 @select_cst_diff4(i1 zeroext %cond) { 1939; RV32IM-LABEL: select_cst_diff4: 1940; RV32IM: # %bb.0: 1941; RV32IM-NEXT: bnez a0, .LBB51_2 1942; RV32IM-NEXT: # %bb.1: 1943; RV32IM-NEXT: li a0, 6 1944; RV32IM-NEXT: ret 1945; RV32IM-NEXT: .LBB51_2: 1946; RV32IM-NEXT: li a0, 10 1947; RV32IM-NEXT: ret 1948; 1949; RV64IM-LABEL: select_cst_diff4: 1950; RV64IM: # %bb.0: 1951; RV64IM-NEXT: bnez a0, .LBB51_2 1952; RV64IM-NEXT: # %bb.1: 1953; RV64IM-NEXT: li a0, 6 1954; RV64IM-NEXT: ret 1955; RV64IM-NEXT: .LBB51_2: 1956; RV64IM-NEXT: li a0, 10 1957; RV64IM-NEXT: ret 1958; 1959; RV64IMXVTCONDOPS-LABEL: select_cst_diff4: 1960; RV64IMXVTCONDOPS: # %bb.0: 1961; RV64IMXVTCONDOPS-NEXT: li a1, -4 1962; RV64IMXVTCONDOPS-NEXT: vt.maskcn a0, a1, a0 1963; RV64IMXVTCONDOPS-NEXT: addi a0, a0, 10 1964; RV64IMXVTCONDOPS-NEXT: ret 1965; 1966; CHECKZICOND-LABEL: select_cst_diff4: 1967; CHECKZICOND: # %bb.0: 1968; CHECKZICOND-NEXT: li a1, -4 1969; CHECKZICOND-NEXT: czero.nez a0, a1, a0 1970; CHECKZICOND-NEXT: addi a0, a0, 10 1971; CHECKZICOND-NEXT: ret 1972 %ret = select i1 %cond, i32 10, i32 6 1973 ret i32 %ret 1974} 1975 1976define i32 @select_cst_diff4_invert(i1 zeroext %cond) { 1977; RV32IM-LABEL: select_cst_diff4_invert: 1978; RV32IM: # %bb.0: 1979; RV32IM-NEXT: bnez a0, .LBB52_2 1980; RV32IM-NEXT: # %bb.1: 1981; RV32IM-NEXT: li a0, 10 1982; RV32IM-NEXT: ret 1983; RV32IM-NEXT: .LBB52_2: 1984; RV32IM-NEXT: li a0, 6 1985; RV32IM-NEXT: ret 1986; 1987; RV64IM-LABEL: select_cst_diff4_invert: 1988; RV64IM: # %bb.0: 1989; RV64IM-NEXT: bnez a0, .LBB52_2 1990; RV64IM-NEXT: # %bb.1: 1991; RV64IM-NEXT: li a0, 10 1992; RV64IM-NEXT: ret 1993; RV64IM-NEXT: .LBB52_2: 1994; RV64IM-NEXT: li a0, 6 1995; RV64IM-NEXT: ret 1996; 1997; RV64IMXVTCONDOPS-LABEL: select_cst_diff4_invert: 1998; RV64IMXVTCONDOPS: # %bb.0: 1999; RV64IMXVTCONDOPS-NEXT: li a1, 4 2000; RV64IMXVTCONDOPS-NEXT: vt.maskcn a0, a1, a0 2001; RV64IMXVTCONDOPS-NEXT: addi a0, a0, 6 2002; RV64IMXVTCONDOPS-NEXT: ret 2003; 2004; CHECKZICOND-LABEL: select_cst_diff4_invert: 2005; CHECKZICOND: # %bb.0: 2006; CHECKZICOND-NEXT: li a1, 4 2007; CHECKZICOND-NEXT: czero.nez a0, a1, a0 2008; CHECKZICOND-NEXT: addi a0, a0, 6 2009; CHECKZICOND-NEXT: ret 2010 %ret = select i1 %cond, i32 6, i32 10 2011 ret i32 %ret 2012} 2013 2014define i32 @select_cst_diff8(i1 zeroext %cond) { 2015; RV32IM-LABEL: select_cst_diff8: 2016; RV32IM: # %bb.0: 2017; RV32IM-NEXT: bnez a0, .LBB53_2 2018; RV32IM-NEXT: # %bb.1: 2019; RV32IM-NEXT: li a0, 6 2020; RV32IM-NEXT: ret 2021; RV32IM-NEXT: .LBB53_2: 2022; RV32IM-NEXT: li a0, 14 2023; RV32IM-NEXT: ret 2024; 2025; RV64IM-LABEL: select_cst_diff8: 2026; RV64IM: # %bb.0: 2027; RV64IM-NEXT: bnez a0, .LBB53_2 2028; RV64IM-NEXT: # %bb.1: 2029; RV64IM-NEXT: li a0, 6 2030; RV64IM-NEXT: ret 2031; RV64IM-NEXT: .LBB53_2: 2032; RV64IM-NEXT: li a0, 14 2033; RV64IM-NEXT: ret 2034; 2035; RV64IMXVTCONDOPS-LABEL: select_cst_diff8: 2036; RV64IMXVTCONDOPS: # %bb.0: 2037; RV64IMXVTCONDOPS-NEXT: li a1, -8 2038; RV64IMXVTCONDOPS-NEXT: vt.maskcn a0, a1, a0 2039; RV64IMXVTCONDOPS-NEXT: addi a0, a0, 14 2040; RV64IMXVTCONDOPS-NEXT: ret 2041; 2042; CHECKZICOND-LABEL: select_cst_diff8: 2043; CHECKZICOND: # %bb.0: 2044; CHECKZICOND-NEXT: li a1, -8 2045; CHECKZICOND-NEXT: czero.nez a0, a1, a0 2046; CHECKZICOND-NEXT: addi a0, a0, 14 2047; CHECKZICOND-NEXT: ret 2048 %ret = select i1 %cond, i32 14, i32 6 2049 ret i32 %ret 2050} 2051 2052define i32 @select_cst_diff8_invert(i1 zeroext %cond) { 2053; RV32IM-LABEL: select_cst_diff8_invert: 2054; RV32IM: # %bb.0: 2055; RV32IM-NEXT: bnez a0, .LBB54_2 2056; RV32IM-NEXT: # %bb.1: 2057; RV32IM-NEXT: li a0, 14 2058; RV32IM-NEXT: ret 2059; RV32IM-NEXT: .LBB54_2: 2060; RV32IM-NEXT: li a0, 6 2061; RV32IM-NEXT: ret 2062; 2063; RV64IM-LABEL: select_cst_diff8_invert: 2064; RV64IM: # %bb.0: 2065; RV64IM-NEXT: bnez a0, .LBB54_2 2066; RV64IM-NEXT: # %bb.1: 2067; RV64IM-NEXT: li a0, 14 2068; RV64IM-NEXT: ret 2069; RV64IM-NEXT: .LBB54_2: 2070; RV64IM-NEXT: li a0, 6 2071; RV64IM-NEXT: ret 2072; 2073; RV64IMXVTCONDOPS-LABEL: select_cst_diff8_invert: 2074; RV64IMXVTCONDOPS: # %bb.0: 2075; RV64IMXVTCONDOPS-NEXT: li a1, 8 2076; RV64IMXVTCONDOPS-NEXT: vt.maskcn a0, a1, a0 2077; RV64IMXVTCONDOPS-NEXT: addi a0, a0, 6 2078; RV64IMXVTCONDOPS-NEXT: ret 2079; 2080; CHECKZICOND-LABEL: select_cst_diff8_invert: 2081; CHECKZICOND: # %bb.0: 2082; CHECKZICOND-NEXT: li a1, 8 2083; CHECKZICOND-NEXT: czero.nez a0, a1, a0 2084; CHECKZICOND-NEXT: addi a0, a0, 6 2085; CHECKZICOND-NEXT: ret 2086 %ret = select i1 %cond, i32 6, i32 14 2087 ret i32 %ret 2088} 2089 2090 2091define i32 @select_cst_diff1024(i1 zeroext %cond) { 2092; RV32IM-LABEL: select_cst_diff1024: 2093; RV32IM: # %bb.0: 2094; RV32IM-NEXT: bnez a0, .LBB55_2 2095; RV32IM-NEXT: # %bb.1: 2096; RV32IM-NEXT: li a0, 6 2097; RV32IM-NEXT: ret 2098; RV32IM-NEXT: .LBB55_2: 2099; RV32IM-NEXT: li a0, 1030 2100; RV32IM-NEXT: ret 2101; 2102; RV64IM-LABEL: select_cst_diff1024: 2103; RV64IM: # %bb.0: 2104; RV64IM-NEXT: bnez a0, .LBB55_2 2105; RV64IM-NEXT: # %bb.1: 2106; RV64IM-NEXT: li a0, 6 2107; RV64IM-NEXT: ret 2108; RV64IM-NEXT: .LBB55_2: 2109; RV64IM-NEXT: li a0, 1030 2110; RV64IM-NEXT: ret 2111; 2112; RV64IMXVTCONDOPS-LABEL: select_cst_diff1024: 2113; RV64IMXVTCONDOPS: # %bb.0: 2114; RV64IMXVTCONDOPS-NEXT: li a1, -1024 2115; RV64IMXVTCONDOPS-NEXT: vt.maskcn a0, a1, a0 2116; RV64IMXVTCONDOPS-NEXT: addi a0, a0, 1030 2117; RV64IMXVTCONDOPS-NEXT: ret 2118; 2119; CHECKZICOND-LABEL: select_cst_diff1024: 2120; CHECKZICOND: # %bb.0: 2121; CHECKZICOND-NEXT: li a1, -1024 2122; CHECKZICOND-NEXT: czero.nez a0, a1, a0 2123; CHECKZICOND-NEXT: addi a0, a0, 1030 2124; CHECKZICOND-NEXT: ret 2125 %ret = select i1 %cond, i32 1030, i32 6 2126 ret i32 %ret 2127} 2128 2129define i32 @select_cst_diff1024_invert(i1 zeroext %cond) { 2130; RV32IM-LABEL: select_cst_diff1024_invert: 2131; RV32IM: # %bb.0: 2132; RV32IM-NEXT: bnez a0, .LBB56_2 2133; RV32IM-NEXT: # %bb.1: 2134; RV32IM-NEXT: li a0, 1030 2135; RV32IM-NEXT: ret 2136; RV32IM-NEXT: .LBB56_2: 2137; RV32IM-NEXT: li a0, 6 2138; RV32IM-NEXT: ret 2139; 2140; RV64IM-LABEL: select_cst_diff1024_invert: 2141; RV64IM: # %bb.0: 2142; RV64IM-NEXT: bnez a0, .LBB56_2 2143; RV64IM-NEXT: # %bb.1: 2144; RV64IM-NEXT: li a0, 1030 2145; RV64IM-NEXT: ret 2146; RV64IM-NEXT: .LBB56_2: 2147; RV64IM-NEXT: li a0, 6 2148; RV64IM-NEXT: ret 2149; 2150; RV64IMXVTCONDOPS-LABEL: select_cst_diff1024_invert: 2151; RV64IMXVTCONDOPS: # %bb.0: 2152; RV64IMXVTCONDOPS-NEXT: li a1, 1024 2153; RV64IMXVTCONDOPS-NEXT: vt.maskcn a0, a1, a0 2154; RV64IMXVTCONDOPS-NEXT: addi a0, a0, 6 2155; RV64IMXVTCONDOPS-NEXT: ret 2156; 2157; CHECKZICOND-LABEL: select_cst_diff1024_invert: 2158; CHECKZICOND: # %bb.0: 2159; CHECKZICOND-NEXT: li a1, 1024 2160; CHECKZICOND-NEXT: czero.nez a0, a1, a0 2161; CHECKZICOND-NEXT: addi a0, a0, 6 2162; CHECKZICOND-NEXT: ret 2163 %ret = select i1 %cond, i32 6, i32 1030 2164 ret i32 %ret 2165} 2166 2167 2168@select_redundant_czero_eqz_data = global i32 0, align 4 2169 2170define void @select_redundant_czero_eqz1(ptr %0, ptr %1) { 2171; RV32IM-LABEL: select_redundant_czero_eqz1: 2172; RV32IM: # %bb.0: # %entry 2173; RV32IM-NEXT: bnez a0, .LBB57_2 2174; RV32IM-NEXT: # %bb.1: 2175; RV32IM-NEXT: lui a0, %hi(select_redundant_czero_eqz_data) 2176; RV32IM-NEXT: addi a0, a0, %lo(select_redundant_czero_eqz_data) 2177; RV32IM-NEXT: .LBB57_2: # %entry 2178; RV32IM-NEXT: sw a0, 0(a1) 2179; RV32IM-NEXT: ret 2180; 2181; RV64IM-LABEL: select_redundant_czero_eqz1: 2182; RV64IM: # %bb.0: # %entry 2183; RV64IM-NEXT: bnez a0, .LBB57_2 2184; RV64IM-NEXT: # %bb.1: 2185; RV64IM-NEXT: lui a0, %hi(select_redundant_czero_eqz_data) 2186; RV64IM-NEXT: addi a0, a0, %lo(select_redundant_czero_eqz_data) 2187; RV64IM-NEXT: .LBB57_2: # %entry 2188; RV64IM-NEXT: sd a0, 0(a1) 2189; RV64IM-NEXT: ret 2190; 2191; RV64IMXVTCONDOPS-LABEL: select_redundant_czero_eqz1: 2192; RV64IMXVTCONDOPS: # %bb.0: # %entry 2193; RV64IMXVTCONDOPS-NEXT: lui a2, %hi(select_redundant_czero_eqz_data) 2194; RV64IMXVTCONDOPS-NEXT: addi a2, a2, %lo(select_redundant_czero_eqz_data) 2195; RV64IMXVTCONDOPS-NEXT: vt.maskcn a2, a2, a0 2196; RV64IMXVTCONDOPS-NEXT: or a0, a2, a0 2197; RV64IMXVTCONDOPS-NEXT: sd a0, 0(a1) 2198; RV64IMXVTCONDOPS-NEXT: ret 2199; 2200; RV32IMZICOND-LABEL: select_redundant_czero_eqz1: 2201; RV32IMZICOND: # %bb.0: # %entry 2202; RV32IMZICOND-NEXT: lui a2, %hi(select_redundant_czero_eqz_data) 2203; RV32IMZICOND-NEXT: addi a2, a2, %lo(select_redundant_czero_eqz_data) 2204; RV32IMZICOND-NEXT: czero.nez a2, a2, a0 2205; RV32IMZICOND-NEXT: or a0, a2, a0 2206; RV32IMZICOND-NEXT: sw a0, 0(a1) 2207; RV32IMZICOND-NEXT: ret 2208; 2209; RV64IMZICOND-LABEL: select_redundant_czero_eqz1: 2210; RV64IMZICOND: # %bb.0: # %entry 2211; RV64IMZICOND-NEXT: lui a2, %hi(select_redundant_czero_eqz_data) 2212; RV64IMZICOND-NEXT: addi a2, a2, %lo(select_redundant_czero_eqz_data) 2213; RV64IMZICOND-NEXT: czero.nez a2, a2, a0 2214; RV64IMZICOND-NEXT: or a0, a2, a0 2215; RV64IMZICOND-NEXT: sd a0, 0(a1) 2216; RV64IMZICOND-NEXT: ret 2217entry: 2218 %3 = icmp eq ptr %0, null 2219 %4 = select i1 %3, ptr @select_redundant_czero_eqz_data, ptr %0 2220 store ptr %4, ptr %1, align 8 2221 ret void 2222} 2223 2224define void @select_redundant_czero_eqz2(ptr %0, ptr %1) { 2225; RV32IM-LABEL: select_redundant_czero_eqz2: 2226; RV32IM: # %bb.0: # %entry 2227; RV32IM-NEXT: bnez a0, .LBB58_2 2228; RV32IM-NEXT: # %bb.1: # %entry 2229; RV32IM-NEXT: lui a0, %hi(select_redundant_czero_eqz_data) 2230; RV32IM-NEXT: addi a0, a0, %lo(select_redundant_czero_eqz_data) 2231; RV32IM-NEXT: .LBB58_2: # %entry 2232; RV32IM-NEXT: sw a0, 0(a1) 2233; RV32IM-NEXT: ret 2234; 2235; RV64IM-LABEL: select_redundant_czero_eqz2: 2236; RV64IM: # %bb.0: # %entry 2237; RV64IM-NEXT: bnez a0, .LBB58_2 2238; RV64IM-NEXT: # %bb.1: # %entry 2239; RV64IM-NEXT: lui a0, %hi(select_redundant_czero_eqz_data) 2240; RV64IM-NEXT: addi a0, a0, %lo(select_redundant_czero_eqz_data) 2241; RV64IM-NEXT: .LBB58_2: # %entry 2242; RV64IM-NEXT: sd a0, 0(a1) 2243; RV64IM-NEXT: ret 2244; 2245; RV64IMXVTCONDOPS-LABEL: select_redundant_czero_eqz2: 2246; RV64IMXVTCONDOPS: # %bb.0: # %entry 2247; RV64IMXVTCONDOPS-NEXT: lui a2, %hi(select_redundant_czero_eqz_data) 2248; RV64IMXVTCONDOPS-NEXT: addi a2, a2, %lo(select_redundant_czero_eqz_data) 2249; RV64IMXVTCONDOPS-NEXT: vt.maskcn a2, a2, a0 2250; RV64IMXVTCONDOPS-NEXT: or a0, a0, a2 2251; RV64IMXVTCONDOPS-NEXT: sd a0, 0(a1) 2252; RV64IMXVTCONDOPS-NEXT: ret 2253; 2254; RV32IMZICOND-LABEL: select_redundant_czero_eqz2: 2255; RV32IMZICOND: # %bb.0: # %entry 2256; RV32IMZICOND-NEXT: lui a2, %hi(select_redundant_czero_eqz_data) 2257; RV32IMZICOND-NEXT: addi a2, a2, %lo(select_redundant_czero_eqz_data) 2258; RV32IMZICOND-NEXT: czero.nez a2, a2, a0 2259; RV32IMZICOND-NEXT: or a0, a0, a2 2260; RV32IMZICOND-NEXT: sw a0, 0(a1) 2261; RV32IMZICOND-NEXT: ret 2262; 2263; RV64IMZICOND-LABEL: select_redundant_czero_eqz2: 2264; RV64IMZICOND: # %bb.0: # %entry 2265; RV64IMZICOND-NEXT: lui a2, %hi(select_redundant_czero_eqz_data) 2266; RV64IMZICOND-NEXT: addi a2, a2, %lo(select_redundant_czero_eqz_data) 2267; RV64IMZICOND-NEXT: czero.nez a2, a2, a0 2268; RV64IMZICOND-NEXT: or a0, a0, a2 2269; RV64IMZICOND-NEXT: sd a0, 0(a1) 2270; RV64IMZICOND-NEXT: ret 2271entry: 2272 %3 = icmp ne ptr %0, null 2273 %4 = select i1 %3, ptr %0, ptr @select_redundant_czero_eqz_data 2274 store ptr %4, ptr %1, align 8 2275 ret void 2276} 2277