1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ 3; RUN: | FileCheck %s -check-prefix=RV32I 4; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ 5; RUN: | FileCheck %s -check-prefix=RV64I 6 7 8define i32 @from_cmpeq(i32 %xx, i32 %y) { 9; RV32I-LABEL: from_cmpeq: 10; RV32I: # %bb.0: 11; RV32I-NEXT: addi a0, a0, -9 12; RV32I-NEXT: seqz a0, a0 13; RV32I-NEXT: and a0, a0, a1 14; RV32I-NEXT: ret 15; 16; RV64I-LABEL: from_cmpeq: 17; RV64I: # %bb.0: 18; RV64I-NEXT: sext.w a0, a0 19; RV64I-NEXT: addi a0, a0, -9 20; RV64I-NEXT: seqz a0, a0 21; RV64I-NEXT: and a0, a0, a1 22; RV64I-NEXT: ret 23 %x = icmp eq i32 %xx, 9 24 %masked = and i32 %y, 1 25 26 %r = select i1 %x, i32 %masked, i32 0 27 ret i32 %r 28} 29 30define i32 @from_cmpeq_fail_bad_andmask(i32 %xx, i32 %y) { 31; RV32I-LABEL: from_cmpeq_fail_bad_andmask: 32; RV32I: # %bb.0: 33; RV32I-NEXT: addi a0, a0, -9 34; RV32I-NEXT: snez a0, a0 35; RV32I-NEXT: addi a0, a0, -1 36; RV32I-NEXT: and a0, a1, a0 37; RV32I-NEXT: andi a0, a0, 3 38; RV32I-NEXT: ret 39; 40; RV64I-LABEL: from_cmpeq_fail_bad_andmask: 41; RV64I: # %bb.0: 42; RV64I-NEXT: sext.w a0, a0 43; RV64I-NEXT: addi a0, a0, -9 44; RV64I-NEXT: snez a0, a0 45; RV64I-NEXT: addi a0, a0, -1 46; RV64I-NEXT: and a0, a1, a0 47; RV64I-NEXT: andi a0, a0, 3 48; RV64I-NEXT: ret 49 %x = icmp eq i32 %xx, 9 50 %masked = and i32 %y, 3 51 %r = select i1 %x, i32 %masked, i32 0 52 ret i32 %r 53} 54 55define i32 @from_i1(i1 %x, i32 %y) { 56; RV32I-LABEL: from_i1: 57; RV32I: # %bb.0: 58; RV32I-NEXT: and a0, a0, a1 59; RV32I-NEXT: andi a0, a0, 1 60; RV32I-NEXT: ret 61; 62; RV64I-LABEL: from_i1: 63; RV64I: # %bb.0: 64; RV64I-NEXT: and a0, a0, a1 65; RV64I-NEXT: andi a0, a0, 1 66; RV64I-NEXT: ret 67 %masked = and i32 %y, 1 68 %r = select i1 %x, i32 %masked, i32 0 69 ret i32 %r 70} 71 72define i32 @from_trunc_i8(i8 %xx, i32 %y) { 73; RV32I-LABEL: from_trunc_i8: 74; RV32I: # %bb.0: 75; RV32I-NEXT: and a0, a0, a1 76; RV32I-NEXT: andi a0, a0, 1 77; RV32I-NEXT: ret 78; 79; RV64I-LABEL: from_trunc_i8: 80; RV64I: # %bb.0: 81; RV64I-NEXT: and a0, a0, a1 82; RV64I-NEXT: andi a0, a0, 1 83; RV64I-NEXT: ret 84 %masked = and i32 %y, 1 85 %x = trunc i8 %xx to i1 86 %r = select i1 %x, i32 %masked, i32 0 87 ret i32 %r 88} 89 90define i32 @from_trunc_i64(i64 %xx, i32 %y) { 91; RV32I-LABEL: from_trunc_i64: 92; RV32I: # %bb.0: 93; RV32I-NEXT: and a0, a0, a2 94; RV32I-NEXT: andi a0, a0, 1 95; RV32I-NEXT: ret 96; 97; RV64I-LABEL: from_trunc_i64: 98; RV64I: # %bb.0: 99; RV64I-NEXT: and a0, a0, a1 100; RV64I-NEXT: andi a0, a0, 1 101; RV64I-NEXT: ret 102 %masked = and i32 %y, 1 103 %x = trunc i64 %xx to i1 104 %r = select i1 %x, i32 %masked, i32 0 105 ret i32 %r 106} 107 108define i32 @from_i1_fail_bad_select0(i1 %x, i32 %y) { 109; RV32I-LABEL: from_i1_fail_bad_select0: 110; RV32I: # %bb.0: 111; RV32I-NEXT: andi a0, a0, 1 112; RV32I-NEXT: bnez a0, .LBB5_2 113; RV32I-NEXT: # %bb.1: 114; RV32I-NEXT: li a0, 1 115; RV32I-NEXT: ret 116; RV32I-NEXT: .LBB5_2: 117; RV32I-NEXT: andi a0, a1, 1 118; RV32I-NEXT: ret 119; 120; RV64I-LABEL: from_i1_fail_bad_select0: 121; RV64I: # %bb.0: 122; RV64I-NEXT: andi a0, a0, 1 123; RV64I-NEXT: bnez a0, .LBB5_2 124; RV64I-NEXT: # %bb.1: 125; RV64I-NEXT: li a0, 1 126; RV64I-NEXT: ret 127; RV64I-NEXT: .LBB5_2: 128; RV64I-NEXT: andi a0, a1, 1 129; RV64I-NEXT: ret 130 %masked = and i32 %y, 1 131 %r = select i1 %x, i32 %masked, i32 1 132 ret i32 %r 133} 134 135define i32 @from_i1_fail_bad_select1(i1 %x, i32 %y) { 136; RV32I-LABEL: from_i1_fail_bad_select1: 137; RV32I: # %bb.0: 138; RV32I-NEXT: addi a0, a0, -1 139; RV32I-NEXT: and a0, a1, a0 140; RV32I-NEXT: andi a0, a0, 1 141; RV32I-NEXT: ret 142; 143; RV64I-LABEL: from_i1_fail_bad_select1: 144; RV64I: # %bb.0: 145; RV64I-NEXT: addi a0, a0, -1 146; RV64I-NEXT: and a0, a1, a0 147; RV64I-NEXT: andi a0, a0, 1 148; RV64I-NEXT: ret 149 %masked = and i32 %y, 1 150 %r = select i1 %x, i32 0, i32 %masked 151 ret i32 %r 152} 153