1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=riscv32 %s -o - | FileCheck %s --check-prefix=RV32 3; RUN: llc -mtriple=riscv64 %s -o - | FileCheck %s --check-prefix=RV64 4 5define i32 @xori64i32(i64 %a) { 6; RV32-LABEL: xori64i32: 7; RV32: # %bb.0: 8; RV32-NEXT: srai a1, a1, 31 9; RV32-NEXT: lui a0, 524288 10; RV32-NEXT: addi a0, a0, -1 11; RV32-NEXT: xor a0, a1, a0 12; RV32-NEXT: ret 13; 14; RV64-LABEL: xori64i32: 15; RV64: # %bb.0: 16; RV64-NEXT: srai a0, a0, 63 17; RV64-NEXT: lui a1, 524288 18; RV64-NEXT: addiw a1, a1, -1 19; RV64-NEXT: xor a0, a0, a1 20; RV64-NEXT: ret 21 %shr4 = ashr i64 %a, 63 22 %conv5 = trunc i64 %shr4 to i32 23 %xor = xor i32 %conv5, 2147483647 24 ret i32 %xor 25} 26 27define i64 @selecti64i64(i64 %a) { 28; RV32-LABEL: selecti64i64: 29; RV32: # %bb.0: 30; RV32-NEXT: srai a1, a1, 31 31; RV32-NEXT: lui a0, 524288 32; RV32-NEXT: addi a0, a0, -1 33; RV32-NEXT: xor a0, a1, a0 34; RV32-NEXT: ret 35; 36; RV64-LABEL: selecti64i64: 37; RV64: # %bb.0: 38; RV64-NEXT: srai a0, a0, 63 39; RV64-NEXT: lui a1, 524288 40; RV64-NEXT: addiw a1, a1, -1 41; RV64-NEXT: xor a0, a0, a1 42; RV64-NEXT: ret 43 %c = icmp sgt i64 %a, -1 44 %s = select i1 %c, i64 2147483647, i64 -2147483648 45 ret i64 %s 46} 47 48define i32 @selecti64i32(i64 %a) { 49; RV32-LABEL: selecti64i32: 50; RV32: # %bb.0: 51; RV32-NEXT: slti a0, a1, 0 52; RV32-NEXT: xori a0, a0, 1 53; RV32-NEXT: lui a1, 524288 54; RV32-NEXT: sub a0, a1, a0 55; RV32-NEXT: ret 56; 57; RV64-LABEL: selecti64i32: 58; RV64: # %bb.0: 59; RV64-NEXT: srai a0, a0, 63 60; RV64-NEXT: lui a1, 524288 61; RV64-NEXT: addiw a1, a1, -1 62; RV64-NEXT: xor a0, a0, a1 63; RV64-NEXT: ret 64 %c = icmp sgt i64 %a, -1 65 %s = select i1 %c, i32 2147483647, i32 -2147483648 66 ret i32 %s 67} 68 69define i64 @selecti32i64(i32 %a) { 70; RV32-LABEL: selecti32i64: 71; RV32: # %bb.0: 72; RV32-NEXT: srai a1, a0, 31 73; RV32-NEXT: lui a0, 524288 74; RV32-NEXT: addi a0, a0, -1 75; RV32-NEXT: xor a0, a1, a0 76; RV32-NEXT: ret 77; 78; RV64-LABEL: selecti32i64: 79; RV64: # %bb.0: 80; RV64-NEXT: sraiw a0, a0, 31 81; RV64-NEXT: lui a1, 524288 82; RV64-NEXT: addiw a1, a1, -1 83; RV64-NEXT: xor a0, a0, a1 84; RV64-NEXT: ret 85 %c = icmp sgt i32 %a, -1 86 %s = select i1 %c, i64 2147483647, i64 -2147483648 87 ret i64 %s 88} 89 90 91 92define i8 @xori32i8(i32 %a) { 93; RV32-LABEL: xori32i8: 94; RV32: # %bb.0: 95; RV32-NEXT: srai a0, a0, 31 96; RV32-NEXT: xori a0, a0, 84 97; RV32-NEXT: ret 98; 99; RV64-LABEL: xori32i8: 100; RV64: # %bb.0: 101; RV64-NEXT: sraiw a0, a0, 31 102; RV64-NEXT: xori a0, a0, 84 103; RV64-NEXT: ret 104 %shr4 = ashr i32 %a, 31 105 %conv5 = trunc i32 %shr4 to i8 106 %xor = xor i8 %conv5, 84 107 ret i8 %xor 108} 109 110define i32 @selecti32i32(i32 %a) { 111; RV32-LABEL: selecti32i32: 112; RV32: # %bb.0: 113; RV32-NEXT: srai a0, a0, 31 114; RV32-NEXT: xori a0, a0, 84 115; RV32-NEXT: ret 116; 117; RV64-LABEL: selecti32i32: 118; RV64: # %bb.0: 119; RV64-NEXT: sraiw a0, a0, 31 120; RV64-NEXT: xori a0, a0, 84 121; RV64-NEXT: ret 122 %c = icmp sgt i32 %a, -1 123 %s = select i1 %c, i32 84, i32 -85 124 ret i32 %s 125} 126 127define i8 @selecti32i8(i32 %a) { 128; RV32-LABEL: selecti32i8: 129; RV32: # %bb.0: 130; RV32-NEXT: srai a0, a0, 31 131; RV32-NEXT: xori a0, a0, 84 132; RV32-NEXT: ret 133; 134; RV64-LABEL: selecti32i8: 135; RV64: # %bb.0: 136; RV64-NEXT: sraiw a0, a0, 31 137; RV64-NEXT: xori a0, a0, 84 138; RV64-NEXT: ret 139 %c = icmp sgt i32 %a, -1 140 %s = select i1 %c, i8 84, i8 -85 141 ret i8 %s 142} 143 144define i32 @selecti8i32(i8 %a) { 145; RV32-LABEL: selecti8i32: 146; RV32: # %bb.0: 147; RV32-NEXT: slli a0, a0, 24 148; RV32-NEXT: srai a0, a0, 31 149; RV32-NEXT: xori a0, a0, 84 150; RV32-NEXT: ret 151; 152; RV64-LABEL: selecti8i32: 153; RV64: # %bb.0: 154; RV64-NEXT: slli a0, a0, 56 155; RV64-NEXT: srai a0, a0, 63 156; RV64-NEXT: xori a0, a0, 84 157; RV64-NEXT: ret 158 %c = icmp sgt i8 %a, -1 159 %s = select i1 %c, i32 84, i32 -85 160 ret i32 %s 161} 162 163define i32 @icmpasreq(i32 %input, i32 %a, i32 %b) { 164; RV32-LABEL: icmpasreq: 165; RV32: # %bb.0: 166; RV32-NEXT: bltz a0, .LBB8_2 167; RV32-NEXT: # %bb.1: 168; RV32-NEXT: mv a1, a2 169; RV32-NEXT: .LBB8_2: 170; RV32-NEXT: mv a0, a1 171; RV32-NEXT: ret 172; 173; RV64-LABEL: icmpasreq: 174; RV64: # %bb.0: 175; RV64-NEXT: sext.w a3, a0 176; RV64-NEXT: mv a0, a1 177; RV64-NEXT: bltz a3, .LBB8_2 178; RV64-NEXT: # %bb.1: 179; RV64-NEXT: mv a0, a2 180; RV64-NEXT: .LBB8_2: 181; RV64-NEXT: ret 182 %sh = ashr i32 %input, 31 183 %c = icmp eq i32 %sh, -1 184 %s = select i1 %c, i32 %a, i32 %b 185 ret i32 %s 186} 187 188define i32 @icmpasrne(i32 %input, i32 %a, i32 %b) { 189; RV32-LABEL: icmpasrne: 190; RV32: # %bb.0: 191; RV32-NEXT: bgez a0, .LBB9_2 192; RV32-NEXT: # %bb.1: 193; RV32-NEXT: mv a1, a2 194; RV32-NEXT: .LBB9_2: 195; RV32-NEXT: mv a0, a1 196; RV32-NEXT: ret 197; 198; RV64-LABEL: icmpasrne: 199; RV64: # %bb.0: 200; RV64-NEXT: sext.w a3, a0 201; RV64-NEXT: mv a0, a1 202; RV64-NEXT: bgez a3, .LBB9_2 203; RV64-NEXT: # %bb.1: 204; RV64-NEXT: mv a0, a2 205; RV64-NEXT: .LBB9_2: 206; RV64-NEXT: ret 207 %sh = ashr i32 %input, 31 208 %c = icmp ne i32 %sh, -1 209 %s = select i1 %c, i32 %a, i32 %b 210 ret i32 %s 211} 212 213define i32 @oneusecmp(i32 %a, i32 %b, i32 %d) { 214; RV32-LABEL: oneusecmp: 215; RV32: # %bb.0: 216; RV32-NEXT: srai a3, a0, 31 217; RV32-NEXT: xori a3, a3, 127 218; RV32-NEXT: bltz a0, .LBB10_2 219; RV32-NEXT: # %bb.1: 220; RV32-NEXT: mv a2, a1 221; RV32-NEXT: .LBB10_2: 222; RV32-NEXT: add a0, a3, a2 223; RV32-NEXT: ret 224; 225; RV64-LABEL: oneusecmp: 226; RV64: # %bb.0: 227; RV64-NEXT: sext.w a3, a0 228; RV64-NEXT: sraiw a0, a0, 31 229; RV64-NEXT: xori a0, a0, 127 230; RV64-NEXT: bltz a3, .LBB10_2 231; RV64-NEXT: # %bb.1: 232; RV64-NEXT: mv a2, a1 233; RV64-NEXT: .LBB10_2: 234; RV64-NEXT: addw a0, a0, a2 235; RV64-NEXT: ret 236 %c = icmp sle i32 %a, -1 237 %s = select i1 %c, i32 -128, i32 127 238 %s2 = select i1 %c, i32 %d, i32 %b 239 %x = add i32 %s, %s2 240 ret i32 %x 241} 242