1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ 3; RUN: | FileCheck %s -check-prefix=RV32I 4; RUN: llc -mtriple=riscv64 -mattr=+xmipscmove -verify-machineinstrs < %s \ 5; RUN: | FileCheck -check-prefix=RV64I-CCMOV %s 6 7define i32 @bare_select(i1 %a, i32 %b, i32 %c) nounwind { 8; RV32I-LABEL: bare_select: 9; RV32I: # %bb.0: 10; RV32I-NEXT: andi a3, a0, 1 11; RV32I-NEXT: mv a0, a1 12; RV32I-NEXT: bnez a3, .LBB0_2 13; RV32I-NEXT: # %bb.1: 14; RV32I-NEXT: mv a0, a2 15; RV32I-NEXT: .LBB0_2: 16; RV32I-NEXT: ret 17; 18; RV64I-CCMOV-LABEL: bare_select: 19; RV64I-CCMOV: # %bb.0: 20; RV64I-CCMOV-NEXT: andi a0, a0, 1 21; RV64I-CCMOV-NEXT: mips.ccmov a0, a0, a1, a2 22; RV64I-CCMOV-NEXT: ret 23 %1 = select i1 %a, i32 %b, i32 %c 24 ret i32 %1 25} 26 27define float @bare_select_float(i1 %a, float %b, float %c) nounwind { 28; RV32I-LABEL: bare_select_float: 29; RV32I: # %bb.0: 30; RV32I-NEXT: andi a3, a0, 1 31; RV32I-NEXT: mv a0, a1 32; RV32I-NEXT: bnez a3, .LBB1_2 33; RV32I-NEXT: # %bb.1: 34; RV32I-NEXT: mv a0, a2 35; RV32I-NEXT: .LBB1_2: 36; RV32I-NEXT: ret 37; 38; RV64I-CCMOV-LABEL: bare_select_float: 39; RV64I-CCMOV: # %bb.0: 40; RV64I-CCMOV-NEXT: andi a0, a0, 1 41; RV64I-CCMOV-NEXT: mips.ccmov a0, a0, a1, a2 42; RV64I-CCMOV-NEXT: ret 43 %1 = select i1 %a, float %b, float %c 44 ret float %1 45} 46