xref: /llvm-project/llvm/test/CodeGen/RISCV/scmp.ll (revision 14c4f28ec109ec84158d60a74d3d1b7bfa411c77) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
2; RUN: llc < %s -mtriple=riscv32 | FileCheck %s --check-prefix=RV32I
3; RUN: llc < %s -mtriple=riscv64 | FileCheck %s --check-prefix=RV64I
4
5define i8 @scmp.8.8(i8 signext %x, i8 signext %y) nounwind {
6; RV32I-LABEL: scmp.8.8:
7; RV32I:       # %bb.0:
8; RV32I-NEXT:    slt a2, a0, a1
9; RV32I-NEXT:    slt a0, a1, a0
10; RV32I-NEXT:    sub a0, a0, a2
11; RV32I-NEXT:    ret
12;
13; RV64I-LABEL: scmp.8.8:
14; RV64I:       # %bb.0:
15; RV64I-NEXT:    slt a2, a0, a1
16; RV64I-NEXT:    slt a0, a1, a0
17; RV64I-NEXT:    sub a0, a0, a2
18; RV64I-NEXT:    ret
19  %1 = call i8 @llvm.scmp(i8 %x, i8 %y)
20  ret i8 %1
21}
22
23define i8 @scmp.8.16(i16 signext %x, i16 signext %y) nounwind {
24; RV32I-LABEL: scmp.8.16:
25; RV32I:       # %bb.0:
26; RV32I-NEXT:    slt a2, a0, a1
27; RV32I-NEXT:    slt a0, a1, a0
28; RV32I-NEXT:    sub a0, a0, a2
29; RV32I-NEXT:    ret
30;
31; RV64I-LABEL: scmp.8.16:
32; RV64I:       # %bb.0:
33; RV64I-NEXT:    slt a2, a0, a1
34; RV64I-NEXT:    slt a0, a1, a0
35; RV64I-NEXT:    sub a0, a0, a2
36; RV64I-NEXT:    ret
37  %1 = call i8 @llvm.scmp(i16 %x, i16 %y)
38  ret i8 %1
39}
40
41define i8 @scmp.8.32(i32 %x, i32 %y) nounwind {
42; RV32I-LABEL: scmp.8.32:
43; RV32I:       # %bb.0:
44; RV32I-NEXT:    slt a2, a0, a1
45; RV32I-NEXT:    slt a0, a1, a0
46; RV32I-NEXT:    sub a0, a0, a2
47; RV32I-NEXT:    ret
48;
49; RV64I-LABEL: scmp.8.32:
50; RV64I:       # %bb.0:
51; RV64I-NEXT:    sext.w a1, a1
52; RV64I-NEXT:    sext.w a0, a0
53; RV64I-NEXT:    slt a2, a0, a1
54; RV64I-NEXT:    slt a0, a1, a0
55; RV64I-NEXT:    sub a0, a0, a2
56; RV64I-NEXT:    ret
57  %1 = call i8 @llvm.scmp(i32 %x, i32 %y)
58  ret i8 %1
59}
60
61define i8 @scmp.8.64(i64 %x, i64 %y) nounwind {
62; RV32I-LABEL: scmp.8.64:
63; RV32I:       # %bb.0:
64; RV32I-NEXT:    beq a1, a3, .LBB3_2
65; RV32I-NEXT:  # %bb.1:
66; RV32I-NEXT:    slt a4, a1, a3
67; RV32I-NEXT:    slt a0, a3, a1
68; RV32I-NEXT:    sub a0, a0, a4
69; RV32I-NEXT:    ret
70; RV32I-NEXT:  .LBB3_2:
71; RV32I-NEXT:    sltu a4, a0, a2
72; RV32I-NEXT:    sltu a0, a2, a0
73; RV32I-NEXT:    sub a0, a0, a4
74; RV32I-NEXT:    ret
75;
76; RV64I-LABEL: scmp.8.64:
77; RV64I:       # %bb.0:
78; RV64I-NEXT:    slt a2, a0, a1
79; RV64I-NEXT:    slt a0, a1, a0
80; RV64I-NEXT:    sub a0, a0, a2
81; RV64I-NEXT:    ret
82  %1 = call i8 @llvm.scmp(i64 %x, i64 %y)
83  ret i8 %1
84}
85
86define i8 @scmp.8.128(i128 %x, i128 %y) nounwind {
87; RV32I-LABEL: scmp.8.128:
88; RV32I:       # %bb.0:
89; RV32I-NEXT:    lw a2, 4(a1)
90; RV32I-NEXT:    lw a4, 8(a1)
91; RV32I-NEXT:    lw a5, 12(a1)
92; RV32I-NEXT:    lw a6, 12(a0)
93; RV32I-NEXT:    lw a3, 4(a0)
94; RV32I-NEXT:    lw a7, 8(a0)
95; RV32I-NEXT:    beq a6, a5, .LBB4_2
96; RV32I-NEXT:  # %bb.1:
97; RV32I-NEXT:    slt t2, a6, a5
98; RV32I-NEXT:    j .LBB4_3
99; RV32I-NEXT:  .LBB4_2:
100; RV32I-NEXT:    sltu t2, a7, a4
101; RV32I-NEXT:  .LBB4_3:
102; RV32I-NEXT:    lw a1, 0(a1)
103; RV32I-NEXT:    lw t0, 0(a0)
104; RV32I-NEXT:    beq a3, a2, .LBB4_5
105; RV32I-NEXT:  # %bb.4:
106; RV32I-NEXT:    sltu a0, a3, a2
107; RV32I-NEXT:    j .LBB4_6
108; RV32I-NEXT:  .LBB4_5:
109; RV32I-NEXT:    sltu a0, t0, a1
110; RV32I-NEXT:  .LBB4_6:
111; RV32I-NEXT:    xor t1, a6, a5
112; RV32I-NEXT:    xor t3, a7, a4
113; RV32I-NEXT:    or t1, t3, t1
114; RV32I-NEXT:    beqz t1, .LBB4_8
115; RV32I-NEXT:  # %bb.7:
116; RV32I-NEXT:    mv a0, t2
117; RV32I-NEXT:  .LBB4_8:
118; RV32I-NEXT:    beq a6, a5, .LBB4_11
119; RV32I-NEXT:  # %bb.9:
120; RV32I-NEXT:    slt a4, a5, a6
121; RV32I-NEXT:    bne a3, a2, .LBB4_12
122; RV32I-NEXT:  .LBB4_10:
123; RV32I-NEXT:    sltu a1, a1, t0
124; RV32I-NEXT:    bnez t1, .LBB4_13
125; RV32I-NEXT:    j .LBB4_14
126; RV32I-NEXT:  .LBB4_11:
127; RV32I-NEXT:    sltu a4, a4, a7
128; RV32I-NEXT:    beq a3, a2, .LBB4_10
129; RV32I-NEXT:  .LBB4_12:
130; RV32I-NEXT:    sltu a1, a2, a3
131; RV32I-NEXT:    beqz t1, .LBB4_14
132; RV32I-NEXT:  .LBB4_13:
133; RV32I-NEXT:    mv a1, a4
134; RV32I-NEXT:  .LBB4_14:
135; RV32I-NEXT:    sub a0, a1, a0
136; RV32I-NEXT:    ret
137;
138; RV64I-LABEL: scmp.8.128:
139; RV64I:       # %bb.0:
140; RV64I-NEXT:    beq a1, a3, .LBB4_2
141; RV64I-NEXT:  # %bb.1:
142; RV64I-NEXT:    slt a4, a1, a3
143; RV64I-NEXT:    slt a0, a3, a1
144; RV64I-NEXT:    sub a0, a0, a4
145; RV64I-NEXT:    ret
146; RV64I-NEXT:  .LBB4_2:
147; RV64I-NEXT:    sltu a4, a0, a2
148; RV64I-NEXT:    sltu a0, a2, a0
149; RV64I-NEXT:    sub a0, a0, a4
150; RV64I-NEXT:    ret
151  %1 = call i8 @llvm.scmp(i128 %x, i128 %y)
152  ret i8 %1
153}
154
155define i32 @scmp.32.32(i32 %x, i32 %y) nounwind {
156; RV32I-LABEL: scmp.32.32:
157; RV32I:       # %bb.0:
158; RV32I-NEXT:    slt a2, a0, a1
159; RV32I-NEXT:    slt a0, a1, a0
160; RV32I-NEXT:    sub a0, a0, a2
161; RV32I-NEXT:    ret
162;
163; RV64I-LABEL: scmp.32.32:
164; RV64I:       # %bb.0:
165; RV64I-NEXT:    sext.w a1, a1
166; RV64I-NEXT:    sext.w a0, a0
167; RV64I-NEXT:    slt a2, a0, a1
168; RV64I-NEXT:    slt a0, a1, a0
169; RV64I-NEXT:    sub a0, a0, a2
170; RV64I-NEXT:    ret
171  %1 = call i32 @llvm.scmp(i32 %x, i32 %y)
172  ret i32 %1
173}
174
175define i32 @scmp.32.64(i64 %x, i64 %y) nounwind {
176; RV32I-LABEL: scmp.32.64:
177; RV32I:       # %bb.0:
178; RV32I-NEXT:    beq a1, a3, .LBB6_2
179; RV32I-NEXT:  # %bb.1:
180; RV32I-NEXT:    slt a4, a1, a3
181; RV32I-NEXT:    slt a0, a3, a1
182; RV32I-NEXT:    sub a0, a0, a4
183; RV32I-NEXT:    ret
184; RV32I-NEXT:  .LBB6_2:
185; RV32I-NEXT:    sltu a4, a0, a2
186; RV32I-NEXT:    sltu a0, a2, a0
187; RV32I-NEXT:    sub a0, a0, a4
188; RV32I-NEXT:    ret
189;
190; RV64I-LABEL: scmp.32.64:
191; RV64I:       # %bb.0:
192; RV64I-NEXT:    slt a2, a0, a1
193; RV64I-NEXT:    slt a0, a1, a0
194; RV64I-NEXT:    sub a0, a0, a2
195; RV64I-NEXT:    ret
196  %1 = call i32 @llvm.scmp(i64 %x, i64 %y)
197  ret i32 %1
198}
199
200define i64 @scmp.64.64(i64 %x, i64 %y) nounwind {
201; RV32I-LABEL: scmp.64.64:
202; RV32I:       # %bb.0:
203; RV32I-NEXT:    beq a1, a3, .LBB7_2
204; RV32I-NEXT:  # %bb.1:
205; RV32I-NEXT:    slt a4, a1, a3
206; RV32I-NEXT:    slt a0, a3, a1
207; RV32I-NEXT:    j .LBB7_3
208; RV32I-NEXT:  .LBB7_2:
209; RV32I-NEXT:    sltu a4, a0, a2
210; RV32I-NEXT:    sltu a0, a2, a0
211; RV32I-NEXT:  .LBB7_3:
212; RV32I-NEXT:    sub a0, a0, a4
213; RV32I-NEXT:    srai a1, a0, 31
214; RV32I-NEXT:    ret
215;
216; RV64I-LABEL: scmp.64.64:
217; RV64I:       # %bb.0:
218; RV64I-NEXT:    slt a2, a0, a1
219; RV64I-NEXT:    slt a0, a1, a0
220; RV64I-NEXT:    sub a0, a0, a2
221; RV64I-NEXT:    ret
222  %1 = call i64 @llvm.scmp(i64 %x, i64 %y)
223  ret i64 %1
224}
225