xref: /llvm-project/llvm/test/CodeGen/RISCV/rvv/xtheadvdot-vmaqa.ll (revision f2bdc29f3e5dd4d8d65081094f8afc789d58706a) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+xtheadvdot \
3; RUN:   -verify-machineinstrs | FileCheck %s
4; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+xtheadvdot \
5; RUN:   -verify-machineinstrs | FileCheck %s
6
7declare <vscale x 1 x i32> @llvm.riscv.th.vmaqa.nxv1i32.nxv4i8(
8  <vscale x 1 x i32>,
9  <vscale x 4 x i8>,
10  <vscale x 4 x i8>,
11  iXLen,
12  iXLen);
13
14define <vscale x 1 x i32>  @intrinsic_th_vmaqa_vv_nxv1i32_nxv4i8_nxv4i8(<vscale x 1 x i32> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, iXLen %3) nounwind {
15; CHECK-LABEL: intrinsic_th_vmaqa_vv_nxv1i32_nxv4i8_nxv4i8:
16; CHECK:       # %bb.0: # %entry
17; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, tu, ma
18; CHECK-NEXT:    th.vmaqa.vv v8, v9, v10
19; CHECK-NEXT:    ret
20entry:
21  %a = call <vscale x 1 x i32> @llvm.riscv.th.vmaqa.nxv1i32.nxv4i8(
22    <vscale x 1 x i32> %0,
23    <vscale x 4 x i8> %1,
24    <vscale x 4 x i8> %2,
25    iXLen %3, iXLen 0)
26
27  ret <vscale x 1 x i32> %a
28}
29
30declare <vscale x 1 x i32> @llvm.riscv.th.vmaqa.mask.nxv1i32.nxv4i8(
31  <vscale x 1 x i32>,
32  <vscale x 4 x i8>,
33  <vscale x 4 x i8>,
34  <vscale x 4 x i1>,
35  iXLen, iXLen);
36
37define <vscale x 1 x i32>  @intrinsic_th_vmaqa_mask_vv_nxv1i32_nxv4i8_nxv4i8(<vscale x 1 x i32> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
38; CHECK-LABEL: intrinsic_th_vmaqa_mask_vv_nxv1i32_nxv4i8_nxv4i8:
39; CHECK:       # %bb.0: # %entry
40; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, tu, mu
41; CHECK-NEXT:    th.vmaqa.vv v8, v9, v10, v0.t
42; CHECK-NEXT:    ret
43entry:
44  %a = call <vscale x 1 x i32> @llvm.riscv.th.vmaqa.mask.nxv1i32.nxv4i8(
45    <vscale x 1 x i32> %0,
46    <vscale x 4 x i8> %1,
47    <vscale x 4 x i8> %2,
48    <vscale x 4 x i1> %3,
49    iXLen %4, iXLen 0)
50
51  ret <vscale x 1 x i32> %a
52}
53
54declare <vscale x 2 x i32> @llvm.riscv.th.vmaqa.nxv2i32.nxv8i8(
55  <vscale x 2 x i32>,
56  <vscale x 8 x i8>,
57  <vscale x 8 x i8>,
58  iXLen,
59  iXLen);
60
61define <vscale x 2 x i32>  @intrinsic_th_vmaqa_vv_nxv2i32_nxv8i8_nxv8i8(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {
62; CHECK-LABEL: intrinsic_th_vmaqa_vv_nxv2i32_nxv8i8_nxv8i8:
63; CHECK:       # %bb.0: # %entry
64; CHECK-NEXT:    vsetvli zero, a0, e32, m1, tu, ma
65; CHECK-NEXT:    th.vmaqa.vv v8, v9, v10
66; CHECK-NEXT:    ret
67entry:
68  %a = call <vscale x 2 x i32> @llvm.riscv.th.vmaqa.nxv2i32.nxv8i8(
69    <vscale x 2 x i32> %0,
70    <vscale x 8 x i8> %1,
71    <vscale x 8 x i8> %2,
72    iXLen %3, iXLen 0)
73
74  ret <vscale x 2 x i32> %a
75}
76
77declare <vscale x 2 x i32> @llvm.riscv.th.vmaqa.mask.nxv2i32.nxv8i8(
78  <vscale x 2 x i32>,
79  <vscale x 8 x i8>,
80  <vscale x 8 x i8>,
81  <vscale x 8 x i1>,
82  iXLen, iXLen);
83
84define <vscale x 2 x i32>  @intrinsic_th_vmaqa_mask_vv_nxv2i32_nxv8i8_nxv8i8(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
85; CHECK-LABEL: intrinsic_th_vmaqa_mask_vv_nxv2i32_nxv8i8_nxv8i8:
86; CHECK:       # %bb.0: # %entry
87; CHECK-NEXT:    vsetvli zero, a0, e32, m1, tu, mu
88; CHECK-NEXT:    th.vmaqa.vv v8, v9, v10, v0.t
89; CHECK-NEXT:    ret
90entry:
91  %a = call <vscale x 2 x i32> @llvm.riscv.th.vmaqa.mask.nxv2i32.nxv8i8(
92    <vscale x 2 x i32> %0,
93    <vscale x 8 x i8> %1,
94    <vscale x 8 x i8> %2,
95    <vscale x 8 x i1> %3,
96    iXLen %4, iXLen 0)
97
98  ret <vscale x 2 x i32> %a
99}
100
101declare <vscale x 4 x i32> @llvm.riscv.th.vmaqa.nxv4i32.nxv16i8(
102  <vscale x 4 x i32>,
103  <vscale x 16 x i8>,
104  <vscale x 16 x i8>,
105  iXLen,
106  iXLen);
107
108define <vscale x 4 x i32>  @intrinsic_th_vmaqa_vv_nxv4i32_nxv16i8_nxv16i8(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, iXLen %3) nounwind {
109; CHECK-LABEL: intrinsic_th_vmaqa_vv_nxv4i32_nxv16i8_nxv16i8:
110; CHECK:       # %bb.0: # %entry
111; CHECK-NEXT:    vsetvli zero, a0, e32, m2, tu, ma
112; CHECK-NEXT:    th.vmaqa.vv v8, v10, v12
113; CHECK-NEXT:    ret
114entry:
115  %a = call <vscale x 4 x i32> @llvm.riscv.th.vmaqa.nxv4i32.nxv16i8(
116    <vscale x 4 x i32> %0,
117    <vscale x 16 x i8> %1,
118    <vscale x 16 x i8> %2,
119    iXLen %3, iXLen 0)
120
121  ret <vscale x 4 x i32> %a
122}
123
124declare <vscale x 4 x i32> @llvm.riscv.th.vmaqa.mask.nxv4i32.nxv16i8(
125  <vscale x 4 x i32>,
126  <vscale x 16 x i8>,
127  <vscale x 16 x i8>,
128  <vscale x 16 x i1>,
129  iXLen, iXLen);
130
131define <vscale x 4 x i32>  @intrinsic_th_vmaqa_mask_vv_nxv4i32_nxv16i8_nxv16i8(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
132; CHECK-LABEL: intrinsic_th_vmaqa_mask_vv_nxv4i32_nxv16i8_nxv16i8:
133; CHECK:       # %bb.0: # %entry
134; CHECK-NEXT:    vsetvli zero, a0, e32, m2, tu, mu
135; CHECK-NEXT:    th.vmaqa.vv v8, v10, v12, v0.t
136; CHECK-NEXT:    ret
137entry:
138  %a = call <vscale x 4 x i32> @llvm.riscv.th.vmaqa.mask.nxv4i32.nxv16i8(
139    <vscale x 4 x i32> %0,
140    <vscale x 16 x i8> %1,
141    <vscale x 16 x i8> %2,
142    <vscale x 16 x i1> %3,
143    iXLen %4, iXLen 0)
144
145  ret <vscale x 4 x i32> %a
146}
147
148declare <vscale x 8 x i32> @llvm.riscv.th.vmaqa.nxv8i32.nxv32i8(
149  <vscale x 8 x i32>,
150  <vscale x 32 x i8>,
151  <vscale x 32 x i8>,
152  iXLen,
153  iXLen);
154
155define <vscale x 8 x i32>  @intrinsic_th_vmaqa_vv_nxv8i32_nxv32i8_nxv32i8(<vscale x 8 x i32> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, iXLen %3) nounwind {
156; CHECK-LABEL: intrinsic_th_vmaqa_vv_nxv8i32_nxv32i8_nxv32i8:
157; CHECK:       # %bb.0: # %entry
158; CHECK-NEXT:    vsetvli zero, a0, e32, m4, tu, ma
159; CHECK-NEXT:    th.vmaqa.vv v8, v12, v16
160; CHECK-NEXT:    ret
161entry:
162  %a = call <vscale x 8 x i32> @llvm.riscv.th.vmaqa.nxv8i32.nxv32i8(
163    <vscale x 8 x i32> %0,
164    <vscale x 32 x i8> %1,
165    <vscale x 32 x i8> %2,
166    iXLen %3, iXLen 0)
167
168  ret <vscale x 8 x i32> %a
169}
170
171declare <vscale x 8 x i32> @llvm.riscv.th.vmaqa.mask.nxv8i32.nxv32i8(
172  <vscale x 8 x i32>,
173  <vscale x 32 x i8>,
174  <vscale x 32 x i8>,
175  <vscale x 32 x i1>,
176  iXLen, iXLen);
177
178define <vscale x 8 x i32>  @intrinsic_th_vmaqa_mask_vv_nxv8i32_nxv32i8_nxv32i8(<vscale x 8 x i32> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {
179; CHECK-LABEL: intrinsic_th_vmaqa_mask_vv_nxv8i32_nxv32i8_nxv32i8:
180; CHECK:       # %bb.0: # %entry
181; CHECK-NEXT:    vsetvli zero, a0, e32, m4, tu, mu
182; CHECK-NEXT:    th.vmaqa.vv v8, v12, v16, v0.t
183; CHECK-NEXT:    ret
184entry:
185  %a = call <vscale x 8 x i32> @llvm.riscv.th.vmaqa.mask.nxv8i32.nxv32i8(
186    <vscale x 8 x i32> %0,
187    <vscale x 32 x i8> %1,
188    <vscale x 32 x i8> %2,
189    <vscale x 32 x i1> %3,
190    iXLen %4, iXLen 0)
191
192  ret <vscale x 8 x i32> %a
193}
194
195
196declare <vscale x 1 x i32> @llvm.riscv.th.vmaqa.nxv1i32.i8(
197  <vscale x 1 x i32>,
198  i8,
199  <vscale x 4 x i8>,
200  iXLen,
201  iXLen);
202
203define <vscale x 1 x i32>  @intrinsic_th_vmaqa_vx_nxv1i32_i8_nxv4i8(<vscale x 1 x i32> %0, i8 %1, <vscale x 4 x i8> %2, iXLen %3) nounwind {
204; CHECK-LABEL: intrinsic_th_vmaqa_vx_nxv1i32_i8_nxv4i8:
205; CHECK:       # %bb.0: # %entry
206; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, tu, ma
207; CHECK-NEXT:    th.vmaqa.vx v8, a0, v9
208; CHECK-NEXT:    ret
209entry:
210  %a = call <vscale x 1 x i32> @llvm.riscv.th.vmaqa.nxv1i32.i8(
211    <vscale x 1 x i32> %0,
212    i8 %1,
213    <vscale x 4 x i8> %2,
214    iXLen %3, iXLen 0)
215
216  ret <vscale x 1 x i32> %a
217}
218
219declare <vscale x 1 x i32> @llvm.riscv.th.vmaqa.mask.nxv1i32.i8(
220  <vscale x 1 x i32>,
221  i8,
222  <vscale x 4 x i8>,
223  <vscale x 4 x i1>,
224  iXLen, iXLen);
225
226define <vscale x 1 x i32> @intrinsic_th_vmaqa_mask_vx_nxv1i32_i8_nxv4i8(<vscale x 1 x i32> %0, i8 %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
227; CHECK-LABEL: intrinsic_th_vmaqa_mask_vx_nxv1i32_i8_nxv4i8:
228; CHECK:       # %bb.0: # %entry
229; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, tu, mu
230; CHECK-NEXT:    th.vmaqa.vx v8, a0, v9, v0.t
231; CHECK-NEXT:    ret
232entry:
233  %a = call <vscale x 1 x i32> @llvm.riscv.th.vmaqa.mask.nxv1i32.i8(
234    <vscale x 1 x i32> %0,
235    i8 %1,
236    <vscale x 4 x i8> %2,
237    <vscale x 4 x i1> %3,
238    iXLen %4, iXLen 0)
239
240  ret <vscale x 1 x i32> %a
241}
242
243declare <vscale x 2 x i32> @llvm.riscv.th.vmaqa.nxv2i32.i8(
244  <vscale x 2 x i32>,
245  i8,
246  <vscale x 8 x i8>,
247  iXLen,
248  iXLen);
249
250define <vscale x 2 x i32>  @intrinsic_th_vmaqa_vx_nxv2i32_i8_nxv8i8(<vscale x 2 x i32> %0, i8 %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {
251; CHECK-LABEL: intrinsic_th_vmaqa_vx_nxv2i32_i8_nxv8i8:
252; CHECK:       # %bb.0: # %entry
253; CHECK-NEXT:    vsetvli zero, a1, e32, m1, tu, ma
254; CHECK-NEXT:    th.vmaqa.vx v8, a0, v9
255; CHECK-NEXT:    ret
256entry:
257  %a = call <vscale x 2 x i32> @llvm.riscv.th.vmaqa.nxv2i32.i8(
258    <vscale x 2 x i32> %0,
259    i8 %1,
260    <vscale x 8 x i8> %2,
261    iXLen %3, iXLen 0)
262
263  ret <vscale x 2 x i32> %a
264}
265
266declare <vscale x 2 x i32> @llvm.riscv.th.vmaqa.mask.nxv2i32.i8(
267  <vscale x 2 x i32>,
268  i8,
269  <vscale x 8 x i8>,
270  <vscale x 8 x i1>,
271  iXLen, iXLen);
272
273define <vscale x 2 x i32> @intrinsic_th_vmaqa_mask_vx_nxv2i32_i8_nxv8i8(<vscale x 2 x i32> %0, i8 %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
274; CHECK-LABEL: intrinsic_th_vmaqa_mask_vx_nxv2i32_i8_nxv8i8:
275; CHECK:       # %bb.0: # %entry
276; CHECK-NEXT:    vsetvli zero, a1, e32, m1, tu, mu
277; CHECK-NEXT:    th.vmaqa.vx v8, a0, v9, v0.t
278; CHECK-NEXT:    ret
279entry:
280  %a = call <vscale x 2 x i32> @llvm.riscv.th.vmaqa.mask.nxv2i32.i8(
281    <vscale x 2 x i32> %0,
282    i8 %1,
283    <vscale x 8 x i8> %2,
284    <vscale x 8 x i1> %3,
285    iXLen %4, iXLen 0)
286
287  ret <vscale x 2 x i32> %a
288}
289
290declare <vscale x 4 x i32> @llvm.riscv.th.vmaqa.nxv4i32.i8(
291  <vscale x 4 x i32>,
292  i8,
293  <vscale x 16 x i8>,
294  iXLen,
295  iXLen);
296
297define <vscale x 4 x i32>  @intrinsic_th_vmaqa_vx_nxv4i32_i8_nxv16i8(<vscale x 4 x i32> %0, i8 %1, <vscale x 16 x i8> %2, iXLen %3) nounwind {
298; CHECK-LABEL: intrinsic_th_vmaqa_vx_nxv4i32_i8_nxv16i8:
299; CHECK:       # %bb.0: # %entry
300; CHECK-NEXT:    vsetvli zero, a1, e32, m2, tu, ma
301; CHECK-NEXT:    th.vmaqa.vx v8, a0, v10
302; CHECK-NEXT:    ret
303entry:
304  %a = call <vscale x 4 x i32> @llvm.riscv.th.vmaqa.nxv4i32.i8(
305    <vscale x 4 x i32> %0,
306    i8 %1,
307    <vscale x 16 x i8> %2,
308    iXLen %3, iXLen 0)
309
310  ret <vscale x 4 x i32> %a
311}
312
313declare <vscale x 4 x i32> @llvm.riscv.th.vmaqa.mask.nxv4i32.i8(
314  <vscale x 4 x i32>,
315  i8,
316  <vscale x 16 x i8>,
317  <vscale x 16 x i1>,
318  iXLen, iXLen);
319
320define <vscale x 4 x i32> @intrinsic_th_vmaqa_mask_vx_nxv4i32_i8_nxv16i8(<vscale x 4 x i32> %0, i8 %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
321; CHECK-LABEL: intrinsic_th_vmaqa_mask_vx_nxv4i32_i8_nxv16i8:
322; CHECK:       # %bb.0: # %entry
323; CHECK-NEXT:    vsetvli zero, a1, e32, m2, tu, mu
324; CHECK-NEXT:    th.vmaqa.vx v8, a0, v10, v0.t
325; CHECK-NEXT:    ret
326entry:
327  %a = call <vscale x 4 x i32> @llvm.riscv.th.vmaqa.mask.nxv4i32.i8(
328    <vscale x 4 x i32> %0,
329    i8 %1,
330    <vscale x 16 x i8> %2,
331    <vscale x 16 x i1> %3,
332    iXLen %4, iXLen 0)
333
334  ret <vscale x 4 x i32> %a
335}
336
337declare <vscale x 8 x i32> @llvm.riscv.th.vmaqa.nxv8i32.i8(
338  <vscale x 8 x i32>,
339  i8,
340  <vscale x 32 x i8>,
341  iXLen,
342  iXLen);
343
344define <vscale x 8 x i32>  @intrinsic_th_vmaqa_vx_nxv8i32_i8_nxv32i8(<vscale x 8 x i32> %0, i8 %1, <vscale x 32 x i8> %2, iXLen %3) nounwind {
345; CHECK-LABEL: intrinsic_th_vmaqa_vx_nxv8i32_i8_nxv32i8:
346; CHECK:       # %bb.0: # %entry
347; CHECK-NEXT:    vsetvli zero, a1, e32, m4, tu, ma
348; CHECK-NEXT:    th.vmaqa.vx v8, a0, v12
349; CHECK-NEXT:    ret
350entry:
351  %a = call <vscale x 8 x i32> @llvm.riscv.th.vmaqa.nxv8i32.i8(
352    <vscale x 8 x i32> %0,
353    i8 %1,
354    <vscale x 32 x i8> %2,
355    iXLen %3, iXLen 0)
356
357  ret <vscale x 8 x i32> %a
358}
359
360declare <vscale x 8 x i32> @llvm.riscv.th.vmaqa.mask.nxv8i32.i8(
361  <vscale x 8 x i32>,
362  i8,
363  <vscale x 32 x i8>,
364  <vscale x 32 x i1>,
365  iXLen, iXLen);
366
367define <vscale x 8 x i32> @intrinsic_th_vmaqa_mask_vx_nxv8i32_i8_nxv32i8(<vscale x 8 x i32> %0, i8 %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {
368; CHECK-LABEL: intrinsic_th_vmaqa_mask_vx_nxv8i32_i8_nxv32i8:
369; CHECK:       # %bb.0: # %entry
370; CHECK-NEXT:    vsetvli zero, a1, e32, m4, tu, mu
371; CHECK-NEXT:    th.vmaqa.vx v8, a0, v12, v0.t
372; CHECK-NEXT:    ret
373entry:
374  %a = call <vscale x 8 x i32> @llvm.riscv.th.vmaqa.mask.nxv8i32.i8(
375    <vscale x 8 x i32> %0,
376    i8 %1,
377    <vscale x 32 x i8> %2,
378    <vscale x 32 x i1> %3,
379    iXLen %4, iXLen 0)
380
381  ret <vscale x 8 x i32> %a
382}
383