1# NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2# RUN: llc -mtriple=riscv64 -mattr=+m,+v -o - %s \ 3# RUN: -start-before=prologepilog | FileCheck %s 4# 5# This test checks that we are assigning the right stack slot to GPRs and to 6# vector registers (VRs). If this test changes, make sure there is no overlap 7# between slots for GPRs and VRs. 8--- | 9 define void @foo() #0 { 10 ; CHECK-LABEL: foo: 11 ; CHECK: # %bb.0: # %entry 12 ; CHECK-NEXT: addi sp, sp, -48 13 ; CHECK-NEXT: sd s9, 40(sp) # 8-byte Folded Spill 14 ; CHECK-NEXT: csrr a1, vlenb 15 ; CHECK-NEXT: slli a1, a1, 1 16 ; CHECK-NEXT: sub sp, sp, a1 17 ; CHECK-NEXT: sd a0, 16(sp) # 8-byte Folded Spill 18 ; CHECK-NEXT: addi a0, sp, 32 19 ; CHECK-NEXT: vs2r.v v30, (a0) # Unknown-size Folded Spill 20 ; CHECK-NEXT: csrr a0, vlenb 21 ; CHECK-NEXT: slli a0, a0, 1 22 ; CHECK-NEXT: add sp, sp, a0 23 ; CHECK-NEXT: ld s9, 40(sp) # 8-byte Folded Reload 24 ; CHECK-NEXT: addi sp, sp, 48 25 ; CHECK-NEXT: ret 26 entry: 27 ret void 28 } 29 30 attributes #0 = { nounwind } 31... 32--- 33name: foo 34alignment: 2 35tracksRegLiveness: true 36frameInfo: 37 maxAlignment: 8 38stack: 39 - { id: 0, type: spill-slot, size: 8, alignment: 8 } 40 - { id: 1, type: spill-slot, size: 16, alignment: 8, stack-id: scalable-vector } 41machineFunctionInfo: {} 42body: | 43 bb.0.entry: 44 liveins: $x10, $v30m2 45 46 $x25 = COPY $x10 47 SD renamable $x25, %stack.0, 0 :: (store (s64) into %stack.0) 48 VS2R_V renamable $v30m2, %stack.1 :: (store unknown-size into %stack.1, align 8) 49 PseudoRET 50 51... 52