xref: /llvm-project/llvm/test/CodeGen/RISCV/rvv/vzext-vp.ll (revision b6c0f1bfa79a3a32d841ac5ab1f94c3aee3b5d90) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+v < %s | FileCheck %s
3; RUN: llc -mtriple=riscv64 -mattr=+v < %s | FileCheck %s
4
5declare <vscale x 2 x i16> @llvm.vp.zext.nxv2i16.nxv2i8(<vscale x 2 x i8>, <vscale x 2 x i1>, i32)
6
7define <vscale x 2 x i16> @vzext_nxv2i8_nxv2i16(<vscale x 2 x i8> %a, <vscale x 2 x i1> %m, i32 zeroext %vl) {
8; CHECK-LABEL: vzext_nxv2i8_nxv2i16:
9; CHECK:       # %bb.0:
10; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma
11; CHECK-NEXT:    vzext.vf2 v9, v8, v0.t
12; CHECK-NEXT:    vmv1r.v v8, v9
13; CHECK-NEXT:    ret
14  %v = call <vscale x 2 x i16> @llvm.vp.zext.nxv2i16.nxv2i8(<vscale x 2 x i8> %a, <vscale x 2 x i1> %m, i32 %vl)
15  ret <vscale x 2 x i16> %v
16}
17
18define <vscale x 2 x i16> @vzext_nxv2i8_nxv2i16_unmasked(<vscale x 2 x i8> %a, i32 zeroext %vl) {
19; CHECK-LABEL: vzext_nxv2i8_nxv2i16_unmasked:
20; CHECK:       # %bb.0:
21; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma
22; CHECK-NEXT:    vzext.vf2 v9, v8
23; CHECK-NEXT:    vmv1r.v v8, v9
24; CHECK-NEXT:    ret
25  %v = call <vscale x 2 x i16> @llvm.vp.zext.nxv2i16.nxv2i8(<vscale x 2 x i8> %a, <vscale x 2 x i1> splat (i1 true), i32 %vl)
26  ret <vscale x 2 x i16> %v
27}
28
29declare <vscale x 2 x i32> @llvm.vp.zext.nxv2i32.nxv2i8(<vscale x 2 x i8>, <vscale x 2 x i1>, i32)
30
31define <vscale x 2 x i32> @vzext_nxv2i8_nxv2i32(<vscale x 2 x i8> %a, <vscale x 2 x i1> %m, i32 zeroext %vl) {
32; CHECK-LABEL: vzext_nxv2i8_nxv2i32:
33; CHECK:       # %bb.0:
34; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma
35; CHECK-NEXT:    vzext.vf4 v9, v8, v0.t
36; CHECK-NEXT:    vmv.v.v v8, v9
37; CHECK-NEXT:    ret
38  %v = call <vscale x 2 x i32> @llvm.vp.zext.nxv2i32.nxv2i8(<vscale x 2 x i8> %a, <vscale x 2 x i1> %m, i32 %vl)
39  ret <vscale x 2 x i32> %v
40}
41
42define <vscale x 2 x i32> @vzext_nxv2i8_nxv2i32_unmasked(<vscale x 2 x i8> %a, i32 zeroext %vl) {
43; CHECK-LABEL: vzext_nxv2i8_nxv2i32_unmasked:
44; CHECK:       # %bb.0:
45; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma
46; CHECK-NEXT:    vzext.vf4 v9, v8
47; CHECK-NEXT:    vmv.v.v v8, v9
48; CHECK-NEXT:    ret
49  %v = call <vscale x 2 x i32> @llvm.vp.zext.nxv2i32.nxv2i8(<vscale x 2 x i8> %a, <vscale x 2 x i1> splat (i1 true), i32 %vl)
50  ret <vscale x 2 x i32> %v
51}
52
53declare <vscale x 2 x i64> @llvm.vp.zext.nxv2i64.nxv2i8(<vscale x 2 x i8>, <vscale x 2 x i1>, i32)
54
55define <vscale x 2 x i64> @vzext_nxv2i8_nxv2i64(<vscale x 2 x i8> %a, <vscale x 2 x i1> %m, i32 zeroext %vl) {
56; CHECK-LABEL: vzext_nxv2i8_nxv2i64:
57; CHECK:       # %bb.0:
58; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, ma
59; CHECK-NEXT:    vzext.vf8 v10, v8, v0.t
60; CHECK-NEXT:    vmv.v.v v8, v10
61; CHECK-NEXT:    ret
62  %v = call <vscale x 2 x i64> @llvm.vp.zext.nxv2i64.nxv2i8(<vscale x 2 x i8> %a, <vscale x 2 x i1> %m, i32 %vl)
63  ret <vscale x 2 x i64> %v
64}
65
66define <vscale x 2 x i64> @vzext_nxv2i8_nxv2i64_unmasked(<vscale x 2 x i8> %a, i32 zeroext %vl) {
67; CHECK-LABEL: vzext_nxv2i8_nxv2i64_unmasked:
68; CHECK:       # %bb.0:
69; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, ma
70; CHECK-NEXT:    vzext.vf8 v10, v8
71; CHECK-NEXT:    vmv.v.v v8, v10
72; CHECK-NEXT:    ret
73  %v = call <vscale x 2 x i64> @llvm.vp.zext.nxv2i64.nxv2i8(<vscale x 2 x i8> %a, <vscale x 2 x i1> splat (i1 true), i32 %vl)
74  ret <vscale x 2 x i64> %v
75}
76
77declare <vscale x 2 x i32> @llvm.vp.zext.nxv2i32.nxv2i16(<vscale x 2 x i16>, <vscale x 2 x i1>, i32)
78
79define <vscale x 2 x i32> @vzext_nxv2i16_nxv2i32(<vscale x 2 x i16> %a, <vscale x 2 x i1> %m, i32 zeroext %vl) {
80; CHECK-LABEL: vzext_nxv2i16_nxv2i32:
81; CHECK:       # %bb.0:
82; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma
83; CHECK-NEXT:    vzext.vf2 v9, v8, v0.t
84; CHECK-NEXT:    vmv.v.v v8, v9
85; CHECK-NEXT:    ret
86  %v = call <vscale x 2 x i32> @llvm.vp.zext.nxv2i32.nxv2i16(<vscale x 2 x i16> %a, <vscale x 2 x i1> %m, i32 %vl)
87  ret <vscale x 2 x i32> %v
88}
89
90define <vscale x 2 x i32> @vzext_nxv2i16_nxv2i32_unmasked(<vscale x 2 x i16> %a, i32 zeroext %vl) {
91; CHECK-LABEL: vzext_nxv2i16_nxv2i32_unmasked:
92; CHECK:       # %bb.0:
93; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma
94; CHECK-NEXT:    vzext.vf2 v9, v8
95; CHECK-NEXT:    vmv.v.v v8, v9
96; CHECK-NEXT:    ret
97  %v = call <vscale x 2 x i32> @llvm.vp.zext.nxv2i32.nxv2i16(<vscale x 2 x i16> %a, <vscale x 2 x i1> splat (i1 true), i32 %vl)
98  ret <vscale x 2 x i32> %v
99}
100
101declare <vscale x 2 x i64> @llvm.vp.zext.nxv2i64.nxv2i16(<vscale x 2 x i16>, <vscale x 2 x i1>, i32)
102
103define <vscale x 2 x i64> @vzext_nxv2i16_nxv2i64(<vscale x 2 x i16> %a, <vscale x 2 x i1> %m, i32 zeroext %vl) {
104; CHECK-LABEL: vzext_nxv2i16_nxv2i64:
105; CHECK:       # %bb.0:
106; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, ma
107; CHECK-NEXT:    vzext.vf4 v10, v8, v0.t
108; CHECK-NEXT:    vmv.v.v v8, v10
109; CHECK-NEXT:    ret
110  %v = call <vscale x 2 x i64> @llvm.vp.zext.nxv2i64.nxv2i16(<vscale x 2 x i16> %a, <vscale x 2 x i1> %m, i32 %vl)
111  ret <vscale x 2 x i64> %v
112}
113
114define <vscale x 2 x i64> @vzext_nxv2i16_nxv2i64_unmasked(<vscale x 2 x i16> %a, i32 zeroext %vl) {
115; CHECK-LABEL: vzext_nxv2i16_nxv2i64_unmasked:
116; CHECK:       # %bb.0:
117; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, ma
118; CHECK-NEXT:    vzext.vf4 v10, v8
119; CHECK-NEXT:    vmv.v.v v8, v10
120; CHECK-NEXT:    ret
121  %v = call <vscale x 2 x i64> @llvm.vp.zext.nxv2i64.nxv2i16(<vscale x 2 x i16> %a, <vscale x 2 x i1> splat (i1 true), i32 %vl)
122  ret <vscale x 2 x i64> %v
123}
124
125declare <vscale x 2 x i64> @llvm.vp.zext.nxv2i64.nxv2i32(<vscale x 2 x i32>, <vscale x 2 x i1>, i32)
126
127define <vscale x 2 x i64> @vzext_nxv2i32_nxv2i64(<vscale x 2 x i32> %a, <vscale x 2 x i1> %m, i32 zeroext %vl) {
128; CHECK-LABEL: vzext_nxv2i32_nxv2i64:
129; CHECK:       # %bb.0:
130; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, ma
131; CHECK-NEXT:    vzext.vf2 v10, v8, v0.t
132; CHECK-NEXT:    vmv.v.v v8, v10
133; CHECK-NEXT:    ret
134  %v = call <vscale x 2 x i64> @llvm.vp.zext.nxv2i64.nxv2i32(<vscale x 2 x i32> %a, <vscale x 2 x i1> %m, i32 %vl)
135  ret <vscale x 2 x i64> %v
136}
137
138define <vscale x 2 x i64> @vzext_nxv2i32_nxv2i64_unmasked(<vscale x 2 x i32> %a, i32 zeroext %vl) {
139; CHECK-LABEL: vzext_nxv2i32_nxv2i64_unmasked:
140; CHECK:       # %bb.0:
141; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, ma
142; CHECK-NEXT:    vzext.vf2 v10, v8
143; CHECK-NEXT:    vmv.v.v v8, v10
144; CHECK-NEXT:    ret
145  %v = call <vscale x 2 x i64> @llvm.vp.zext.nxv2i64.nxv2i32(<vscale x 2 x i32> %a, <vscale x 2 x i1> splat (i1 true), i32 %vl)
146  ret <vscale x 2 x i64> %v
147}
148
149declare <vscale x 32 x i32> @llvm.vp.zext.nxv32i32.nxv32i8(<vscale x 32 x i8>, <vscale x 32 x i1>, i32)
150
151define <vscale x 32 x i32> @vzext_nxv32i8_nxv32i32(<vscale x 32 x i8> %a, <vscale x 32 x i1> %m, i32 zeroext %vl) {
152; CHECK-LABEL: vzext_nxv32i8_nxv32i32:
153; CHECK:       # %bb.0:
154; CHECK-NEXT:    vsetvli a1, zero, e8, mf2, ta, ma
155; CHECK-NEXT:    vmv1r.v v12, v0
156; CHECK-NEXT:    csrr a1, vlenb
157; CHECK-NEXT:    srli a2, a1, 2
158; CHECK-NEXT:    slli a1, a1, 1
159; CHECK-NEXT:    vslidedown.vx v0, v0, a2
160; CHECK-NEXT:    sub a2, a0, a1
161; CHECK-NEXT:    sltu a3, a0, a2
162; CHECK-NEXT:    addi a3, a3, -1
163; CHECK-NEXT:    and a2, a3, a2
164; CHECK-NEXT:    vsetvli zero, a2, e32, m8, ta, ma
165; CHECK-NEXT:    vzext.vf4 v16, v10, v0.t
166; CHECK-NEXT:    bltu a0, a1, .LBB12_2
167; CHECK-NEXT:  # %bb.1:
168; CHECK-NEXT:    mv a0, a1
169; CHECK-NEXT:  .LBB12_2:
170; CHECK-NEXT:    vmv1r.v v0, v12
171; CHECK-NEXT:    vsetvli zero, a0, e32, m8, ta, ma
172; CHECK-NEXT:    vzext.vf4 v24, v8, v0.t
173; CHECK-NEXT:    vmv.v.v v8, v24
174; CHECK-NEXT:    ret
175  %v = call <vscale x 32 x i32> @llvm.vp.zext.nxv32i32.nxv32i8(<vscale x 32 x i8> %a, <vscale x 32 x i1> %m, i32 %vl)
176  ret <vscale x 32 x i32> %v
177}
178
179define <vscale x 32 x i32> @vzext_nxv32i8_nxv32i32_unmasked(<vscale x 32 x i8> %a, i32 zeroext %vl) {
180; CHECK-LABEL: vzext_nxv32i8_nxv32i32_unmasked:
181; CHECK:       # %bb.0:
182; CHECK-NEXT:    csrr a1, vlenb
183; CHECK-NEXT:    slli a1, a1, 1
184; CHECK-NEXT:    sub a2, a0, a1
185; CHECK-NEXT:    sltu a3, a0, a2
186; CHECK-NEXT:    addi a3, a3, -1
187; CHECK-NEXT:    and a2, a3, a2
188; CHECK-NEXT:    vsetvli zero, a2, e32, m8, ta, ma
189; CHECK-NEXT:    vzext.vf4 v16, v10
190; CHECK-NEXT:    bltu a0, a1, .LBB13_2
191; CHECK-NEXT:  # %bb.1:
192; CHECK-NEXT:    mv a0, a1
193; CHECK-NEXT:  .LBB13_2:
194; CHECK-NEXT:    vsetvli zero, a0, e32, m8, ta, ma
195; CHECK-NEXT:    vzext.vf4 v24, v8
196; CHECK-NEXT:    vmv.v.v v8, v24
197; CHECK-NEXT:    ret
198  %v = call <vscale x 32 x i32> @llvm.vp.zext.nxv32i32.nxv32i8(<vscale x 32 x i8> %a, <vscale x 32 x i1> splat (i1 true), i32 %vl)
199  ret <vscale x 32 x i32> %v
200}
201