xref: /llvm-project/llvm/test/CodeGen/RISCV/rvv/vwsll-sdnode.ll (revision d85f1054fbb04c5299848bf81aa350442f9a56c7) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s
3; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s
4; RUN: llc -mtriple=riscv32 -mattr=+v,+zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB,RV32ZVBB
5; RUN: llc -mtriple=riscv64 -mattr=+v,+zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB,RV64ZVBB
6
7; ==============================================================================
8; i32 -> i64
9; ==============================================================================
10
11define <vscale x 2 x i64> @vwsll_vv_nxv2i64_sext(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b) {
12; CHECK-LABEL: vwsll_vv_nxv2i64_sext:
13; CHECK:       # %bb.0:
14; CHECK-NEXT:    vsetvli a0, zero, e64, m2, ta, ma
15; CHECK-NEXT:    vzext.vf2 v10, v8
16; CHECK-NEXT:    vsext.vf2 v12, v9
17; CHECK-NEXT:    vsll.vv v8, v10, v12
18; CHECK-NEXT:    ret
19;
20; CHECK-ZVBB-LABEL: vwsll_vv_nxv2i64_sext:
21; CHECK-ZVBB:       # %bb.0:
22; CHECK-ZVBB-NEXT:    vsetvli a0, zero, e32, m1, ta, ma
23; CHECK-ZVBB-NEXT:    vwsll.vv v10, v8, v9
24; CHECK-ZVBB-NEXT:    vmv2r.v v8, v10
25; CHECK-ZVBB-NEXT:    ret
26  %x = zext <vscale x 2 x i32> %a to <vscale x 2 x i64>
27  %y = sext <vscale x 2 x i32> %b to <vscale x 2 x i64>
28  %z = shl <vscale x 2 x i64> %x, %y
29  ret <vscale x 2 x i64> %z
30}
31
32define <vscale x 2 x i64> @vwsll_vv_nxv2i64_zext(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b) {
33; CHECK-LABEL: vwsll_vv_nxv2i64_zext:
34; CHECK:       # %bb.0:
35; CHECK-NEXT:    vsetvli a0, zero, e64, m2, ta, ma
36; CHECK-NEXT:    vzext.vf2 v10, v8
37; CHECK-NEXT:    vzext.vf2 v12, v9
38; CHECK-NEXT:    vsll.vv v8, v10, v12
39; CHECK-NEXT:    ret
40;
41; CHECK-ZVBB-LABEL: vwsll_vv_nxv2i64_zext:
42; CHECK-ZVBB:       # %bb.0:
43; CHECK-ZVBB-NEXT:    vsetvli a0, zero, e32, m1, ta, ma
44; CHECK-ZVBB-NEXT:    vwsll.vv v10, v8, v9
45; CHECK-ZVBB-NEXT:    vmv2r.v v8, v10
46; CHECK-ZVBB-NEXT:    ret
47  %x = zext <vscale x 2 x i32> %a to <vscale x 2 x i64>
48  %y = zext <vscale x 2 x i32> %b to <vscale x 2 x i64>
49  %z = shl <vscale x 2 x i64> %x, %y
50  ret <vscale x 2 x i64> %z
51}
52
53define <vscale x 2 x i64> @vwsll_vx_i64_nxv2i64(<vscale x 2 x i32> %a, i64 %b) {
54; CHECK-LABEL: vwsll_vx_i64_nxv2i64:
55; CHECK:       # %bb.0:
56; CHECK-NEXT:    vsetvli a1, zero, e64, m2, ta, ma
57; CHECK-NEXT:    vzext.vf2 v10, v8
58; CHECK-NEXT:    vsll.vx v8, v10, a0
59; CHECK-NEXT:    ret
60;
61; CHECK-ZVBB-LABEL: vwsll_vx_i64_nxv2i64:
62; CHECK-ZVBB:       # %bb.0:
63; CHECK-ZVBB-NEXT:    vsetvli a1, zero, e32, m1, ta, ma
64; CHECK-ZVBB-NEXT:    vwsll.vx v10, v8, a0
65; CHECK-ZVBB-NEXT:    vmv2r.v v8, v10
66; CHECK-ZVBB-NEXT:    ret
67  %head = insertelement <vscale x 2 x i64> poison, i64 %b, i32 0
68  %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
69  %x = zext <vscale x 2 x i32> %a to <vscale x 2 x i64>
70  %z = shl <vscale x 2 x i64> %x, %splat
71  ret <vscale x 2 x i64> %z
72}
73
74define <vscale x 2 x i64> @vwsll_vx_i32_nxv2i64_sext(<vscale x 2 x i32> %a, i32 %b) {
75; CHECK-LABEL: vwsll_vx_i32_nxv2i64_sext:
76; CHECK:       # %bb.0:
77; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, ma
78; CHECK-NEXT:    vmv.v.x v9, a0
79; CHECK-NEXT:    vsetvli zero, zero, e64, m2, ta, ma
80; CHECK-NEXT:    vzext.vf2 v10, v8
81; CHECK-NEXT:    vsext.vf2 v12, v9
82; CHECK-NEXT:    vsll.vv v8, v10, v12
83; CHECK-NEXT:    ret
84;
85; CHECK-ZVBB-LABEL: vwsll_vx_i32_nxv2i64_sext:
86; CHECK-ZVBB:       # %bb.0:
87; CHECK-ZVBB-NEXT:    vsetvli a1, zero, e32, m1, ta, ma
88; CHECK-ZVBB-NEXT:    vwsll.vx v10, v8, a0
89; CHECK-ZVBB-NEXT:    vmv2r.v v8, v10
90; CHECK-ZVBB-NEXT:    ret
91  %head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0
92  %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer
93  %x = zext <vscale x 2 x i32> %a to <vscale x 2 x i64>
94  %y = sext <vscale x 2 x i32> %splat to <vscale x 2 x i64>
95  %z = shl <vscale x 2 x i64> %x, %y
96  ret <vscale x 2 x i64> %z
97}
98
99define <vscale x 2 x i64> @vwsll_vx_i32_nxv2i64_zext(<vscale x 2 x i32> %a, i32 %b) {
100; CHECK-LABEL: vwsll_vx_i32_nxv2i64_zext:
101; CHECK:       # %bb.0:
102; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, ma
103; CHECK-NEXT:    vmv.v.x v9, a0
104; CHECK-NEXT:    vsetvli zero, zero, e64, m2, ta, ma
105; CHECK-NEXT:    vzext.vf2 v10, v8
106; CHECK-NEXT:    vzext.vf2 v12, v9
107; CHECK-NEXT:    vsll.vv v8, v10, v12
108; CHECK-NEXT:    ret
109;
110; CHECK-ZVBB-LABEL: vwsll_vx_i32_nxv2i64_zext:
111; CHECK-ZVBB:       # %bb.0:
112; CHECK-ZVBB-NEXT:    vsetvli a1, zero, e32, m1, ta, ma
113; CHECK-ZVBB-NEXT:    vwsll.vx v10, v8, a0
114; CHECK-ZVBB-NEXT:    vmv2r.v v8, v10
115; CHECK-ZVBB-NEXT:    ret
116  %head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0
117  %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer
118  %x = zext <vscale x 2 x i32> %a to <vscale x 2 x i64>
119  %y = zext <vscale x 2 x i32> %splat to <vscale x 2 x i64>
120  %z = shl <vscale x 2 x i64> %x, %y
121  ret <vscale x 2 x i64> %z
122}
123
124define <vscale x 2 x i64> @vwsll_vx_i16_nxv2i64_sext(<vscale x 2 x i32> %a, i16 %b) {
125; CHECK-LABEL: vwsll_vx_i16_nxv2i64_sext:
126; CHECK:       # %bb.0:
127; CHECK-NEXT:    vsetvli a1, zero, e16, mf2, ta, ma
128; CHECK-NEXT:    vmv.v.x v9, a0
129; CHECK-NEXT:    vsetvli zero, zero, e64, m2, ta, ma
130; CHECK-NEXT:    vzext.vf2 v10, v8
131; CHECK-NEXT:    vsext.vf4 v12, v9
132; CHECK-NEXT:    vsll.vv v8, v10, v12
133; CHECK-NEXT:    ret
134;
135; CHECK-ZVBB-LABEL: vwsll_vx_i16_nxv2i64_sext:
136; CHECK-ZVBB:       # %bb.0:
137; CHECK-ZVBB-NEXT:    vsetvli a1, zero, e32, m1, ta, ma
138; CHECK-ZVBB-NEXT:    vwsll.vx v10, v8, a0
139; CHECK-ZVBB-NEXT:    vmv2r.v v8, v10
140; CHECK-ZVBB-NEXT:    ret
141  %head = insertelement <vscale x 2 x i16> poison, i16 %b, i32 0
142  %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer
143  %x = zext <vscale x 2 x i32> %a to <vscale x 2 x i64>
144  %y = sext <vscale x 2 x i16> %splat to <vscale x 2 x i64>
145  %z = shl <vscale x 2 x i64> %x, %y
146  ret <vscale x 2 x i64> %z
147}
148
149define <vscale x 2 x i64> @vwsll_vx_i16_nxv2i64_zext(<vscale x 2 x i32> %a, i16 %b) {
150; CHECK-LABEL: vwsll_vx_i16_nxv2i64_zext:
151; CHECK:       # %bb.0:
152; CHECK-NEXT:    vsetvli a1, zero, e16, mf2, ta, ma
153; CHECK-NEXT:    vmv.v.x v9, a0
154; CHECK-NEXT:    vsetvli zero, zero, e64, m2, ta, ma
155; CHECK-NEXT:    vzext.vf2 v10, v8
156; CHECK-NEXT:    vzext.vf4 v12, v9
157; CHECK-NEXT:    vsll.vv v8, v10, v12
158; CHECK-NEXT:    ret
159;
160; CHECK-ZVBB-LABEL: vwsll_vx_i16_nxv2i64_zext:
161; CHECK-ZVBB:       # %bb.0:
162; CHECK-ZVBB-NEXT:    vsetvli a1, zero, e32, m1, ta, ma
163; CHECK-ZVBB-NEXT:    vwsll.vx v10, v8, a0
164; CHECK-ZVBB-NEXT:    vmv2r.v v8, v10
165; CHECK-ZVBB-NEXT:    ret
166  %head = insertelement <vscale x 2 x i16> poison, i16 %b, i32 0
167  %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer
168  %x = zext <vscale x 2 x i32> %a to <vscale x 2 x i64>
169  %y = zext <vscale x 2 x i16> %splat to <vscale x 2 x i64>
170  %z = shl <vscale x 2 x i64> %x, %y
171  ret <vscale x 2 x i64> %z
172}
173
174define <vscale x 2 x i64> @vwsll_vx_i8_nxv2i64_sext(<vscale x 2 x i32> %a, i8 %b) {
175; CHECK-LABEL: vwsll_vx_i8_nxv2i64_sext:
176; CHECK:       # %bb.0:
177; CHECK-NEXT:    vsetvli a1, zero, e8, mf4, ta, ma
178; CHECK-NEXT:    vmv.v.x v9, a0
179; CHECK-NEXT:    vsetvli zero, zero, e64, m2, ta, ma
180; CHECK-NEXT:    vzext.vf2 v10, v8
181; CHECK-NEXT:    vsext.vf8 v12, v9
182; CHECK-NEXT:    vsll.vv v8, v10, v12
183; CHECK-NEXT:    ret
184;
185; CHECK-ZVBB-LABEL: vwsll_vx_i8_nxv2i64_sext:
186; CHECK-ZVBB:       # %bb.0:
187; CHECK-ZVBB-NEXT:    vsetvli a1, zero, e32, m1, ta, ma
188; CHECK-ZVBB-NEXT:    vwsll.vx v10, v8, a0
189; CHECK-ZVBB-NEXT:    vmv2r.v v8, v10
190; CHECK-ZVBB-NEXT:    ret
191  %head = insertelement <vscale x 2 x i8> poison, i8 %b, i32 0
192  %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> poison, <vscale x 2 x i32> zeroinitializer
193  %x = zext <vscale x 2 x i32> %a to <vscale x 2 x i64>
194  %y = sext <vscale x 2 x i8> %splat to <vscale x 2 x i64>
195  %z = shl <vscale x 2 x i64> %x, %y
196  ret <vscale x 2 x i64> %z
197}
198
199define <vscale x 2 x i64> @vwsll_vx_i8_nxv2i64_zext(<vscale x 2 x i32> %a, i8 %b) {
200; CHECK-LABEL: vwsll_vx_i8_nxv2i64_zext:
201; CHECK:       # %bb.0:
202; CHECK-NEXT:    vsetvli a1, zero, e8, mf4, ta, ma
203; CHECK-NEXT:    vmv.v.x v9, a0
204; CHECK-NEXT:    vsetvli zero, zero, e64, m2, ta, ma
205; CHECK-NEXT:    vzext.vf2 v10, v8
206; CHECK-NEXT:    vzext.vf8 v12, v9
207; CHECK-NEXT:    vsll.vv v8, v10, v12
208; CHECK-NEXT:    ret
209;
210; CHECK-ZVBB-LABEL: vwsll_vx_i8_nxv2i64_zext:
211; CHECK-ZVBB:       # %bb.0:
212; CHECK-ZVBB-NEXT:    vsetvli a1, zero, e32, m1, ta, ma
213; CHECK-ZVBB-NEXT:    vwsll.vx v10, v8, a0
214; CHECK-ZVBB-NEXT:    vmv2r.v v8, v10
215; CHECK-ZVBB-NEXT:    ret
216  %head = insertelement <vscale x 2 x i8> poison, i8 %b, i32 0
217  %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> poison, <vscale x 2 x i32> zeroinitializer
218  %x = zext <vscale x 2 x i32> %a to <vscale x 2 x i64>
219  %y = zext <vscale x 2 x i8> %splat to <vscale x 2 x i64>
220  %z = shl <vscale x 2 x i64> %x, %y
221  ret <vscale x 2 x i64> %z
222}
223
224define <vscale x 2 x i64> @vwsll_vi_nxv2i64(<vscale x 2 x i32> %a) {
225; CHECK-LABEL: vwsll_vi_nxv2i64:
226; CHECK:       # %bb.0:
227; CHECK-NEXT:    vsetvli a0, zero, e64, m2, ta, ma
228; CHECK-NEXT:    vzext.vf2 v10, v8
229; CHECK-NEXT:    vsll.vi v8, v10, 2
230; CHECK-NEXT:    ret
231;
232; CHECK-ZVBB-LABEL: vwsll_vi_nxv2i64:
233; CHECK-ZVBB:       # %bb.0:
234; CHECK-ZVBB-NEXT:    vsetvli a0, zero, e32, m1, ta, ma
235; CHECK-ZVBB-NEXT:    vwsll.vi v10, v8, 2
236; CHECK-ZVBB-NEXT:    vmv2r.v v8, v10
237; CHECK-ZVBB-NEXT:    ret
238  %x = zext <vscale x 2 x i32> %a to <vscale x 2 x i64>
239  %z = shl <vscale x 2 x i64> %x, splat (i64 2)
240  ret <vscale x 2 x i64> %z
241}
242
243; ==============================================================================
244; i16 -> i32
245; ==============================================================================
246
247define <vscale x 4 x i32> @vwsll_vv_nxv4i32_sext(<vscale x 4 x i16> %a, <vscale x 4 x i16> %b) {
248; CHECK-LABEL: vwsll_vv_nxv4i32_sext:
249; CHECK:       # %bb.0:
250; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, ma
251; CHECK-NEXT:    vzext.vf2 v10, v8
252; CHECK-NEXT:    vsext.vf2 v12, v9
253; CHECK-NEXT:    vsll.vv v8, v10, v12
254; CHECK-NEXT:    ret
255;
256; CHECK-ZVBB-LABEL: vwsll_vv_nxv4i32_sext:
257; CHECK-ZVBB:       # %bb.0:
258; CHECK-ZVBB-NEXT:    vsetvli a0, zero, e16, m1, ta, ma
259; CHECK-ZVBB-NEXT:    vwsll.vv v10, v8, v9
260; CHECK-ZVBB-NEXT:    vmv2r.v v8, v10
261; CHECK-ZVBB-NEXT:    ret
262  %x = zext <vscale x 4 x i16> %a to <vscale x 4 x i32>
263  %y = sext <vscale x 4 x i16> %b to <vscale x 4 x i32>
264  %z = shl <vscale x 4 x i32> %x, %y
265  ret <vscale x 4 x i32> %z
266}
267
268define <vscale x 4 x i32> @vwsll_vv_nxv4i32_zext(<vscale x 4 x i16> %a, <vscale x 4 x i16> %b) {
269; CHECK-LABEL: vwsll_vv_nxv4i32_zext:
270; CHECK:       # %bb.0:
271; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, ma
272; CHECK-NEXT:    vzext.vf2 v10, v8
273; CHECK-NEXT:    vzext.vf2 v12, v9
274; CHECK-NEXT:    vsll.vv v8, v10, v12
275; CHECK-NEXT:    ret
276;
277; CHECK-ZVBB-LABEL: vwsll_vv_nxv4i32_zext:
278; CHECK-ZVBB:       # %bb.0:
279; CHECK-ZVBB-NEXT:    vsetvli a0, zero, e16, m1, ta, ma
280; CHECK-ZVBB-NEXT:    vwsll.vv v10, v8, v9
281; CHECK-ZVBB-NEXT:    vmv2r.v v8, v10
282; CHECK-ZVBB-NEXT:    ret
283  %x = zext <vscale x 4 x i16> %a to <vscale x 4 x i32>
284  %y = zext <vscale x 4 x i16> %b to <vscale x 4 x i32>
285  %z = shl <vscale x 4 x i32> %x, %y
286  ret <vscale x 4 x i32> %z
287}
288
289define <vscale x 4 x i32> @vwsll_vx_i64_nxv4i32(<vscale x 4 x i16> %a, i64 %b) {
290; CHECK-LABEL: vwsll_vx_i64_nxv4i32:
291; CHECK:       # %bb.0:
292; CHECK-NEXT:    vsetvli a1, zero, e32, m2, ta, ma
293; CHECK-NEXT:    vzext.vf2 v10, v8
294; CHECK-NEXT:    vsll.vx v8, v10, a0
295; CHECK-NEXT:    ret
296;
297; CHECK-ZVBB-LABEL: vwsll_vx_i64_nxv4i32:
298; CHECK-ZVBB:       # %bb.0:
299; CHECK-ZVBB-NEXT:    vsetvli a1, zero, e16, m1, ta, ma
300; CHECK-ZVBB-NEXT:    vwsll.vx v10, v8, a0
301; CHECK-ZVBB-NEXT:    vmv2r.v v8, v10
302; CHECK-ZVBB-NEXT:    ret
303  %head = insertelement <vscale x 4 x i64> poison, i64 %b, i32 0
304  %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer
305  %x = zext <vscale x 4 x i16> %a to <vscale x 4 x i32>
306  %y = trunc <vscale x 4 x i64> %splat to <vscale x 4 x i32>
307  %z = shl <vscale x 4 x i32> %x, %y
308  ret <vscale x 4 x i32> %z
309}
310
311define <vscale x 4 x i32> @vwsll_vx_i32_nxv4i32(<vscale x 4 x i16> %a, i32 %b) {
312; CHECK-LABEL: vwsll_vx_i32_nxv4i32:
313; CHECK:       # %bb.0:
314; CHECK-NEXT:    vsetvli a1, zero, e32, m2, ta, ma
315; CHECK-NEXT:    vzext.vf2 v10, v8
316; CHECK-NEXT:    vsll.vx v8, v10, a0
317; CHECK-NEXT:    ret
318;
319; CHECK-ZVBB-LABEL: vwsll_vx_i32_nxv4i32:
320; CHECK-ZVBB:       # %bb.0:
321; CHECK-ZVBB-NEXT:    vsetvli a1, zero, e16, m1, ta, ma
322; CHECK-ZVBB-NEXT:    vwsll.vx v10, v8, a0
323; CHECK-ZVBB-NEXT:    vmv2r.v v8, v10
324; CHECK-ZVBB-NEXT:    ret
325  %head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0
326  %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
327  %x = zext <vscale x 4 x i16> %a to <vscale x 4 x i32>
328  %z = shl <vscale x 4 x i32> %x, %splat
329  ret <vscale x 4 x i32> %z
330}
331
332define <vscale x 4 x i32> @vwsll_vx_i16_nxv4i32_sext(<vscale x 4 x i16> %a, i16 %b) {
333; CHECK-LABEL: vwsll_vx_i16_nxv4i32_sext:
334; CHECK:       # %bb.0:
335; CHECK-NEXT:    vsetvli a1, zero, e16, m1, ta, ma
336; CHECK-NEXT:    vmv.v.x v9, a0
337; CHECK-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
338; CHECK-NEXT:    vzext.vf2 v10, v8
339; CHECK-NEXT:    vsext.vf2 v12, v9
340; CHECK-NEXT:    vsll.vv v8, v10, v12
341; CHECK-NEXT:    ret
342;
343; CHECK-ZVBB-LABEL: vwsll_vx_i16_nxv4i32_sext:
344; CHECK-ZVBB:       # %bb.0:
345; CHECK-ZVBB-NEXT:    vsetvli a1, zero, e16, m1, ta, ma
346; CHECK-ZVBB-NEXT:    vwsll.vx v10, v8, a0
347; CHECK-ZVBB-NEXT:    vmv2r.v v8, v10
348; CHECK-ZVBB-NEXT:    ret
349  %head = insertelement <vscale x 4 x i16> poison, i16 %b, i32 0
350  %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> poison, <vscale x 4 x i32> zeroinitializer
351  %x = zext <vscale x 4 x i16> %a to <vscale x 4 x i32>
352  %y = sext <vscale x 4 x i16> %splat to <vscale x 4 x i32>
353  %z = shl <vscale x 4 x i32> %x, %y
354  ret <vscale x 4 x i32> %z
355}
356
357define <vscale x 4 x i32> @vwsll_vx_i16_nxv4i32_zext(<vscale x 4 x i16> %a, i16 %b) {
358; CHECK-LABEL: vwsll_vx_i16_nxv4i32_zext:
359; CHECK:       # %bb.0:
360; CHECK-NEXT:    vsetvli a1, zero, e16, m1, ta, ma
361; CHECK-NEXT:    vmv.v.x v9, a0
362; CHECK-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
363; CHECK-NEXT:    vzext.vf2 v10, v8
364; CHECK-NEXT:    vzext.vf2 v12, v9
365; CHECK-NEXT:    vsll.vv v8, v10, v12
366; CHECK-NEXT:    ret
367;
368; CHECK-ZVBB-LABEL: vwsll_vx_i16_nxv4i32_zext:
369; CHECK-ZVBB:       # %bb.0:
370; CHECK-ZVBB-NEXT:    vsetvli a1, zero, e16, m1, ta, ma
371; CHECK-ZVBB-NEXT:    vwsll.vx v10, v8, a0
372; CHECK-ZVBB-NEXT:    vmv2r.v v8, v10
373; CHECK-ZVBB-NEXT:    ret
374  %head = insertelement <vscale x 4 x i16> poison, i16 %b, i32 0
375  %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> poison, <vscale x 4 x i32> zeroinitializer
376  %x = zext <vscale x 4 x i16> %a to <vscale x 4 x i32>
377  %y = zext <vscale x 4 x i16> %splat to <vscale x 4 x i32>
378  %z = shl <vscale x 4 x i32> %x, %y
379  ret <vscale x 4 x i32> %z
380}
381
382define <vscale x 4 x i32> @vwsll_vx_i8_nxv4i32_sext(<vscale x 4 x i16> %a, i8 %b) {
383; CHECK-LABEL: vwsll_vx_i8_nxv4i32_sext:
384; CHECK:       # %bb.0:
385; CHECK-NEXT:    vsetvli a1, zero, e8, mf2, ta, ma
386; CHECK-NEXT:    vmv.v.x v9, a0
387; CHECK-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
388; CHECK-NEXT:    vzext.vf2 v10, v8
389; CHECK-NEXT:    vsext.vf4 v12, v9
390; CHECK-NEXT:    vsll.vv v8, v10, v12
391; CHECK-NEXT:    ret
392;
393; CHECK-ZVBB-LABEL: vwsll_vx_i8_nxv4i32_sext:
394; CHECK-ZVBB:       # %bb.0:
395; CHECK-ZVBB-NEXT:    vsetvli a1, zero, e16, m1, ta, ma
396; CHECK-ZVBB-NEXT:    vwsll.vx v10, v8, a0
397; CHECK-ZVBB-NEXT:    vmv2r.v v8, v10
398; CHECK-ZVBB-NEXT:    ret
399  %head = insertelement <vscale x 4 x i8> poison, i8 %b, i32 0
400  %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> poison, <vscale x 4 x i32> zeroinitializer
401  %x = zext <vscale x 4 x i16> %a to <vscale x 4 x i32>
402  %y = sext <vscale x 4 x i8> %splat to <vscale x 4 x i32>
403  %z = shl <vscale x 4 x i32> %x, %y
404  ret <vscale x 4 x i32> %z
405}
406
407define <vscale x 4 x i32> @vwsll_vx_i8_nxv4i32_zext(<vscale x 4 x i16> %a, i8 %b) {
408; CHECK-LABEL: vwsll_vx_i8_nxv4i32_zext:
409; CHECK:       # %bb.0:
410; CHECK-NEXT:    vsetvli a1, zero, e8, mf2, ta, ma
411; CHECK-NEXT:    vmv.v.x v9, a0
412; CHECK-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
413; CHECK-NEXT:    vzext.vf2 v10, v8
414; CHECK-NEXT:    vzext.vf4 v12, v9
415; CHECK-NEXT:    vsll.vv v8, v10, v12
416; CHECK-NEXT:    ret
417;
418; CHECK-ZVBB-LABEL: vwsll_vx_i8_nxv4i32_zext:
419; CHECK-ZVBB:       # %bb.0:
420; CHECK-ZVBB-NEXT:    vsetvli a1, zero, e16, m1, ta, ma
421; CHECK-ZVBB-NEXT:    vwsll.vx v10, v8, a0
422; CHECK-ZVBB-NEXT:    vmv2r.v v8, v10
423; CHECK-ZVBB-NEXT:    ret
424  %head = insertelement <vscale x 4 x i8> poison, i8 %b, i32 0
425  %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> poison, <vscale x 4 x i32> zeroinitializer
426  %x = zext <vscale x 4 x i16> %a to <vscale x 4 x i32>
427  %y = zext <vscale x 4 x i8> %splat to <vscale x 4 x i32>
428  %z = shl <vscale x 4 x i32> %x, %y
429  ret <vscale x 4 x i32> %z
430}
431
432define <vscale x 4 x i32> @vwsll_vi_nxv4i32(<vscale x 4 x i16> %a) {
433; CHECK-LABEL: vwsll_vi_nxv4i32:
434; CHECK:       # %bb.0:
435; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, ma
436; CHECK-NEXT:    vzext.vf2 v10, v8
437; CHECK-NEXT:    vsll.vi v8, v10, 2
438; CHECK-NEXT:    ret
439;
440; CHECK-ZVBB-LABEL: vwsll_vi_nxv4i32:
441; CHECK-ZVBB:       # %bb.0:
442; CHECK-ZVBB-NEXT:    vsetvli a0, zero, e16, m1, ta, ma
443; CHECK-ZVBB-NEXT:    vwsll.vi v10, v8, 2
444; CHECK-ZVBB-NEXT:    vmv2r.v v8, v10
445; CHECK-ZVBB-NEXT:    ret
446  %x = zext <vscale x 4 x i16> %a to <vscale x 4 x i32>
447  %z = shl <vscale x 4 x i32> %x, splat (i32 2)
448  ret <vscale x 4 x i32> %z
449}
450
451; ==============================================================================
452; i8 -> i16
453; ==============================================================================
454
455define <vscale x 8 x i16> @vwsll_vv_nxv8i16_sext(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b) {
456; CHECK-LABEL: vwsll_vv_nxv8i16_sext:
457; CHECK:       # %bb.0:
458; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, ma
459; CHECK-NEXT:    vzext.vf2 v10, v8
460; CHECK-NEXT:    vsext.vf2 v12, v9
461; CHECK-NEXT:    vsll.vv v8, v10, v12
462; CHECK-NEXT:    ret
463;
464; CHECK-ZVBB-LABEL: vwsll_vv_nxv8i16_sext:
465; CHECK-ZVBB:       # %bb.0:
466; CHECK-ZVBB-NEXT:    vsetvli a0, zero, e8, m1, ta, ma
467; CHECK-ZVBB-NEXT:    vwsll.vv v10, v8, v9
468; CHECK-ZVBB-NEXT:    vmv2r.v v8, v10
469; CHECK-ZVBB-NEXT:    ret
470  %x = zext <vscale x 8 x i8> %a to <vscale x 8 x i16>
471  %y = sext <vscale x 8 x i8> %b to <vscale x 8 x i16>
472  %z = shl <vscale x 8 x i16> %x, %y
473  ret <vscale x 8 x i16> %z
474}
475
476define <vscale x 8 x i16> @vwsll_vv_nxv8i16_zext(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b) {
477; CHECK-LABEL: vwsll_vv_nxv8i16_zext:
478; CHECK:       # %bb.0:
479; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, ma
480; CHECK-NEXT:    vzext.vf2 v10, v8
481; CHECK-NEXT:    vzext.vf2 v12, v9
482; CHECK-NEXT:    vsll.vv v8, v10, v12
483; CHECK-NEXT:    ret
484;
485; CHECK-ZVBB-LABEL: vwsll_vv_nxv8i16_zext:
486; CHECK-ZVBB:       # %bb.0:
487; CHECK-ZVBB-NEXT:    vsetvli a0, zero, e8, m1, ta, ma
488; CHECK-ZVBB-NEXT:    vwsll.vv v10, v8, v9
489; CHECK-ZVBB-NEXT:    vmv2r.v v8, v10
490; CHECK-ZVBB-NEXT:    ret
491  %x = zext <vscale x 8 x i8> %a to <vscale x 8 x i16>
492  %y = zext <vscale x 8 x i8> %b to <vscale x 8 x i16>
493  %z = shl <vscale x 8 x i16> %x, %y
494  ret <vscale x 8 x i16> %z
495}
496
497define <vscale x 8 x i16> @vwsll_vx_i64_nxv8i16(<vscale x 8 x i8> %a, i64 %b) {
498; CHECK-LABEL: vwsll_vx_i64_nxv8i16:
499; CHECK:       # %bb.0:
500; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, ma
501; CHECK-NEXT:    vzext.vf2 v10, v8
502; CHECK-NEXT:    vsll.vx v8, v10, a0
503; CHECK-NEXT:    ret
504;
505; CHECK-ZVBB-LABEL: vwsll_vx_i64_nxv8i16:
506; CHECK-ZVBB:       # %bb.0:
507; CHECK-ZVBB-NEXT:    vsetvli a1, zero, e8, m1, ta, ma
508; CHECK-ZVBB-NEXT:    vwsll.vx v10, v8, a0
509; CHECK-ZVBB-NEXT:    vmv2r.v v8, v10
510; CHECK-ZVBB-NEXT:    ret
511  %head = insertelement <vscale x 4 x i64> poison, i64 %b, i32 0
512  %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> poison, <vscale x 8 x i32> zeroinitializer
513  %x = zext <vscale x 8 x i8> %a to <vscale x 8 x i16>
514  %y = trunc <vscale x 8 x i64> %splat to <vscale x 8 x i16>
515  %z = shl <vscale x 8 x i16> %x, %y
516  ret <vscale x 8 x i16> %z
517}
518
519define <vscale x 8 x i16> @vwsll_vx_i32_nxv8i16(<vscale x 8 x i8> %a, i32 %b) {
520; CHECK-LABEL: vwsll_vx_i32_nxv8i16:
521; CHECK:       # %bb.0:
522; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, ma
523; CHECK-NEXT:    vzext.vf2 v10, v8
524; CHECK-NEXT:    vsll.vx v8, v10, a0
525; CHECK-NEXT:    ret
526;
527; CHECK-ZVBB-LABEL: vwsll_vx_i32_nxv8i16:
528; CHECK-ZVBB:       # %bb.0:
529; CHECK-ZVBB-NEXT:    vsetvli a1, zero, e8, m1, ta, ma
530; CHECK-ZVBB-NEXT:    vwsll.vx v10, v8, a0
531; CHECK-ZVBB-NEXT:    vmv2r.v v8, v10
532; CHECK-ZVBB-NEXT:    ret
533  %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
534  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
535  %x = zext <vscale x 8 x i8> %a to <vscale x 8 x i16>
536  %y = trunc <vscale x 8 x i32> %splat to <vscale x 8 x i16>
537  %z = shl <vscale x 8 x i16> %x, %y
538  ret <vscale x 8 x i16> %z
539}
540
541define <vscale x 8 x i16> @vwsll_vx_i16_nxv8i16(<vscale x 8 x i8> %a, i16 %b) {
542; CHECK-LABEL: vwsll_vx_i16_nxv8i16:
543; CHECK:       # %bb.0:
544; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, ma
545; CHECK-NEXT:    vzext.vf2 v10, v8
546; CHECK-NEXT:    vsll.vx v8, v10, a0
547; CHECK-NEXT:    ret
548;
549; CHECK-ZVBB-LABEL: vwsll_vx_i16_nxv8i16:
550; CHECK-ZVBB:       # %bb.0:
551; CHECK-ZVBB-NEXT:    vsetvli a1, zero, e8, m1, ta, ma
552; CHECK-ZVBB-NEXT:    vwsll.vx v10, v8, a0
553; CHECK-ZVBB-NEXT:    vmv2r.v v8, v10
554; CHECK-ZVBB-NEXT:    ret
555  %head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0
556  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
557  %x = zext <vscale x 8 x i8> %a to <vscale x 8 x i16>
558  %z = shl <vscale x 8 x i16> %x, %splat
559  ret <vscale x 8 x i16> %z
560}
561
562define <vscale x 8 x i16> @vwsll_vx_i8_nxv8i16_sext(<vscale x 8 x i8> %a, i8 %b) {
563; CHECK-LABEL: vwsll_vx_i8_nxv8i16_sext:
564; CHECK:       # %bb.0:
565; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, ma
566; CHECK-NEXT:    vmv.v.x v9, a0
567; CHECK-NEXT:    vsetvli zero, zero, e16, m2, ta, ma
568; CHECK-NEXT:    vzext.vf2 v10, v8
569; CHECK-NEXT:    vsext.vf2 v12, v9
570; CHECK-NEXT:    vsll.vv v8, v10, v12
571; CHECK-NEXT:    ret
572;
573; CHECK-ZVBB-LABEL: vwsll_vx_i8_nxv8i16_sext:
574; CHECK-ZVBB:       # %bb.0:
575; CHECK-ZVBB-NEXT:    vsetvli a1, zero, e8, m1, ta, ma
576; CHECK-ZVBB-NEXT:    vwsll.vx v10, v8, a0
577; CHECK-ZVBB-NEXT:    vmv2r.v v8, v10
578; CHECK-ZVBB-NEXT:    ret
579  %head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0
580  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
581  %x = zext <vscale x 8 x i8> %a to <vscale x 8 x i16>
582  %y = sext <vscale x 8 x i8> %splat to <vscale x 8 x i16>
583  %z = shl <vscale x 8 x i16> %x, %y
584  ret <vscale x 8 x i16> %z
585}
586
587define <vscale x 8 x i16> @vwsll_vx_i8_nxv8i16_zext(<vscale x 8 x i8> %a, i8 %b) {
588; CHECK-LABEL: vwsll_vx_i8_nxv8i16_zext:
589; CHECK:       # %bb.0:
590; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, ma
591; CHECK-NEXT:    vmv.v.x v9, a0
592; CHECK-NEXT:    vsetvli zero, zero, e16, m2, ta, ma
593; CHECK-NEXT:    vzext.vf2 v10, v8
594; CHECK-NEXT:    vzext.vf2 v12, v9
595; CHECK-NEXT:    vsll.vv v8, v10, v12
596; CHECK-NEXT:    ret
597;
598; CHECK-ZVBB-LABEL: vwsll_vx_i8_nxv8i16_zext:
599; CHECK-ZVBB:       # %bb.0:
600; CHECK-ZVBB-NEXT:    vsetvli a1, zero, e8, m1, ta, ma
601; CHECK-ZVBB-NEXT:    vwsll.vx v10, v8, a0
602; CHECK-ZVBB-NEXT:    vmv2r.v v8, v10
603; CHECK-ZVBB-NEXT:    ret
604  %head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0
605  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
606  %x = zext <vscale x 8 x i8> %a to <vscale x 8 x i16>
607  %y = zext <vscale x 8 x i8> %splat to <vscale x 8 x i16>
608  %z = shl <vscale x 8 x i16> %x, %y
609  ret <vscale x 8 x i16> %z
610}
611
612define <vscale x 8 x i16> @vwsll_vi_nxv8i16(<vscale x 8 x i8> %a) {
613; CHECK-LABEL: vwsll_vi_nxv8i16:
614; CHECK:       # %bb.0:
615; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, ma
616; CHECK-NEXT:    vzext.vf2 v10, v8
617; CHECK-NEXT:    vsll.vi v8, v10, 2
618; CHECK-NEXT:    ret
619;
620; CHECK-ZVBB-LABEL: vwsll_vi_nxv8i16:
621; CHECK-ZVBB:       # %bb.0:
622; CHECK-ZVBB-NEXT:    vsetvli a0, zero, e8, m1, ta, ma
623; CHECK-ZVBB-NEXT:    vwsll.vi v10, v8, 2
624; CHECK-ZVBB-NEXT:    vmv2r.v v8, v10
625; CHECK-ZVBB-NEXT:    ret
626  %x = zext <vscale x 8 x i8> %a to <vscale x 8 x i16>
627  %z = shl <vscale x 8 x i16> %x, splat (i16 2)
628  ret <vscale x 8 x i16> %z
629}
630
631; ==============================================================================
632; i8 -> i64
633; ==============================================================================
634
635define <vscale x 2 x i64> @vwsll_vv_nxv2i64_nxv2i8_sext(<vscale x 2 x i8> %a, <vscale x 2 x i8> %b) {
636; CHECK-LABEL: vwsll_vv_nxv2i64_nxv2i8_sext:
637; CHECK:       # %bb.0:
638; CHECK-NEXT:    vsetvli a0, zero, e64, m2, ta, ma
639; CHECK-NEXT:    vzext.vf8 v10, v8
640; CHECK-NEXT:    vsext.vf8 v12, v9
641; CHECK-NEXT:    vsll.vv v8, v10, v12
642; CHECK-NEXT:    ret
643;
644; CHECK-ZVBB-LABEL: vwsll_vv_nxv2i64_nxv2i8_sext:
645; CHECK-ZVBB:       # %bb.0:
646; CHECK-ZVBB-NEXT:    vsetvli a0, zero, e64, m2, ta, ma
647; CHECK-ZVBB-NEXT:    vzext.vf8 v10, v8
648; CHECK-ZVBB-NEXT:    vsext.vf8 v12, v9
649; CHECK-ZVBB-NEXT:    vsll.vv v8, v10, v12
650; CHECK-ZVBB-NEXT:    ret
651  %x = zext <vscale x 2 x i8> %a to <vscale x 2 x i64>
652  %y = sext <vscale x 2 x i8> %b to <vscale x 2 x i64>
653  %z = shl <vscale x 2 x i64> %x, %y
654  ret <vscale x 2 x i64> %z
655}
656
657define <vscale x 2 x i64> @vwsll_vv_nxv2i64_nxv2i8_zext(<vscale x 2 x i8> %a, <vscale x 2 x i8> %b) {
658; CHECK-LABEL: vwsll_vv_nxv2i64_nxv2i8_zext:
659; CHECK:       # %bb.0:
660; CHECK-NEXT:    vsetvli a0, zero, e64, m2, ta, ma
661; CHECK-NEXT:    vzext.vf8 v10, v8
662; CHECK-NEXT:    vzext.vf8 v12, v9
663; CHECK-NEXT:    vsll.vv v8, v10, v12
664; CHECK-NEXT:    ret
665;
666; CHECK-ZVBB-LABEL: vwsll_vv_nxv2i64_nxv2i8_zext:
667; CHECK-ZVBB:       # %bb.0:
668; CHECK-ZVBB-NEXT:    vsetvli a0, zero, e32, m1, ta, ma
669; CHECK-ZVBB-NEXT:    vzext.vf4 v10, v8
670; CHECK-ZVBB-NEXT:    vzext.vf4 v11, v9
671; CHECK-ZVBB-NEXT:    vwsll.vv v8, v10, v11
672; CHECK-ZVBB-NEXT:    ret
673  %x = zext <vscale x 2 x i8> %a to <vscale x 2 x i64>
674  %y = zext <vscale x 2 x i8> %b to <vscale x 2 x i64>
675  %z = shl <vscale x 2 x i64> %x, %y
676  ret <vscale x 2 x i64> %z
677}
678
679define <vscale x 2 x i64> @vwsll_vx_i64_nxv2i64_nxv2i8(<vscale x 2 x i8> %a, i64 %b) {
680; CHECK-LABEL: vwsll_vx_i64_nxv2i64_nxv2i8:
681; CHECK:       # %bb.0:
682; CHECK-NEXT:    vsetvli a1, zero, e64, m2, ta, ma
683; CHECK-NEXT:    vzext.vf8 v10, v8
684; CHECK-NEXT:    vsll.vx v8, v10, a0
685; CHECK-NEXT:    ret
686;
687; CHECK-ZVBB-LABEL: vwsll_vx_i64_nxv2i64_nxv2i8:
688; CHECK-ZVBB:       # %bb.0:
689; CHECK-ZVBB-NEXT:    vsetvli a1, zero, e64, m2, ta, ma
690; CHECK-ZVBB-NEXT:    vzext.vf8 v10, v8
691; CHECK-ZVBB-NEXT:    vsll.vx v8, v10, a0
692; CHECK-ZVBB-NEXT:    ret
693  %head = insertelement <vscale x 2 x i64> poison, i64 %b, i32 0
694  %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
695  %x = zext <vscale x 2 x i8> %a to <vscale x 2 x i64>
696  %z = shl <vscale x 2 x i64> %x, %splat
697  ret <vscale x 2 x i64> %z
698}
699
700define <vscale x 2 x i64> @vwsll_vx_i32_nxv2i64_nxv2i8_sext(<vscale x 2 x i8> %a, i32 %b) {
701; CHECK-LABEL: vwsll_vx_i32_nxv2i64_nxv2i8_sext:
702; CHECK:       # %bb.0:
703; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, ma
704; CHECK-NEXT:    vmv.v.x v9, a0
705; CHECK-NEXT:    vsetvli zero, zero, e64, m2, ta, ma
706; CHECK-NEXT:    vzext.vf8 v10, v8
707; CHECK-NEXT:    vsext.vf2 v12, v9
708; CHECK-NEXT:    vsll.vv v8, v10, v12
709; CHECK-NEXT:    ret
710;
711; CHECK-ZVBB-LABEL: vwsll_vx_i32_nxv2i64_nxv2i8_sext:
712; CHECK-ZVBB:       # %bb.0:
713; CHECK-ZVBB-NEXT:    vsetvli a1, zero, e32, m1, ta, ma
714; CHECK-ZVBB-NEXT:    vmv.v.x v9, a0
715; CHECK-ZVBB-NEXT:    vsetvli zero, zero, e64, m2, ta, ma
716; CHECK-ZVBB-NEXT:    vzext.vf8 v10, v8
717; CHECK-ZVBB-NEXT:    vsext.vf2 v12, v9
718; CHECK-ZVBB-NEXT:    vsll.vv v8, v10, v12
719; CHECK-ZVBB-NEXT:    ret
720  %head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0
721  %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer
722  %x = zext <vscale x 2 x i8> %a to <vscale x 2 x i64>
723  %y = sext <vscale x 2 x i32> %splat to <vscale x 2 x i64>
724  %z = shl <vscale x 2 x i64> %x, %y
725  ret <vscale x 2 x i64> %z
726}
727
728define <vscale x 2 x i64> @vwsll_vx_i32_nxv2i64_nxv2i8_zext(<vscale x 2 x i8> %a, i32 %b) {
729; CHECK-LABEL: vwsll_vx_i32_nxv2i64_nxv2i8_zext:
730; CHECK:       # %bb.0:
731; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, ma
732; CHECK-NEXT:    vmv.v.x v9, a0
733; CHECK-NEXT:    vsetvli zero, zero, e64, m2, ta, ma
734; CHECK-NEXT:    vzext.vf8 v10, v8
735; CHECK-NEXT:    vzext.vf2 v12, v9
736; CHECK-NEXT:    vsll.vv v8, v10, v12
737; CHECK-NEXT:    ret
738;
739; CHECK-ZVBB-LABEL: vwsll_vx_i32_nxv2i64_nxv2i8_zext:
740; CHECK-ZVBB:       # %bb.0:
741; CHECK-ZVBB-NEXT:    vsetvli a1, zero, e32, m1, ta, ma
742; CHECK-ZVBB-NEXT:    vzext.vf4 v10, v8
743; CHECK-ZVBB-NEXT:    vwsll.vx v8, v10, a0
744; CHECK-ZVBB-NEXT:    ret
745  %head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0
746  %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer
747  %x = zext <vscale x 2 x i8> %a to <vscale x 2 x i64>
748  %y = zext <vscale x 2 x i32> %splat to <vscale x 2 x i64>
749  %z = shl <vscale x 2 x i64> %x, %y
750  ret <vscale x 2 x i64> %z
751}
752
753define <vscale x 2 x i64> @vwsll_vx_i16_nxv2i64_nxv2i8_sext(<vscale x 2 x i8> %a, i16 %b) {
754; CHECK-LABEL: vwsll_vx_i16_nxv2i64_nxv2i8_sext:
755; CHECK:       # %bb.0:
756; CHECK-NEXT:    vsetvli a1, zero, e16, mf2, ta, ma
757; CHECK-NEXT:    vmv.v.x v9, a0
758; CHECK-NEXT:    vsetvli zero, zero, e64, m2, ta, ma
759; CHECK-NEXT:    vzext.vf8 v10, v8
760; CHECK-NEXT:    vsext.vf4 v12, v9
761; CHECK-NEXT:    vsll.vv v8, v10, v12
762; CHECK-NEXT:    ret
763;
764; CHECK-ZVBB-LABEL: vwsll_vx_i16_nxv2i64_nxv2i8_sext:
765; CHECK-ZVBB:       # %bb.0:
766; CHECK-ZVBB-NEXT:    vsetvli a1, zero, e16, mf2, ta, ma
767; CHECK-ZVBB-NEXT:    vmv.v.x v9, a0
768; CHECK-ZVBB-NEXT:    vsetvli zero, zero, e64, m2, ta, ma
769; CHECK-ZVBB-NEXT:    vzext.vf8 v10, v8
770; CHECK-ZVBB-NEXT:    vsext.vf4 v12, v9
771; CHECK-ZVBB-NEXT:    vsll.vv v8, v10, v12
772; CHECK-ZVBB-NEXT:    ret
773  %head = insertelement <vscale x 2 x i16> poison, i16 %b, i32 0
774  %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer
775  %x = zext <vscale x 2 x i8> %a to <vscale x 2 x i64>
776  %y = sext <vscale x 2 x i16> %splat to <vscale x 2 x i64>
777  %z = shl <vscale x 2 x i64> %x, %y
778  ret <vscale x 2 x i64> %z
779}
780
781define <vscale x 2 x i64> @vwsll_vx_i16_nxv2i64_nxv2i8_zext(<vscale x 2 x i8> %a, i16 %b) {
782; CHECK-LABEL: vwsll_vx_i16_nxv2i64_nxv2i8_zext:
783; CHECK:       # %bb.0:
784; CHECK-NEXT:    vsetvli a1, zero, e16, mf2, ta, ma
785; CHECK-NEXT:    vmv.v.x v9, a0
786; CHECK-NEXT:    vsetvli zero, zero, e64, m2, ta, ma
787; CHECK-NEXT:    vzext.vf8 v10, v8
788; CHECK-NEXT:    vzext.vf4 v12, v9
789; CHECK-NEXT:    vsll.vv v8, v10, v12
790; CHECK-NEXT:    ret
791;
792; CHECK-ZVBB-LABEL: vwsll_vx_i16_nxv2i64_nxv2i8_zext:
793; CHECK-ZVBB:       # %bb.0:
794; CHECK-ZVBB-NEXT:    vsetvli a1, zero, e32, m1, ta, ma
795; CHECK-ZVBB-NEXT:    vzext.vf4 v10, v8
796; CHECK-ZVBB-NEXT:    vwsll.vx v8, v10, a0
797; CHECK-ZVBB-NEXT:    ret
798  %head = insertelement <vscale x 2 x i16> poison, i16 %b, i32 0
799  %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer
800  %x = zext <vscale x 2 x i8> %a to <vscale x 2 x i64>
801  %y = zext <vscale x 2 x i16> %splat to <vscale x 2 x i64>
802  %z = shl <vscale x 2 x i64> %x, %y
803  ret <vscale x 2 x i64> %z
804}
805
806define <vscale x 2 x i64> @vwsll_vx_i8_nxv2i64_nxv2i8_sext(<vscale x 2 x i8> %a, i8 %b) {
807; CHECK-LABEL: vwsll_vx_i8_nxv2i64_nxv2i8_sext:
808; CHECK:       # %bb.0:
809; CHECK-NEXT:    vsetvli a1, zero, e8, mf4, ta, ma
810; CHECK-NEXT:    vmv.v.x v9, a0
811; CHECK-NEXT:    vsetvli zero, zero, e64, m2, ta, ma
812; CHECK-NEXT:    vzext.vf8 v10, v8
813; CHECK-NEXT:    vsext.vf8 v12, v9
814; CHECK-NEXT:    vsll.vv v8, v10, v12
815; CHECK-NEXT:    ret
816;
817; CHECK-ZVBB-LABEL: vwsll_vx_i8_nxv2i64_nxv2i8_sext:
818; CHECK-ZVBB:       # %bb.0:
819; CHECK-ZVBB-NEXT:    vsetvli a1, zero, e8, mf4, ta, ma
820; CHECK-ZVBB-NEXT:    vmv.v.x v9, a0
821; CHECK-ZVBB-NEXT:    vsetvli zero, zero, e64, m2, ta, ma
822; CHECK-ZVBB-NEXT:    vzext.vf8 v10, v8
823; CHECK-ZVBB-NEXT:    vsext.vf8 v12, v9
824; CHECK-ZVBB-NEXT:    vsll.vv v8, v10, v12
825; CHECK-ZVBB-NEXT:    ret
826  %head = insertelement <vscale x 2 x i8> poison, i8 %b, i32 0
827  %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> poison, <vscale x 2 x i32> zeroinitializer
828  %x = zext <vscale x 2 x i8> %a to <vscale x 2 x i64>
829  %y = sext <vscale x 2 x i8> %splat to <vscale x 2 x i64>
830  %z = shl <vscale x 2 x i64> %x, %y
831  ret <vscale x 2 x i64> %z
832}
833
834define <vscale x 2 x i64> @vwsll_vx_i8_nxv2i64_nxv2i8_zext(<vscale x 2 x i8> %a, i8 %b) {
835; CHECK-LABEL: vwsll_vx_i8_nxv2i64_nxv2i8_zext:
836; CHECK:       # %bb.0:
837; CHECK-NEXT:    vsetvli a1, zero, e8, mf4, ta, ma
838; CHECK-NEXT:    vmv.v.x v9, a0
839; CHECK-NEXT:    vsetvli zero, zero, e64, m2, ta, ma
840; CHECK-NEXT:    vzext.vf8 v10, v8
841; CHECK-NEXT:    vzext.vf8 v12, v9
842; CHECK-NEXT:    vsll.vv v8, v10, v12
843; CHECK-NEXT:    ret
844;
845; CHECK-ZVBB-LABEL: vwsll_vx_i8_nxv2i64_nxv2i8_zext:
846; CHECK-ZVBB:       # %bb.0:
847; CHECK-ZVBB-NEXT:    vsetvli a1, zero, e32, m1, ta, ma
848; CHECK-ZVBB-NEXT:    vzext.vf4 v10, v8
849; CHECK-ZVBB-NEXT:    vwsll.vx v8, v10, a0
850; CHECK-ZVBB-NEXT:    ret
851  %head = insertelement <vscale x 2 x i8> poison, i8 %b, i32 0
852  %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> poison, <vscale x 2 x i32> zeroinitializer
853  %x = zext <vscale x 2 x i8> %a to <vscale x 2 x i64>
854  %y = zext <vscale x 2 x i8> %splat to <vscale x 2 x i64>
855  %z = shl <vscale x 2 x i64> %x, %y
856  ret <vscale x 2 x i64> %z
857}
858
859define <vscale x 2 x i64> @vwsll_vi_nxv2i64_nxv2i8(<vscale x 2 x i8> %a) {
860; CHECK-LABEL: vwsll_vi_nxv2i64_nxv2i8:
861; CHECK:       # %bb.0:
862; CHECK-NEXT:    vsetvli a0, zero, e64, m2, ta, ma
863; CHECK-NEXT:    vzext.vf8 v10, v8
864; CHECK-NEXT:    vsll.vi v8, v10, 2
865; CHECK-NEXT:    ret
866;
867; CHECK-ZVBB-LABEL: vwsll_vi_nxv2i64_nxv2i8:
868; CHECK-ZVBB:       # %bb.0:
869; CHECK-ZVBB-NEXT:    vsetvli a0, zero, e32, m1, ta, ma
870; CHECK-ZVBB-NEXT:    vzext.vf4 v10, v8
871; CHECK-ZVBB-NEXT:    vwsll.vi v8, v10, 2
872; CHECK-ZVBB-NEXT:    ret
873  %x = zext <vscale x 2 x i8> %a to <vscale x 2 x i64>
874  %z = shl <vscale x 2 x i64> %x, splat (i64 2)
875  ret <vscale x 2 x i64> %z
876}
877;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
878; RV32ZVBB: {{.*}}
879; RV64ZVBB: {{.*}}
880