xref: /llvm-project/llvm/test/CodeGen/RISCV/rvv/vwmul.ll (revision f2bdc29f3e5dd4d8d65081094f8afc789d58706a) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v \
3; RUN:   -verify-machineinstrs | FileCheck %s
4; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v \
5; RUN:   -verify-machineinstrs | FileCheck %s
6
7declare <vscale x 1 x i16> @llvm.riscv.vwmul.nxv1i16.nxv1i8.nxv1i8(
8  <vscale x 1 x i16>,
9  <vscale x 1 x i8>,
10  <vscale x 1 x i8>,
11  iXLen);
12
13define <vscale x 1 x i16> @intrinsic_vwmul_vv_nxv1i16_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, iXLen %2) nounwind {
14; CHECK-LABEL: intrinsic_vwmul_vv_nxv1i16_nxv1i8_nxv1i8:
15; CHECK:       # %bb.0: # %entry
16; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, ma
17; CHECK-NEXT:    vwmul.vv v10, v8, v9
18; CHECK-NEXT:    vmv1r.v v8, v10
19; CHECK-NEXT:    ret
20entry:
21  %a = call <vscale x 1 x i16> @llvm.riscv.vwmul.nxv1i16.nxv1i8.nxv1i8(
22    <vscale x 1 x i16> undef,
23    <vscale x 1 x i8> %0,
24    <vscale x 1 x i8> %1,
25    iXLen %2)
26
27  ret <vscale x 1 x i16> %a
28}
29
30declare <vscale x 1 x i16> @llvm.riscv.vwmul.mask.nxv1i16.nxv1i8.nxv1i8(
31  <vscale x 1 x i16>,
32  <vscale x 1 x i8>,
33  <vscale x 1 x i8>,
34  <vscale x 1 x i1>,
35  iXLen,
36  iXLen);
37
38define <vscale x 1 x i16> @intrinsic_vwmul_mask_vv_nxv1i16_nxv1i8_nxv1i8(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
39; CHECK-LABEL: intrinsic_vwmul_mask_vv_nxv1i16_nxv1i8_nxv1i8:
40; CHECK:       # %bb.0: # %entry
41; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, mu
42; CHECK-NEXT:    vwmul.vv v8, v9, v10, v0.t
43; CHECK-NEXT:    ret
44entry:
45  %a = call <vscale x 1 x i16> @llvm.riscv.vwmul.mask.nxv1i16.nxv1i8.nxv1i8(
46    <vscale x 1 x i16> %0,
47    <vscale x 1 x i8> %1,
48    <vscale x 1 x i8> %2,
49    <vscale x 1 x i1> %3,
50    iXLen %4, iXLen 1)
51
52  ret <vscale x 1 x i16> %a
53}
54
55declare <vscale x 2 x i16> @llvm.riscv.vwmul.nxv2i16.nxv2i8.nxv2i8(
56  <vscale x 2 x i16>,
57  <vscale x 2 x i8>,
58  <vscale x 2 x i8>,
59  iXLen);
60
61define <vscale x 2 x i16> @intrinsic_vwmul_vv_nxv2i16_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, iXLen %2) nounwind {
62; CHECK-LABEL: intrinsic_vwmul_vv_nxv2i16_nxv2i8_nxv2i8:
63; CHECK:       # %bb.0: # %entry
64; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, ma
65; CHECK-NEXT:    vwmul.vv v10, v8, v9
66; CHECK-NEXT:    vmv1r.v v8, v10
67; CHECK-NEXT:    ret
68entry:
69  %a = call <vscale x 2 x i16> @llvm.riscv.vwmul.nxv2i16.nxv2i8.nxv2i8(
70    <vscale x 2 x i16> undef,
71    <vscale x 2 x i8> %0,
72    <vscale x 2 x i8> %1,
73    iXLen %2)
74
75  ret <vscale x 2 x i16> %a
76}
77
78declare <vscale x 2 x i16> @llvm.riscv.vwmul.mask.nxv2i16.nxv2i8.nxv2i8(
79  <vscale x 2 x i16>,
80  <vscale x 2 x i8>,
81  <vscale x 2 x i8>,
82  <vscale x 2 x i1>,
83  iXLen,
84  iXLen);
85
86define <vscale x 2 x i16> @intrinsic_vwmul_mask_vv_nxv2i16_nxv2i8_nxv2i8(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
87; CHECK-LABEL: intrinsic_vwmul_mask_vv_nxv2i16_nxv2i8_nxv2i8:
88; CHECK:       # %bb.0: # %entry
89; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, mu
90; CHECK-NEXT:    vwmul.vv v8, v9, v10, v0.t
91; CHECK-NEXT:    ret
92entry:
93  %a = call <vscale x 2 x i16> @llvm.riscv.vwmul.mask.nxv2i16.nxv2i8.nxv2i8(
94    <vscale x 2 x i16> %0,
95    <vscale x 2 x i8> %1,
96    <vscale x 2 x i8> %2,
97    <vscale x 2 x i1> %3,
98    iXLen %4, iXLen 1)
99
100  ret <vscale x 2 x i16> %a
101}
102
103declare <vscale x 4 x i16> @llvm.riscv.vwmul.nxv4i16.nxv4i8.nxv4i8(
104  <vscale x 4 x i16>,
105  <vscale x 4 x i8>,
106  <vscale x 4 x i8>,
107  iXLen);
108
109define <vscale x 4 x i16> @intrinsic_vwmul_vv_nxv4i16_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, iXLen %2) nounwind {
110; CHECK-LABEL: intrinsic_vwmul_vv_nxv4i16_nxv4i8_nxv4i8:
111; CHECK:       # %bb.0: # %entry
112; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma
113; CHECK-NEXT:    vwmul.vv v10, v8, v9
114; CHECK-NEXT:    vmv1r.v v8, v10
115; CHECK-NEXT:    ret
116entry:
117  %a = call <vscale x 4 x i16> @llvm.riscv.vwmul.nxv4i16.nxv4i8.nxv4i8(
118    <vscale x 4 x i16> undef,
119    <vscale x 4 x i8> %0,
120    <vscale x 4 x i8> %1,
121    iXLen %2)
122
123  ret <vscale x 4 x i16> %a
124}
125
126declare <vscale x 4 x i16> @llvm.riscv.vwmul.mask.nxv4i16.nxv4i8.nxv4i8(
127  <vscale x 4 x i16>,
128  <vscale x 4 x i8>,
129  <vscale x 4 x i8>,
130  <vscale x 4 x i1>,
131  iXLen,
132  iXLen);
133
134define <vscale x 4 x i16> @intrinsic_vwmul_mask_vv_nxv4i16_nxv4i8_nxv4i8(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
135; CHECK-LABEL: intrinsic_vwmul_mask_vv_nxv4i16_nxv4i8_nxv4i8:
136; CHECK:       # %bb.0: # %entry
137; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, mu
138; CHECK-NEXT:    vwmul.vv v8, v9, v10, v0.t
139; CHECK-NEXT:    ret
140entry:
141  %a = call <vscale x 4 x i16> @llvm.riscv.vwmul.mask.nxv4i16.nxv4i8.nxv4i8(
142    <vscale x 4 x i16> %0,
143    <vscale x 4 x i8> %1,
144    <vscale x 4 x i8> %2,
145    <vscale x 4 x i1> %3,
146    iXLen %4, iXLen 1)
147
148  ret <vscale x 4 x i16> %a
149}
150
151declare <vscale x 8 x i16> @llvm.riscv.vwmul.nxv8i16.nxv8i8.nxv8i8(
152  <vscale x 8 x i16>,
153  <vscale x 8 x i8>,
154  <vscale x 8 x i8>,
155  iXLen);
156
157define <vscale x 8 x i16> @intrinsic_vwmul_vv_nxv8i16_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, iXLen %2) nounwind {
158; CHECK-LABEL: intrinsic_vwmul_vv_nxv8i16_nxv8i8_nxv8i8:
159; CHECK:       # %bb.0: # %entry
160; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, ma
161; CHECK-NEXT:    vwmul.vv v10, v8, v9
162; CHECK-NEXT:    vmv2r.v v8, v10
163; CHECK-NEXT:    ret
164entry:
165  %a = call <vscale x 8 x i16> @llvm.riscv.vwmul.nxv8i16.nxv8i8.nxv8i8(
166    <vscale x 8 x i16> undef,
167    <vscale x 8 x i8> %0,
168    <vscale x 8 x i8> %1,
169    iXLen %2)
170
171  ret <vscale x 8 x i16> %a
172}
173
174declare <vscale x 8 x i16> @llvm.riscv.vwmul.mask.nxv8i16.nxv8i8.nxv8i8(
175  <vscale x 8 x i16>,
176  <vscale x 8 x i8>,
177  <vscale x 8 x i8>,
178  <vscale x 8 x i1>,
179  iXLen,
180  iXLen);
181
182define <vscale x 8 x i16> @intrinsic_vwmul_mask_vv_nxv8i16_nxv8i8_nxv8i8(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
183; CHECK-LABEL: intrinsic_vwmul_mask_vv_nxv8i16_nxv8i8_nxv8i8:
184; CHECK:       # %bb.0: # %entry
185; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, mu
186; CHECK-NEXT:    vwmul.vv v8, v10, v11, v0.t
187; CHECK-NEXT:    ret
188entry:
189  %a = call <vscale x 8 x i16> @llvm.riscv.vwmul.mask.nxv8i16.nxv8i8.nxv8i8(
190    <vscale x 8 x i16> %0,
191    <vscale x 8 x i8> %1,
192    <vscale x 8 x i8> %2,
193    <vscale x 8 x i1> %3,
194    iXLen %4, iXLen 1)
195
196  ret <vscale x 8 x i16> %a
197}
198
199declare <vscale x 16 x i16> @llvm.riscv.vwmul.nxv16i16.nxv16i8.nxv16i8(
200  <vscale x 16 x i16>,
201  <vscale x 16 x i8>,
202  <vscale x 16 x i8>,
203  iXLen);
204
205define <vscale x 16 x i16> @intrinsic_vwmul_vv_nxv16i16_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, iXLen %2) nounwind {
206; CHECK-LABEL: intrinsic_vwmul_vv_nxv16i16_nxv16i8_nxv16i8:
207; CHECK:       # %bb.0: # %entry
208; CHECK-NEXT:    vsetvli zero, a0, e8, m2, ta, ma
209; CHECK-NEXT:    vwmul.vv v12, v8, v10
210; CHECK-NEXT:    vmv4r.v v8, v12
211; CHECK-NEXT:    ret
212entry:
213  %a = call <vscale x 16 x i16> @llvm.riscv.vwmul.nxv16i16.nxv16i8.nxv16i8(
214    <vscale x 16 x i16> undef,
215    <vscale x 16 x i8> %0,
216    <vscale x 16 x i8> %1,
217    iXLen %2)
218
219  ret <vscale x 16 x i16> %a
220}
221
222declare <vscale x 16 x i16> @llvm.riscv.vwmul.mask.nxv16i16.nxv16i8.nxv16i8(
223  <vscale x 16 x i16>,
224  <vscale x 16 x i8>,
225  <vscale x 16 x i8>,
226  <vscale x 16 x i1>,
227  iXLen,
228  iXLen);
229
230define <vscale x 16 x i16> @intrinsic_vwmul_mask_vv_nxv16i16_nxv16i8_nxv16i8(<vscale x 16 x i16> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
231; CHECK-LABEL: intrinsic_vwmul_mask_vv_nxv16i16_nxv16i8_nxv16i8:
232; CHECK:       # %bb.0: # %entry
233; CHECK-NEXT:    vsetvli zero, a0, e8, m2, ta, mu
234; CHECK-NEXT:    vwmul.vv v8, v12, v14, v0.t
235; CHECK-NEXT:    ret
236entry:
237  %a = call <vscale x 16 x i16> @llvm.riscv.vwmul.mask.nxv16i16.nxv16i8.nxv16i8(
238    <vscale x 16 x i16> %0,
239    <vscale x 16 x i8> %1,
240    <vscale x 16 x i8> %2,
241    <vscale x 16 x i1> %3,
242    iXLen %4, iXLen 1)
243
244  ret <vscale x 16 x i16> %a
245}
246
247declare <vscale x 32 x i16> @llvm.riscv.vwmul.nxv32i16.nxv32i8.nxv32i8(
248  <vscale x 32 x i16>,
249  <vscale x 32 x i8>,
250  <vscale x 32 x i8>,
251  iXLen);
252
253define <vscale x 32 x i16> @intrinsic_vwmul_vv_nxv32i16_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, iXLen %2) nounwind {
254; CHECK-LABEL: intrinsic_vwmul_vv_nxv32i16_nxv32i8_nxv32i8:
255; CHECK:       # %bb.0: # %entry
256; CHECK-NEXT:    vsetvli zero, a0, e8, m4, ta, ma
257; CHECK-NEXT:    vwmul.vv v16, v8, v12
258; CHECK-NEXT:    vmv8r.v v8, v16
259; CHECK-NEXT:    ret
260entry:
261  %a = call <vscale x 32 x i16> @llvm.riscv.vwmul.nxv32i16.nxv32i8.nxv32i8(
262    <vscale x 32 x i16> undef,
263    <vscale x 32 x i8> %0,
264    <vscale x 32 x i8> %1,
265    iXLen %2)
266
267  ret <vscale x 32 x i16> %a
268}
269
270declare <vscale x 32 x i16> @llvm.riscv.vwmul.mask.nxv32i16.nxv32i8.nxv32i8(
271  <vscale x 32 x i16>,
272  <vscale x 32 x i8>,
273  <vscale x 32 x i8>,
274  <vscale x 32 x i1>,
275  iXLen,
276  iXLen);
277
278define <vscale x 32 x i16> @intrinsic_vwmul_mask_vv_nxv32i16_nxv32i8_nxv32i8(<vscale x 32 x i16> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {
279; CHECK-LABEL: intrinsic_vwmul_mask_vv_nxv32i16_nxv32i8_nxv32i8:
280; CHECK:       # %bb.0: # %entry
281; CHECK-NEXT:    vsetvli zero, a0, e8, m4, ta, mu
282; CHECK-NEXT:    vwmul.vv v8, v16, v20, v0.t
283; CHECK-NEXT:    ret
284entry:
285  %a = call <vscale x 32 x i16> @llvm.riscv.vwmul.mask.nxv32i16.nxv32i8.nxv32i8(
286    <vscale x 32 x i16> %0,
287    <vscale x 32 x i8> %1,
288    <vscale x 32 x i8> %2,
289    <vscale x 32 x i1> %3,
290    iXLen %4, iXLen 1)
291
292  ret <vscale x 32 x i16> %a
293}
294
295declare <vscale x 1 x i32> @llvm.riscv.vwmul.nxv1i32.nxv1i16.nxv1i16(
296  <vscale x 1 x i32>,
297  <vscale x 1 x i16>,
298  <vscale x 1 x i16>,
299  iXLen);
300
301define <vscale x 1 x i32> @intrinsic_vwmul_vv_nxv1i32_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, iXLen %2) nounwind {
302; CHECK-LABEL: intrinsic_vwmul_vv_nxv1i32_nxv1i16_nxv1i16:
303; CHECK:       # %bb.0: # %entry
304; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma
305; CHECK-NEXT:    vwmul.vv v10, v8, v9
306; CHECK-NEXT:    vmv1r.v v8, v10
307; CHECK-NEXT:    ret
308entry:
309  %a = call <vscale x 1 x i32> @llvm.riscv.vwmul.nxv1i32.nxv1i16.nxv1i16(
310    <vscale x 1 x i32> undef,
311    <vscale x 1 x i16> %0,
312    <vscale x 1 x i16> %1,
313    iXLen %2)
314
315  ret <vscale x 1 x i32> %a
316}
317
318declare <vscale x 1 x i32> @llvm.riscv.vwmul.mask.nxv1i32.nxv1i16.nxv1i16(
319  <vscale x 1 x i32>,
320  <vscale x 1 x i16>,
321  <vscale x 1 x i16>,
322  <vscale x 1 x i1>,
323  iXLen,
324  iXLen);
325
326define <vscale x 1 x i32> @intrinsic_vwmul_mask_vv_nxv1i32_nxv1i16_nxv1i16(<vscale x 1 x i32> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
327; CHECK-LABEL: intrinsic_vwmul_mask_vv_nxv1i32_nxv1i16_nxv1i16:
328; CHECK:       # %bb.0: # %entry
329; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, mu
330; CHECK-NEXT:    vwmul.vv v8, v9, v10, v0.t
331; CHECK-NEXT:    ret
332entry:
333  %a = call <vscale x 1 x i32> @llvm.riscv.vwmul.mask.nxv1i32.nxv1i16.nxv1i16(
334    <vscale x 1 x i32> %0,
335    <vscale x 1 x i16> %1,
336    <vscale x 1 x i16> %2,
337    <vscale x 1 x i1> %3,
338    iXLen %4, iXLen 1)
339
340  ret <vscale x 1 x i32> %a
341}
342
343declare <vscale x 2 x i32> @llvm.riscv.vwmul.nxv2i32.nxv2i16.nxv2i16(
344  <vscale x 2 x i32>,
345  <vscale x 2 x i16>,
346  <vscale x 2 x i16>,
347  iXLen);
348
349define <vscale x 2 x i32> @intrinsic_vwmul_vv_nxv2i32_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, iXLen %2) nounwind {
350; CHECK-LABEL: intrinsic_vwmul_vv_nxv2i32_nxv2i16_nxv2i16:
351; CHECK:       # %bb.0: # %entry
352; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma
353; CHECK-NEXT:    vwmul.vv v10, v8, v9
354; CHECK-NEXT:    vmv1r.v v8, v10
355; CHECK-NEXT:    ret
356entry:
357  %a = call <vscale x 2 x i32> @llvm.riscv.vwmul.nxv2i32.nxv2i16.nxv2i16(
358    <vscale x 2 x i32> undef,
359    <vscale x 2 x i16> %0,
360    <vscale x 2 x i16> %1,
361    iXLen %2)
362
363  ret <vscale x 2 x i32> %a
364}
365
366declare <vscale x 2 x i32> @llvm.riscv.vwmul.mask.nxv2i32.nxv2i16.nxv2i16(
367  <vscale x 2 x i32>,
368  <vscale x 2 x i16>,
369  <vscale x 2 x i16>,
370  <vscale x 2 x i1>,
371  iXLen,
372  iXLen);
373
374define <vscale x 2 x i32> @intrinsic_vwmul_mask_vv_nxv2i32_nxv2i16_nxv2i16(<vscale x 2 x i32> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
375; CHECK-LABEL: intrinsic_vwmul_mask_vv_nxv2i32_nxv2i16_nxv2i16:
376; CHECK:       # %bb.0: # %entry
377; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, mu
378; CHECK-NEXT:    vwmul.vv v8, v9, v10, v0.t
379; CHECK-NEXT:    ret
380entry:
381  %a = call <vscale x 2 x i32> @llvm.riscv.vwmul.mask.nxv2i32.nxv2i16.nxv2i16(
382    <vscale x 2 x i32> %0,
383    <vscale x 2 x i16> %1,
384    <vscale x 2 x i16> %2,
385    <vscale x 2 x i1> %3,
386    iXLen %4, iXLen 1)
387
388  ret <vscale x 2 x i32> %a
389}
390
391declare <vscale x 4 x i32> @llvm.riscv.vwmul.nxv4i32.nxv4i16.nxv4i16(
392  <vscale x 4 x i32>,
393  <vscale x 4 x i16>,
394  <vscale x 4 x i16>,
395  iXLen);
396
397define <vscale x 4 x i32> @intrinsic_vwmul_vv_nxv4i32_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, iXLen %2) nounwind {
398; CHECK-LABEL: intrinsic_vwmul_vv_nxv4i32_nxv4i16_nxv4i16:
399; CHECK:       # %bb.0: # %entry
400; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, ma
401; CHECK-NEXT:    vwmul.vv v10, v8, v9
402; CHECK-NEXT:    vmv2r.v v8, v10
403; CHECK-NEXT:    ret
404entry:
405  %a = call <vscale x 4 x i32> @llvm.riscv.vwmul.nxv4i32.nxv4i16.nxv4i16(
406    <vscale x 4 x i32> undef,
407    <vscale x 4 x i16> %0,
408    <vscale x 4 x i16> %1,
409    iXLen %2)
410
411  ret <vscale x 4 x i32> %a
412}
413
414declare <vscale x 4 x i32> @llvm.riscv.vwmul.mask.nxv4i32.nxv4i16.nxv4i16(
415  <vscale x 4 x i32>,
416  <vscale x 4 x i16>,
417  <vscale x 4 x i16>,
418  <vscale x 4 x i1>,
419  iXLen,
420  iXLen);
421
422define <vscale x 4 x i32> @intrinsic_vwmul_mask_vv_nxv4i32_nxv4i16_nxv4i16(<vscale x 4 x i32> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
423; CHECK-LABEL: intrinsic_vwmul_mask_vv_nxv4i32_nxv4i16_nxv4i16:
424; CHECK:       # %bb.0: # %entry
425; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, mu
426; CHECK-NEXT:    vwmul.vv v8, v10, v11, v0.t
427; CHECK-NEXT:    ret
428entry:
429  %a = call <vscale x 4 x i32> @llvm.riscv.vwmul.mask.nxv4i32.nxv4i16.nxv4i16(
430    <vscale x 4 x i32> %0,
431    <vscale x 4 x i16> %1,
432    <vscale x 4 x i16> %2,
433    <vscale x 4 x i1> %3,
434    iXLen %4, iXLen 1)
435
436  ret <vscale x 4 x i32> %a
437}
438
439declare <vscale x 8 x i32> @llvm.riscv.vwmul.nxv8i32.nxv8i16.nxv8i16(
440  <vscale x 8 x i32>,
441  <vscale x 8 x i16>,
442  <vscale x 8 x i16>,
443  iXLen);
444
445define <vscale x 8 x i32> @intrinsic_vwmul_vv_nxv8i32_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, iXLen %2) nounwind {
446; CHECK-LABEL: intrinsic_vwmul_vv_nxv8i32_nxv8i16_nxv8i16:
447; CHECK:       # %bb.0: # %entry
448; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, ma
449; CHECK-NEXT:    vwmul.vv v12, v8, v10
450; CHECK-NEXT:    vmv4r.v v8, v12
451; CHECK-NEXT:    ret
452entry:
453  %a = call <vscale x 8 x i32> @llvm.riscv.vwmul.nxv8i32.nxv8i16.nxv8i16(
454    <vscale x 8 x i32> undef,
455    <vscale x 8 x i16> %0,
456    <vscale x 8 x i16> %1,
457    iXLen %2)
458
459  ret <vscale x 8 x i32> %a
460}
461
462declare <vscale x 8 x i32> @llvm.riscv.vwmul.mask.nxv8i32.nxv8i16.nxv8i16(
463  <vscale x 8 x i32>,
464  <vscale x 8 x i16>,
465  <vscale x 8 x i16>,
466  <vscale x 8 x i1>,
467  iXLen,
468  iXLen);
469
470define <vscale x 8 x i32> @intrinsic_vwmul_mask_vv_nxv8i32_nxv8i16_nxv8i16(<vscale x 8 x i32> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
471; CHECK-LABEL: intrinsic_vwmul_mask_vv_nxv8i32_nxv8i16_nxv8i16:
472; CHECK:       # %bb.0: # %entry
473; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, mu
474; CHECK-NEXT:    vwmul.vv v8, v12, v14, v0.t
475; CHECK-NEXT:    ret
476entry:
477  %a = call <vscale x 8 x i32> @llvm.riscv.vwmul.mask.nxv8i32.nxv8i16.nxv8i16(
478    <vscale x 8 x i32> %0,
479    <vscale x 8 x i16> %1,
480    <vscale x 8 x i16> %2,
481    <vscale x 8 x i1> %3,
482    iXLen %4, iXLen 1)
483
484  ret <vscale x 8 x i32> %a
485}
486
487declare <vscale x 16 x i32> @llvm.riscv.vwmul.nxv16i32.nxv16i16.nxv16i16(
488  <vscale x 16 x i32>,
489  <vscale x 16 x i16>,
490  <vscale x 16 x i16>,
491  iXLen);
492
493define <vscale x 16 x i32> @intrinsic_vwmul_vv_nxv16i32_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, iXLen %2) nounwind {
494; CHECK-LABEL: intrinsic_vwmul_vv_nxv16i32_nxv16i16_nxv16i16:
495; CHECK:       # %bb.0: # %entry
496; CHECK-NEXT:    vsetvli zero, a0, e16, m4, ta, ma
497; CHECK-NEXT:    vwmul.vv v16, v8, v12
498; CHECK-NEXT:    vmv8r.v v8, v16
499; CHECK-NEXT:    ret
500entry:
501  %a = call <vscale x 16 x i32> @llvm.riscv.vwmul.nxv16i32.nxv16i16.nxv16i16(
502    <vscale x 16 x i32> undef,
503    <vscale x 16 x i16> %0,
504    <vscale x 16 x i16> %1,
505    iXLen %2)
506
507  ret <vscale x 16 x i32> %a
508}
509
510declare <vscale x 16 x i32> @llvm.riscv.vwmul.mask.nxv16i32.nxv16i16.nxv16i16(
511  <vscale x 16 x i32>,
512  <vscale x 16 x i16>,
513  <vscale x 16 x i16>,
514  <vscale x 16 x i1>,
515  iXLen,
516  iXLen);
517
518define <vscale x 16 x i32> @intrinsic_vwmul_mask_vv_nxv16i32_nxv16i16_nxv16i16(<vscale x 16 x i32> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
519; CHECK-LABEL: intrinsic_vwmul_mask_vv_nxv16i32_nxv16i16_nxv16i16:
520; CHECK:       # %bb.0: # %entry
521; CHECK-NEXT:    vsetvli zero, a0, e16, m4, ta, mu
522; CHECK-NEXT:    vwmul.vv v8, v16, v20, v0.t
523; CHECK-NEXT:    ret
524entry:
525  %a = call <vscale x 16 x i32> @llvm.riscv.vwmul.mask.nxv16i32.nxv16i16.nxv16i16(
526    <vscale x 16 x i32> %0,
527    <vscale x 16 x i16> %1,
528    <vscale x 16 x i16> %2,
529    <vscale x 16 x i1> %3,
530    iXLen %4, iXLen 1)
531
532  ret <vscale x 16 x i32> %a
533}
534
535declare <vscale x 1 x i64> @llvm.riscv.vwmul.nxv1i64.nxv1i32.nxv1i32(
536  <vscale x 1 x i64>,
537  <vscale x 1 x i32>,
538  <vscale x 1 x i32>,
539  iXLen);
540
541define <vscale x 1 x i64> @intrinsic_vwmul_vv_nxv1i64_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, iXLen %2) nounwind {
542; CHECK-LABEL: intrinsic_vwmul_vv_nxv1i64_nxv1i32_nxv1i32:
543; CHECK:       # %bb.0: # %entry
544; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma
545; CHECK-NEXT:    vwmul.vv v10, v8, v9
546; CHECK-NEXT:    vmv1r.v v8, v10
547; CHECK-NEXT:    ret
548entry:
549  %a = call <vscale x 1 x i64> @llvm.riscv.vwmul.nxv1i64.nxv1i32.nxv1i32(
550    <vscale x 1 x i64> undef,
551    <vscale x 1 x i32> %0,
552    <vscale x 1 x i32> %1,
553    iXLen %2)
554
555  ret <vscale x 1 x i64> %a
556}
557
558declare <vscale x 1 x i64> @llvm.riscv.vwmul.mask.nxv1i64.nxv1i32.nxv1i32(
559  <vscale x 1 x i64>,
560  <vscale x 1 x i32>,
561  <vscale x 1 x i32>,
562  <vscale x 1 x i1>,
563  iXLen,
564  iXLen);
565
566define <vscale x 1 x i64> @intrinsic_vwmul_mask_vv_nxv1i64_nxv1i32_nxv1i32(<vscale x 1 x i64> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
567; CHECK-LABEL: intrinsic_vwmul_mask_vv_nxv1i64_nxv1i32_nxv1i32:
568; CHECK:       # %bb.0: # %entry
569; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, mu
570; CHECK-NEXT:    vwmul.vv v8, v9, v10, v0.t
571; CHECK-NEXT:    ret
572entry:
573  %a = call <vscale x 1 x i64> @llvm.riscv.vwmul.mask.nxv1i64.nxv1i32.nxv1i32(
574    <vscale x 1 x i64> %0,
575    <vscale x 1 x i32> %1,
576    <vscale x 1 x i32> %2,
577    <vscale x 1 x i1> %3,
578    iXLen %4, iXLen 1)
579
580  ret <vscale x 1 x i64> %a
581}
582
583declare <vscale x 2 x i64> @llvm.riscv.vwmul.nxv2i64.nxv2i32.nxv2i32(
584  <vscale x 2 x i64>,
585  <vscale x 2 x i32>,
586  <vscale x 2 x i32>,
587  iXLen);
588
589define <vscale x 2 x i64> @intrinsic_vwmul_vv_nxv2i64_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, iXLen %2) nounwind {
590; CHECK-LABEL: intrinsic_vwmul_vv_nxv2i64_nxv2i32_nxv2i32:
591; CHECK:       # %bb.0: # %entry
592; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma
593; CHECK-NEXT:    vwmul.vv v10, v8, v9
594; CHECK-NEXT:    vmv2r.v v8, v10
595; CHECK-NEXT:    ret
596entry:
597  %a = call <vscale x 2 x i64> @llvm.riscv.vwmul.nxv2i64.nxv2i32.nxv2i32(
598    <vscale x 2 x i64> undef,
599    <vscale x 2 x i32> %0,
600    <vscale x 2 x i32> %1,
601    iXLen %2)
602
603  ret <vscale x 2 x i64> %a
604}
605
606declare <vscale x 2 x i64> @llvm.riscv.vwmul.mask.nxv2i64.nxv2i32.nxv2i32(
607  <vscale x 2 x i64>,
608  <vscale x 2 x i32>,
609  <vscale x 2 x i32>,
610  <vscale x 2 x i1>,
611  iXLen,
612  iXLen);
613
614define <vscale x 2 x i64> @intrinsic_vwmul_mask_vv_nxv2i64_nxv2i32_nxv2i32(<vscale x 2 x i64> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
615; CHECK-LABEL: intrinsic_vwmul_mask_vv_nxv2i64_nxv2i32_nxv2i32:
616; CHECK:       # %bb.0: # %entry
617; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, mu
618; CHECK-NEXT:    vwmul.vv v8, v10, v11, v0.t
619; CHECK-NEXT:    ret
620entry:
621  %a = call <vscale x 2 x i64> @llvm.riscv.vwmul.mask.nxv2i64.nxv2i32.nxv2i32(
622    <vscale x 2 x i64> %0,
623    <vscale x 2 x i32> %1,
624    <vscale x 2 x i32> %2,
625    <vscale x 2 x i1> %3,
626    iXLen %4, iXLen 1)
627
628  ret <vscale x 2 x i64> %a
629}
630
631declare <vscale x 4 x i64> @llvm.riscv.vwmul.nxv4i64.nxv4i32.nxv4i32(
632  <vscale x 4 x i64>,
633  <vscale x 4 x i32>,
634  <vscale x 4 x i32>,
635  iXLen);
636
637define <vscale x 4 x i64> @intrinsic_vwmul_vv_nxv4i64_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, iXLen %2) nounwind {
638; CHECK-LABEL: intrinsic_vwmul_vv_nxv4i64_nxv4i32_nxv4i32:
639; CHECK:       # %bb.0: # %entry
640; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma
641; CHECK-NEXT:    vwmul.vv v12, v8, v10
642; CHECK-NEXT:    vmv4r.v v8, v12
643; CHECK-NEXT:    ret
644entry:
645  %a = call <vscale x 4 x i64> @llvm.riscv.vwmul.nxv4i64.nxv4i32.nxv4i32(
646    <vscale x 4 x i64> undef,
647    <vscale x 4 x i32> %0,
648    <vscale x 4 x i32> %1,
649    iXLen %2)
650
651  ret <vscale x 4 x i64> %a
652}
653
654declare <vscale x 4 x i64> @llvm.riscv.vwmul.mask.nxv4i64.nxv4i32.nxv4i32(
655  <vscale x 4 x i64>,
656  <vscale x 4 x i32>,
657  <vscale x 4 x i32>,
658  <vscale x 4 x i1>,
659  iXLen,
660  iXLen);
661
662define <vscale x 4 x i64> @intrinsic_vwmul_mask_vv_nxv4i64_nxv4i32_nxv4i32(<vscale x 4 x i64> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
663; CHECK-LABEL: intrinsic_vwmul_mask_vv_nxv4i64_nxv4i32_nxv4i32:
664; CHECK:       # %bb.0: # %entry
665; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, mu
666; CHECK-NEXT:    vwmul.vv v8, v12, v14, v0.t
667; CHECK-NEXT:    ret
668entry:
669  %a = call <vscale x 4 x i64> @llvm.riscv.vwmul.mask.nxv4i64.nxv4i32.nxv4i32(
670    <vscale x 4 x i64> %0,
671    <vscale x 4 x i32> %1,
672    <vscale x 4 x i32> %2,
673    <vscale x 4 x i1> %3,
674    iXLen %4, iXLen 1)
675
676  ret <vscale x 4 x i64> %a
677}
678
679declare <vscale x 8 x i64> @llvm.riscv.vwmul.nxv8i64.nxv8i32.nxv8i32(
680  <vscale x 8 x i64>,
681  <vscale x 8 x i32>,
682  <vscale x 8 x i32>,
683  iXLen);
684
685define <vscale x 8 x i64> @intrinsic_vwmul_vv_nxv8i64_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, iXLen %2) nounwind {
686; CHECK-LABEL: intrinsic_vwmul_vv_nxv8i64_nxv8i32_nxv8i32:
687; CHECK:       # %bb.0: # %entry
688; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, ma
689; CHECK-NEXT:    vwmul.vv v16, v8, v12
690; CHECK-NEXT:    vmv8r.v v8, v16
691; CHECK-NEXT:    ret
692entry:
693  %a = call <vscale x 8 x i64> @llvm.riscv.vwmul.nxv8i64.nxv8i32.nxv8i32(
694    <vscale x 8 x i64> undef,
695    <vscale x 8 x i32> %0,
696    <vscale x 8 x i32> %1,
697    iXLen %2)
698
699  ret <vscale x 8 x i64> %a
700}
701
702declare <vscale x 8 x i64> @llvm.riscv.vwmul.mask.nxv8i64.nxv8i32.nxv8i32(
703  <vscale x 8 x i64>,
704  <vscale x 8 x i32>,
705  <vscale x 8 x i32>,
706  <vscale x 8 x i1>,
707  iXLen,
708  iXLen);
709
710define <vscale x 8 x i64> @intrinsic_vwmul_mask_vv_nxv8i64_nxv8i32_nxv8i32(<vscale x 8 x i64> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
711; CHECK-LABEL: intrinsic_vwmul_mask_vv_nxv8i64_nxv8i32_nxv8i32:
712; CHECK:       # %bb.0: # %entry
713; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, mu
714; CHECK-NEXT:    vwmul.vv v8, v16, v20, v0.t
715; CHECK-NEXT:    ret
716entry:
717  %a = call <vscale x 8 x i64> @llvm.riscv.vwmul.mask.nxv8i64.nxv8i32.nxv8i32(
718    <vscale x 8 x i64> %0,
719    <vscale x 8 x i32> %1,
720    <vscale x 8 x i32> %2,
721    <vscale x 8 x i1> %3,
722    iXLen %4, iXLen 1)
723
724  ret <vscale x 8 x i64> %a
725}
726
727declare <vscale x 1 x i16> @llvm.riscv.vwmul.nxv1i16.nxv1i8.i8(
728  <vscale x 1 x i16>,
729  <vscale x 1 x i8>,
730  i8,
731  iXLen);
732
733define <vscale x 1 x i16> @intrinsic_vwmul_vx_nxv1i16_nxv1i8_i8(<vscale x 1 x i8> %0, i8 %1, iXLen %2) nounwind {
734; CHECK-LABEL: intrinsic_vwmul_vx_nxv1i16_nxv1i8_i8:
735; CHECK:       # %bb.0: # %entry
736; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma
737; CHECK-NEXT:    vwmul.vx v9, v8, a0
738; CHECK-NEXT:    vmv1r.v v8, v9
739; CHECK-NEXT:    ret
740entry:
741  %a = call <vscale x 1 x i16> @llvm.riscv.vwmul.nxv1i16.nxv1i8.i8(
742    <vscale x 1 x i16> undef,
743    <vscale x 1 x i8> %0,
744    i8 %1,
745    iXLen %2)
746
747  ret <vscale x 1 x i16> %a
748}
749
750declare <vscale x 1 x i16> @llvm.riscv.vwmul.mask.nxv1i16.nxv1i8.i8(
751  <vscale x 1 x i16>,
752  <vscale x 1 x i8>,
753  i8,
754  <vscale x 1 x i1>,
755  iXLen,
756  iXLen);
757
758define <vscale x 1 x i16> @intrinsic_vwmul_mask_vx_nxv1i16_nxv1i8_i8(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
759; CHECK-LABEL: intrinsic_vwmul_mask_vx_nxv1i16_nxv1i8_i8:
760; CHECK:       # %bb.0: # %entry
761; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, mu
762; CHECK-NEXT:    vwmul.vx v8, v9, a0, v0.t
763; CHECK-NEXT:    ret
764entry:
765  %a = call <vscale x 1 x i16> @llvm.riscv.vwmul.mask.nxv1i16.nxv1i8.i8(
766    <vscale x 1 x i16> %0,
767    <vscale x 1 x i8> %1,
768    i8 %2,
769    <vscale x 1 x i1> %3,
770    iXLen %4, iXLen 1)
771
772  ret <vscale x 1 x i16> %a
773}
774
775declare <vscale x 2 x i16> @llvm.riscv.vwmul.nxv2i16.nxv2i8.i8(
776  <vscale x 2 x i16>,
777  <vscale x 2 x i8>,
778  i8,
779  iXLen);
780
781define <vscale x 2 x i16> @intrinsic_vwmul_vx_nxv2i16_nxv2i8_i8(<vscale x 2 x i8> %0, i8 %1, iXLen %2) nounwind {
782; CHECK-LABEL: intrinsic_vwmul_vx_nxv2i16_nxv2i8_i8:
783; CHECK:       # %bb.0: # %entry
784; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma
785; CHECK-NEXT:    vwmul.vx v9, v8, a0
786; CHECK-NEXT:    vmv1r.v v8, v9
787; CHECK-NEXT:    ret
788entry:
789  %a = call <vscale x 2 x i16> @llvm.riscv.vwmul.nxv2i16.nxv2i8.i8(
790    <vscale x 2 x i16> undef,
791    <vscale x 2 x i8> %0,
792    i8 %1,
793    iXLen %2)
794
795  ret <vscale x 2 x i16> %a
796}
797
798declare <vscale x 2 x i16> @llvm.riscv.vwmul.mask.nxv2i16.nxv2i8.i8(
799  <vscale x 2 x i16>,
800  <vscale x 2 x i8>,
801  i8,
802  <vscale x 2 x i1>,
803  iXLen,
804  iXLen);
805
806define <vscale x 2 x i16> @intrinsic_vwmul_mask_vx_nxv2i16_nxv2i8_i8(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
807; CHECK-LABEL: intrinsic_vwmul_mask_vx_nxv2i16_nxv2i8_i8:
808; CHECK:       # %bb.0: # %entry
809; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, mu
810; CHECK-NEXT:    vwmul.vx v8, v9, a0, v0.t
811; CHECK-NEXT:    ret
812entry:
813  %a = call <vscale x 2 x i16> @llvm.riscv.vwmul.mask.nxv2i16.nxv2i8.i8(
814    <vscale x 2 x i16> %0,
815    <vscale x 2 x i8> %1,
816    i8 %2,
817    <vscale x 2 x i1> %3,
818    iXLen %4, iXLen 1)
819
820  ret <vscale x 2 x i16> %a
821}
822
823declare <vscale x 4 x i16> @llvm.riscv.vwmul.nxv4i16.nxv4i8.i8(
824  <vscale x 4 x i16>,
825  <vscale x 4 x i8>,
826  i8,
827  iXLen);
828
829define <vscale x 4 x i16> @intrinsic_vwmul_vx_nxv4i16_nxv4i8_i8(<vscale x 4 x i8> %0, i8 %1, iXLen %2) nounwind {
830; CHECK-LABEL: intrinsic_vwmul_vx_nxv4i16_nxv4i8_i8:
831; CHECK:       # %bb.0: # %entry
832; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma
833; CHECK-NEXT:    vwmul.vx v9, v8, a0
834; CHECK-NEXT:    vmv1r.v v8, v9
835; CHECK-NEXT:    ret
836entry:
837  %a = call <vscale x 4 x i16> @llvm.riscv.vwmul.nxv4i16.nxv4i8.i8(
838    <vscale x 4 x i16> undef,
839    <vscale x 4 x i8> %0,
840    i8 %1,
841    iXLen %2)
842
843  ret <vscale x 4 x i16> %a
844}
845
846declare <vscale x 4 x i16> @llvm.riscv.vwmul.mask.nxv4i16.nxv4i8.i8(
847  <vscale x 4 x i16>,
848  <vscale x 4 x i8>,
849  i8,
850  <vscale x 4 x i1>,
851  iXLen,
852  iXLen);
853
854define <vscale x 4 x i16> @intrinsic_vwmul_mask_vx_nxv4i16_nxv4i8_i8(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
855; CHECK-LABEL: intrinsic_vwmul_mask_vx_nxv4i16_nxv4i8_i8:
856; CHECK:       # %bb.0: # %entry
857; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, mu
858; CHECK-NEXT:    vwmul.vx v8, v9, a0, v0.t
859; CHECK-NEXT:    ret
860entry:
861  %a = call <vscale x 4 x i16> @llvm.riscv.vwmul.mask.nxv4i16.nxv4i8.i8(
862    <vscale x 4 x i16> %0,
863    <vscale x 4 x i8> %1,
864    i8 %2,
865    <vscale x 4 x i1> %3,
866    iXLen %4, iXLen 1)
867
868  ret <vscale x 4 x i16> %a
869}
870
871declare <vscale x 8 x i16> @llvm.riscv.vwmul.nxv8i16.nxv8i8.i8(
872  <vscale x 8 x i16>,
873  <vscale x 8 x i8>,
874  i8,
875  iXLen);
876
877define <vscale x 8 x i16> @intrinsic_vwmul_vx_nxv8i16_nxv8i8_i8(<vscale x 8 x i8> %0, i8 %1, iXLen %2) nounwind {
878; CHECK-LABEL: intrinsic_vwmul_vx_nxv8i16_nxv8i8_i8:
879; CHECK:       # %bb.0: # %entry
880; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma
881; CHECK-NEXT:    vwmul.vx v10, v8, a0
882; CHECK-NEXT:    vmv2r.v v8, v10
883; CHECK-NEXT:    ret
884entry:
885  %a = call <vscale x 8 x i16> @llvm.riscv.vwmul.nxv8i16.nxv8i8.i8(
886    <vscale x 8 x i16> undef,
887    <vscale x 8 x i8> %0,
888    i8 %1,
889    iXLen %2)
890
891  ret <vscale x 8 x i16> %a
892}
893
894declare <vscale x 8 x i16> @llvm.riscv.vwmul.mask.nxv8i16.nxv8i8.i8(
895  <vscale x 8 x i16>,
896  <vscale x 8 x i8>,
897  i8,
898  <vscale x 8 x i1>,
899  iXLen,
900  iXLen);
901
902define <vscale x 8 x i16> @intrinsic_vwmul_mask_vx_nxv8i16_nxv8i8_i8(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
903; CHECK-LABEL: intrinsic_vwmul_mask_vx_nxv8i16_nxv8i8_i8:
904; CHECK:       # %bb.0: # %entry
905; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, mu
906; CHECK-NEXT:    vwmul.vx v8, v10, a0, v0.t
907; CHECK-NEXT:    ret
908entry:
909  %a = call <vscale x 8 x i16> @llvm.riscv.vwmul.mask.nxv8i16.nxv8i8.i8(
910    <vscale x 8 x i16> %0,
911    <vscale x 8 x i8> %1,
912    i8 %2,
913    <vscale x 8 x i1> %3,
914    iXLen %4, iXLen 1)
915
916  ret <vscale x 8 x i16> %a
917}
918
919declare <vscale x 16 x i16> @llvm.riscv.vwmul.nxv16i16.nxv16i8.i8(
920  <vscale x 16 x i16>,
921  <vscale x 16 x i8>,
922  i8,
923  iXLen);
924
925define <vscale x 16 x i16> @intrinsic_vwmul_vx_nxv16i16_nxv16i8_i8(<vscale x 16 x i8> %0, i8 %1, iXLen %2) nounwind {
926; CHECK-LABEL: intrinsic_vwmul_vx_nxv16i16_nxv16i8_i8:
927; CHECK:       # %bb.0: # %entry
928; CHECK-NEXT:    vsetvli zero, a1, e8, m2, ta, ma
929; CHECK-NEXT:    vwmul.vx v12, v8, a0
930; CHECK-NEXT:    vmv4r.v v8, v12
931; CHECK-NEXT:    ret
932entry:
933  %a = call <vscale x 16 x i16> @llvm.riscv.vwmul.nxv16i16.nxv16i8.i8(
934    <vscale x 16 x i16> undef,
935    <vscale x 16 x i8> %0,
936    i8 %1,
937    iXLen %2)
938
939  ret <vscale x 16 x i16> %a
940}
941
942declare <vscale x 16 x i16> @llvm.riscv.vwmul.mask.nxv16i16.nxv16i8.i8(
943  <vscale x 16 x i16>,
944  <vscale x 16 x i8>,
945  i8,
946  <vscale x 16 x i1>,
947  iXLen,
948  iXLen);
949
950define <vscale x 16 x i16> @intrinsic_vwmul_mask_vx_nxv16i16_nxv16i8_i8(<vscale x 16 x i16> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
951; CHECK-LABEL: intrinsic_vwmul_mask_vx_nxv16i16_nxv16i8_i8:
952; CHECK:       # %bb.0: # %entry
953; CHECK-NEXT:    vsetvli zero, a1, e8, m2, ta, mu
954; CHECK-NEXT:    vwmul.vx v8, v12, a0, v0.t
955; CHECK-NEXT:    ret
956entry:
957  %a = call <vscale x 16 x i16> @llvm.riscv.vwmul.mask.nxv16i16.nxv16i8.i8(
958    <vscale x 16 x i16> %0,
959    <vscale x 16 x i8> %1,
960    i8 %2,
961    <vscale x 16 x i1> %3,
962    iXLen %4, iXLen 1)
963
964  ret <vscale x 16 x i16> %a
965}
966
967declare <vscale x 32 x i16> @llvm.riscv.vwmul.nxv32i16.nxv32i8.i8(
968  <vscale x 32 x i16>,
969  <vscale x 32 x i8>,
970  i8,
971  iXLen);
972
973define <vscale x 32 x i16> @intrinsic_vwmul_vx_nxv32i16_nxv32i8_i8(<vscale x 32 x i8> %0, i8 %1, iXLen %2) nounwind {
974; CHECK-LABEL: intrinsic_vwmul_vx_nxv32i16_nxv32i8_i8:
975; CHECK:       # %bb.0: # %entry
976; CHECK-NEXT:    vsetvli zero, a1, e8, m4, ta, ma
977; CHECK-NEXT:    vwmul.vx v16, v8, a0
978; CHECK-NEXT:    vmv8r.v v8, v16
979; CHECK-NEXT:    ret
980entry:
981  %a = call <vscale x 32 x i16> @llvm.riscv.vwmul.nxv32i16.nxv32i8.i8(
982    <vscale x 32 x i16> undef,
983    <vscale x 32 x i8> %0,
984    i8 %1,
985    iXLen %2)
986
987  ret <vscale x 32 x i16> %a
988}
989
990declare <vscale x 32 x i16> @llvm.riscv.vwmul.mask.nxv32i16.nxv32i8.i8(
991  <vscale x 32 x i16>,
992  <vscale x 32 x i8>,
993  i8,
994  <vscale x 32 x i1>,
995  iXLen,
996  iXLen);
997
998define <vscale x 32 x i16> @intrinsic_vwmul_mask_vx_nxv32i16_nxv32i8_i8(<vscale x 32 x i16> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {
999; CHECK-LABEL: intrinsic_vwmul_mask_vx_nxv32i16_nxv32i8_i8:
1000; CHECK:       # %bb.0: # %entry
1001; CHECK-NEXT:    vsetvli zero, a1, e8, m4, ta, mu
1002; CHECK-NEXT:    vwmul.vx v8, v16, a0, v0.t
1003; CHECK-NEXT:    ret
1004entry:
1005  %a = call <vscale x 32 x i16> @llvm.riscv.vwmul.mask.nxv32i16.nxv32i8.i8(
1006    <vscale x 32 x i16> %0,
1007    <vscale x 32 x i8> %1,
1008    i8 %2,
1009    <vscale x 32 x i1> %3,
1010    iXLen %4, iXLen 1)
1011
1012  ret <vscale x 32 x i16> %a
1013}
1014
1015declare <vscale x 1 x i32> @llvm.riscv.vwmul.nxv1i32.nxv1i16.i16(
1016  <vscale x 1 x i32>,
1017  <vscale x 1 x i16>,
1018  i16,
1019  iXLen);
1020
1021define <vscale x 1 x i32> @intrinsic_vwmul_vx_nxv1i32_nxv1i16_i16(<vscale x 1 x i16> %0, i16 %1, iXLen %2) nounwind {
1022; CHECK-LABEL: intrinsic_vwmul_vx_nxv1i32_nxv1i16_i16:
1023; CHECK:       # %bb.0: # %entry
1024; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
1025; CHECK-NEXT:    vwmul.vx v9, v8, a0
1026; CHECK-NEXT:    vmv1r.v v8, v9
1027; CHECK-NEXT:    ret
1028entry:
1029  %a = call <vscale x 1 x i32> @llvm.riscv.vwmul.nxv1i32.nxv1i16.i16(
1030    <vscale x 1 x i32> undef,
1031    <vscale x 1 x i16> %0,
1032    i16 %1,
1033    iXLen %2)
1034
1035  ret <vscale x 1 x i32> %a
1036}
1037
1038declare <vscale x 1 x i32> @llvm.riscv.vwmul.mask.nxv1i32.nxv1i16.i16(
1039  <vscale x 1 x i32>,
1040  <vscale x 1 x i16>,
1041  i16,
1042  <vscale x 1 x i1>,
1043  iXLen,
1044  iXLen);
1045
1046define <vscale x 1 x i32> @intrinsic_vwmul_mask_vx_nxv1i32_nxv1i16_i16(<vscale x 1 x i32> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
1047; CHECK-LABEL: intrinsic_vwmul_mask_vx_nxv1i32_nxv1i16_i16:
1048; CHECK:       # %bb.0: # %entry
1049; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, mu
1050; CHECK-NEXT:    vwmul.vx v8, v9, a0, v0.t
1051; CHECK-NEXT:    ret
1052entry:
1053  %a = call <vscale x 1 x i32> @llvm.riscv.vwmul.mask.nxv1i32.nxv1i16.i16(
1054    <vscale x 1 x i32> %0,
1055    <vscale x 1 x i16> %1,
1056    i16 %2,
1057    <vscale x 1 x i1> %3,
1058    iXLen %4, iXLen 1)
1059
1060  ret <vscale x 1 x i32> %a
1061}
1062
1063declare <vscale x 2 x i32> @llvm.riscv.vwmul.nxv2i32.nxv2i16.i16(
1064  <vscale x 2 x i32>,
1065  <vscale x 2 x i16>,
1066  i16,
1067  iXLen);
1068
1069define <vscale x 2 x i32> @intrinsic_vwmul_vx_nxv2i32_nxv2i16_i16(<vscale x 2 x i16> %0, i16 %1, iXLen %2) nounwind {
1070; CHECK-LABEL: intrinsic_vwmul_vx_nxv2i32_nxv2i16_i16:
1071; CHECK:       # %bb.0: # %entry
1072; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
1073; CHECK-NEXT:    vwmul.vx v9, v8, a0
1074; CHECK-NEXT:    vmv1r.v v8, v9
1075; CHECK-NEXT:    ret
1076entry:
1077  %a = call <vscale x 2 x i32> @llvm.riscv.vwmul.nxv2i32.nxv2i16.i16(
1078    <vscale x 2 x i32> undef,
1079    <vscale x 2 x i16> %0,
1080    i16 %1,
1081    iXLen %2)
1082
1083  ret <vscale x 2 x i32> %a
1084}
1085
1086declare <vscale x 2 x i32> @llvm.riscv.vwmul.mask.nxv2i32.nxv2i16.i16(
1087  <vscale x 2 x i32>,
1088  <vscale x 2 x i16>,
1089  i16,
1090  <vscale x 2 x i1>,
1091  iXLen,
1092  iXLen);
1093
1094define <vscale x 2 x i32> @intrinsic_vwmul_mask_vx_nxv2i32_nxv2i16_i16(<vscale x 2 x i32> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
1095; CHECK-LABEL: intrinsic_vwmul_mask_vx_nxv2i32_nxv2i16_i16:
1096; CHECK:       # %bb.0: # %entry
1097; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, mu
1098; CHECK-NEXT:    vwmul.vx v8, v9, a0, v0.t
1099; CHECK-NEXT:    ret
1100entry:
1101  %a = call <vscale x 2 x i32> @llvm.riscv.vwmul.mask.nxv2i32.nxv2i16.i16(
1102    <vscale x 2 x i32> %0,
1103    <vscale x 2 x i16> %1,
1104    i16 %2,
1105    <vscale x 2 x i1> %3,
1106    iXLen %4, iXLen 1)
1107
1108  ret <vscale x 2 x i32> %a
1109}
1110
1111declare <vscale x 4 x i32> @llvm.riscv.vwmul.nxv4i32.nxv4i16.i16(
1112  <vscale x 4 x i32>,
1113  <vscale x 4 x i16>,
1114  i16,
1115  iXLen);
1116
1117define <vscale x 4 x i32> @intrinsic_vwmul_vx_nxv4i32_nxv4i16_i16(<vscale x 4 x i16> %0, i16 %1, iXLen %2) nounwind {
1118; CHECK-LABEL: intrinsic_vwmul_vx_nxv4i32_nxv4i16_i16:
1119; CHECK:       # %bb.0: # %entry
1120; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
1121; CHECK-NEXT:    vwmul.vx v10, v8, a0
1122; CHECK-NEXT:    vmv2r.v v8, v10
1123; CHECK-NEXT:    ret
1124entry:
1125  %a = call <vscale x 4 x i32> @llvm.riscv.vwmul.nxv4i32.nxv4i16.i16(
1126    <vscale x 4 x i32> undef,
1127    <vscale x 4 x i16> %0,
1128    i16 %1,
1129    iXLen %2)
1130
1131  ret <vscale x 4 x i32> %a
1132}
1133
1134declare <vscale x 4 x i32> @llvm.riscv.vwmul.mask.nxv4i32.nxv4i16.i16(
1135  <vscale x 4 x i32>,
1136  <vscale x 4 x i16>,
1137  i16,
1138  <vscale x 4 x i1>,
1139  iXLen,
1140  iXLen);
1141
1142define <vscale x 4 x i32> @intrinsic_vwmul_mask_vx_nxv4i32_nxv4i16_i16(<vscale x 4 x i32> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
1143; CHECK-LABEL: intrinsic_vwmul_mask_vx_nxv4i32_nxv4i16_i16:
1144; CHECK:       # %bb.0: # %entry
1145; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, mu
1146; CHECK-NEXT:    vwmul.vx v8, v10, a0, v0.t
1147; CHECK-NEXT:    ret
1148entry:
1149  %a = call <vscale x 4 x i32> @llvm.riscv.vwmul.mask.nxv4i32.nxv4i16.i16(
1150    <vscale x 4 x i32> %0,
1151    <vscale x 4 x i16> %1,
1152    i16 %2,
1153    <vscale x 4 x i1> %3,
1154    iXLen %4, iXLen 1)
1155
1156  ret <vscale x 4 x i32> %a
1157}
1158
1159declare <vscale x 8 x i32> @llvm.riscv.vwmul.nxv8i32.nxv8i16.i16(
1160  <vscale x 8 x i32>,
1161  <vscale x 8 x i16>,
1162  i16,
1163  iXLen);
1164
1165define <vscale x 8 x i32> @intrinsic_vwmul_vx_nxv8i32_nxv8i16_i16(<vscale x 8 x i16> %0, i16 %1, iXLen %2) nounwind {
1166; CHECK-LABEL: intrinsic_vwmul_vx_nxv8i32_nxv8i16_i16:
1167; CHECK:       # %bb.0: # %entry
1168; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma
1169; CHECK-NEXT:    vwmul.vx v12, v8, a0
1170; CHECK-NEXT:    vmv4r.v v8, v12
1171; CHECK-NEXT:    ret
1172entry:
1173  %a = call <vscale x 8 x i32> @llvm.riscv.vwmul.nxv8i32.nxv8i16.i16(
1174    <vscale x 8 x i32> undef,
1175    <vscale x 8 x i16> %0,
1176    i16 %1,
1177    iXLen %2)
1178
1179  ret <vscale x 8 x i32> %a
1180}
1181
1182declare <vscale x 8 x i32> @llvm.riscv.vwmul.mask.nxv8i32.nxv8i16.i16(
1183  <vscale x 8 x i32>,
1184  <vscale x 8 x i16>,
1185  i16,
1186  <vscale x 8 x i1>,
1187  iXLen,
1188  iXLen);
1189
1190define <vscale x 8 x i32> @intrinsic_vwmul_mask_vx_nxv8i32_nxv8i16_i16(<vscale x 8 x i32> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
1191; CHECK-LABEL: intrinsic_vwmul_mask_vx_nxv8i32_nxv8i16_i16:
1192; CHECK:       # %bb.0: # %entry
1193; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, mu
1194; CHECK-NEXT:    vwmul.vx v8, v12, a0, v0.t
1195; CHECK-NEXT:    ret
1196entry:
1197  %a = call <vscale x 8 x i32> @llvm.riscv.vwmul.mask.nxv8i32.nxv8i16.i16(
1198    <vscale x 8 x i32> %0,
1199    <vscale x 8 x i16> %1,
1200    i16 %2,
1201    <vscale x 8 x i1> %3,
1202    iXLen %4, iXLen 1)
1203
1204  ret <vscale x 8 x i32> %a
1205}
1206
1207declare <vscale x 16 x i32> @llvm.riscv.vwmul.nxv16i32.nxv16i16.i16(
1208  <vscale x 16 x i32>,
1209  <vscale x 16 x i16>,
1210  i16,
1211  iXLen);
1212
1213define <vscale x 16 x i32> @intrinsic_vwmul_vx_nxv16i32_nxv16i16_i16(<vscale x 16 x i16> %0, i16 %1, iXLen %2) nounwind {
1214; CHECK-LABEL: intrinsic_vwmul_vx_nxv16i32_nxv16i16_i16:
1215; CHECK:       # %bb.0: # %entry
1216; CHECK-NEXT:    vsetvli zero, a1, e16, m4, ta, ma
1217; CHECK-NEXT:    vwmul.vx v16, v8, a0
1218; CHECK-NEXT:    vmv8r.v v8, v16
1219; CHECK-NEXT:    ret
1220entry:
1221  %a = call <vscale x 16 x i32> @llvm.riscv.vwmul.nxv16i32.nxv16i16.i16(
1222    <vscale x 16 x i32> undef,
1223    <vscale x 16 x i16> %0,
1224    i16 %1,
1225    iXLen %2)
1226
1227  ret <vscale x 16 x i32> %a
1228}
1229
1230declare <vscale x 16 x i32> @llvm.riscv.vwmul.mask.nxv16i32.nxv16i16.i16(
1231  <vscale x 16 x i32>,
1232  <vscale x 16 x i16>,
1233  i16,
1234  <vscale x 16 x i1>,
1235  iXLen,
1236  iXLen);
1237
1238define <vscale x 16 x i32> @intrinsic_vwmul_mask_vx_nxv16i32_nxv16i16_i16(<vscale x 16 x i32> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
1239; CHECK-LABEL: intrinsic_vwmul_mask_vx_nxv16i32_nxv16i16_i16:
1240; CHECK:       # %bb.0: # %entry
1241; CHECK-NEXT:    vsetvli zero, a1, e16, m4, ta, mu
1242; CHECK-NEXT:    vwmul.vx v8, v16, a0, v0.t
1243; CHECK-NEXT:    ret
1244entry:
1245  %a = call <vscale x 16 x i32> @llvm.riscv.vwmul.mask.nxv16i32.nxv16i16.i16(
1246    <vscale x 16 x i32> %0,
1247    <vscale x 16 x i16> %1,
1248    i16 %2,
1249    <vscale x 16 x i1> %3,
1250    iXLen %4, iXLen 1)
1251
1252  ret <vscale x 16 x i32> %a
1253}
1254
1255declare <vscale x 1 x i64> @llvm.riscv.vwmul.nxv1i64.nxv1i32.i32(
1256  <vscale x 1 x i64>,
1257  <vscale x 1 x i32>,
1258  i32,
1259  iXLen);
1260
1261define <vscale x 1 x i64> @intrinsic_vwmul_vx_nxv1i64_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1, iXLen %2) nounwind {
1262; CHECK-LABEL: intrinsic_vwmul_vx_nxv1i64_nxv1i32_i32:
1263; CHECK:       # %bb.0: # %entry
1264; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma
1265; CHECK-NEXT:    vwmul.vx v9, v8, a0
1266; CHECK-NEXT:    vmv1r.v v8, v9
1267; CHECK-NEXT:    ret
1268entry:
1269  %a = call <vscale x 1 x i64> @llvm.riscv.vwmul.nxv1i64.nxv1i32.i32(
1270    <vscale x 1 x i64> undef,
1271    <vscale x 1 x i32> %0,
1272    i32 %1,
1273    iXLen %2)
1274
1275  ret <vscale x 1 x i64> %a
1276}
1277
1278declare <vscale x 1 x i64> @llvm.riscv.vwmul.mask.nxv1i64.nxv1i32.i32(
1279  <vscale x 1 x i64>,
1280  <vscale x 1 x i32>,
1281  i32,
1282  <vscale x 1 x i1>,
1283  iXLen,
1284  iXLen);
1285
1286define <vscale x 1 x i64> @intrinsic_vwmul_mask_vx_nxv1i64_nxv1i32_i32(<vscale x 1 x i64> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
1287; CHECK-LABEL: intrinsic_vwmul_mask_vx_nxv1i64_nxv1i32_i32:
1288; CHECK:       # %bb.0: # %entry
1289; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, mu
1290; CHECK-NEXT:    vwmul.vx v8, v9, a0, v0.t
1291; CHECK-NEXT:    ret
1292entry:
1293  %a = call <vscale x 1 x i64> @llvm.riscv.vwmul.mask.nxv1i64.nxv1i32.i32(
1294    <vscale x 1 x i64> %0,
1295    <vscale x 1 x i32> %1,
1296    i32 %2,
1297    <vscale x 1 x i1> %3,
1298    iXLen %4, iXLen 1)
1299
1300  ret <vscale x 1 x i64> %a
1301}
1302
1303declare <vscale x 2 x i64> @llvm.riscv.vwmul.nxv2i64.nxv2i32.i32(
1304  <vscale x 2 x i64>,
1305  <vscale x 2 x i32>,
1306  i32,
1307  iXLen);
1308
1309define <vscale x 2 x i64> @intrinsic_vwmul_vx_nxv2i64_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1, iXLen %2) nounwind {
1310; CHECK-LABEL: intrinsic_vwmul_vx_nxv2i64_nxv2i32_i32:
1311; CHECK:       # %bb.0: # %entry
1312; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma
1313; CHECK-NEXT:    vwmul.vx v10, v8, a0
1314; CHECK-NEXT:    vmv2r.v v8, v10
1315; CHECK-NEXT:    ret
1316entry:
1317  %a = call <vscale x 2 x i64> @llvm.riscv.vwmul.nxv2i64.nxv2i32.i32(
1318    <vscale x 2 x i64> undef,
1319    <vscale x 2 x i32> %0,
1320    i32 %1,
1321    iXLen %2)
1322
1323  ret <vscale x 2 x i64> %a
1324}
1325
1326declare <vscale x 2 x i64> @llvm.riscv.vwmul.mask.nxv2i64.nxv2i32.i32(
1327  <vscale x 2 x i64>,
1328  <vscale x 2 x i32>,
1329  i32,
1330  <vscale x 2 x i1>,
1331  iXLen,
1332  iXLen);
1333
1334define <vscale x 2 x i64> @intrinsic_vwmul_mask_vx_nxv2i64_nxv2i32_i32(<vscale x 2 x i64> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
1335; CHECK-LABEL: intrinsic_vwmul_mask_vx_nxv2i64_nxv2i32_i32:
1336; CHECK:       # %bb.0: # %entry
1337; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, mu
1338; CHECK-NEXT:    vwmul.vx v8, v10, a0, v0.t
1339; CHECK-NEXT:    ret
1340entry:
1341  %a = call <vscale x 2 x i64> @llvm.riscv.vwmul.mask.nxv2i64.nxv2i32.i32(
1342    <vscale x 2 x i64> %0,
1343    <vscale x 2 x i32> %1,
1344    i32 %2,
1345    <vscale x 2 x i1> %3,
1346    iXLen %4, iXLen 1)
1347
1348  ret <vscale x 2 x i64> %a
1349}
1350
1351declare <vscale x 4 x i64> @llvm.riscv.vwmul.nxv4i64.nxv4i32.i32(
1352  <vscale x 4 x i64>,
1353  <vscale x 4 x i32>,
1354  i32,
1355  iXLen);
1356
1357define <vscale x 4 x i64> @intrinsic_vwmul_vx_nxv4i64_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1, iXLen %2) nounwind {
1358; CHECK-LABEL: intrinsic_vwmul_vx_nxv4i64_nxv4i32_i32:
1359; CHECK:       # %bb.0: # %entry
1360; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma
1361; CHECK-NEXT:    vwmul.vx v12, v8, a0
1362; CHECK-NEXT:    vmv4r.v v8, v12
1363; CHECK-NEXT:    ret
1364entry:
1365  %a = call <vscale x 4 x i64> @llvm.riscv.vwmul.nxv4i64.nxv4i32.i32(
1366    <vscale x 4 x i64> undef,
1367    <vscale x 4 x i32> %0,
1368    i32 %1,
1369    iXLen %2)
1370
1371  ret <vscale x 4 x i64> %a
1372}
1373
1374declare <vscale x 4 x i64> @llvm.riscv.vwmul.mask.nxv4i64.nxv4i32.i32(
1375  <vscale x 4 x i64>,
1376  <vscale x 4 x i32>,
1377  i32,
1378  <vscale x 4 x i1>,
1379  iXLen,
1380  iXLen);
1381
1382define <vscale x 4 x i64> @intrinsic_vwmul_mask_vx_nxv4i64_nxv4i32_i32(<vscale x 4 x i64> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
1383; CHECK-LABEL: intrinsic_vwmul_mask_vx_nxv4i64_nxv4i32_i32:
1384; CHECK:       # %bb.0: # %entry
1385; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, mu
1386; CHECK-NEXT:    vwmul.vx v8, v12, a0, v0.t
1387; CHECK-NEXT:    ret
1388entry:
1389  %a = call <vscale x 4 x i64> @llvm.riscv.vwmul.mask.nxv4i64.nxv4i32.i32(
1390    <vscale x 4 x i64> %0,
1391    <vscale x 4 x i32> %1,
1392    i32 %2,
1393    <vscale x 4 x i1> %3,
1394    iXLen %4, iXLen 1)
1395
1396  ret <vscale x 4 x i64> %a
1397}
1398
1399declare <vscale x 8 x i64> @llvm.riscv.vwmul.nxv8i64.nxv8i32.i32(
1400  <vscale x 8 x i64>,
1401  <vscale x 8 x i32>,
1402  i32,
1403  iXLen);
1404
1405define <vscale x 8 x i64> @intrinsic_vwmul_vx_nxv8i64_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1, iXLen %2) nounwind {
1406; CHECK-LABEL: intrinsic_vwmul_vx_nxv8i64_nxv8i32_i32:
1407; CHECK:       # %bb.0: # %entry
1408; CHECK-NEXT:    vsetvli zero, a1, e32, m4, ta, ma
1409; CHECK-NEXT:    vwmul.vx v16, v8, a0
1410; CHECK-NEXT:    vmv8r.v v8, v16
1411; CHECK-NEXT:    ret
1412entry:
1413  %a = call <vscale x 8 x i64> @llvm.riscv.vwmul.nxv8i64.nxv8i32.i32(
1414    <vscale x 8 x i64> undef,
1415    <vscale x 8 x i32> %0,
1416    i32 %1,
1417    iXLen %2)
1418
1419  ret <vscale x 8 x i64> %a
1420}
1421
1422declare <vscale x 8 x i64> @llvm.riscv.vwmul.mask.nxv8i64.nxv8i32.i32(
1423  <vscale x 8 x i64>,
1424  <vscale x 8 x i32>,
1425  i32,
1426  <vscale x 8 x i1>,
1427  iXLen,
1428  iXLen);
1429
1430define <vscale x 8 x i64> @intrinsic_vwmul_mask_vx_nxv8i64_nxv8i32_i32(<vscale x 8 x i64> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
1431; CHECK-LABEL: intrinsic_vwmul_mask_vx_nxv8i64_nxv8i32_i32:
1432; CHECK:       # %bb.0: # %entry
1433; CHECK-NEXT:    vsetvli zero, a1, e32, m4, ta, mu
1434; CHECK-NEXT:    vwmul.vx v8, v16, a0, v0.t
1435; CHECK-NEXT:    ret
1436entry:
1437  %a = call <vscale x 8 x i64> @llvm.riscv.vwmul.mask.nxv8i64.nxv8i32.i32(
1438    <vscale x 8 x i64> %0,
1439    <vscale x 8 x i32> %1,
1440    i32 %2,
1441    <vscale x 8 x i1> %3,
1442    iXLen %4, iXLen 1)
1443
1444  ret <vscale x 8 x i64> %a
1445}
1446