xref: /llvm-project/llvm/test/CodeGen/RISCV/rvv/vwmul-sdnode.ll (revision 87519a2830eab4b634a5816f53fe773929eed531) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s
3; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s
4
5define <vscale x 1 x i64> @vwmul_vv_nxv1i64_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb) {
6; CHECK-LABEL: vwmul_vv_nxv1i64_nxv1i32:
7; CHECK:       # %bb.0:
8; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, ma
9; CHECK-NEXT:    vwmul.vv v10, v8, v9
10; CHECK-NEXT:    vmv1r.v v8, v10
11; CHECK-NEXT:    ret
12  %vc = sext <vscale x 1 x i32> %va to <vscale x 1 x i64>
13  %vd = sext <vscale x 1 x i32> %vb to <vscale x 1 x i64>
14  %ve = mul <vscale x 1 x i64> %vc, %vd
15  ret <vscale x 1 x i64> %ve
16}
17
18define <vscale x 1 x i64> @vwmulu_vv_nxv1i64_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb) {
19; CHECK-LABEL: vwmulu_vv_nxv1i64_nxv1i32:
20; CHECK:       # %bb.0:
21; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, ma
22; CHECK-NEXT:    vwmulu.vv v10, v8, v9
23; CHECK-NEXT:    vmv1r.v v8, v10
24; CHECK-NEXT:    ret
25  %vc = zext <vscale x 1 x i32> %va to <vscale x 1 x i64>
26  %vd = zext <vscale x 1 x i32> %vb to <vscale x 1 x i64>
27  %ve = mul <vscale x 1 x i64> %vc, %vd
28  ret <vscale x 1 x i64> %ve
29}
30
31define <vscale x 1 x i64> @vwmulsu_vv_nxv1i64_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb) {
32; CHECK-LABEL: vwmulsu_vv_nxv1i64_nxv1i32:
33; CHECK:       # %bb.0:
34; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, ma
35; CHECK-NEXT:    vwmulsu.vv v10, v8, v9
36; CHECK-NEXT:    vmv1r.v v8, v10
37; CHECK-NEXT:    ret
38  %vc = sext <vscale x 1 x i32> %va to <vscale x 1 x i64>
39  %vd = zext <vscale x 1 x i32> %vb to <vscale x 1 x i64>
40  %ve = mul <vscale x 1 x i64> %vc, %vd
41  ret <vscale x 1 x i64> %ve
42}
43
44define <vscale x 1 x i64> @vwmul_vx_nxv1i64_nxv1i32(<vscale x 1 x i32> %va, i32 %b) {
45; CHECK-LABEL: vwmul_vx_nxv1i64_nxv1i32:
46; CHECK:       # %bb.0:
47; CHECK-NEXT:    vsetvli a1, zero, e32, mf2, ta, ma
48; CHECK-NEXT:    vwmul.vx v9, v8, a0
49; CHECK-NEXT:    vmv1r.v v8, v9
50; CHECK-NEXT:    ret
51  %head = insertelement <vscale x 1 x i32> undef, i32 %b, i32 0
52  %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
53  %vc = sext <vscale x 1 x i32> %va to <vscale x 1 x i64>
54  %vd = sext <vscale x 1 x i32> %splat to <vscale x 1 x i64>
55  %ve = mul <vscale x 1 x i64> %vc, %vd
56  ret <vscale x 1 x i64> %ve
57}
58
59define <vscale x 1 x i64> @vwmulu_vx_nxv1i64_nxv1i32(<vscale x 1 x i32> %va, i32 %b) {
60; CHECK-LABEL: vwmulu_vx_nxv1i64_nxv1i32:
61; CHECK:       # %bb.0:
62; CHECK-NEXT:    vsetvli a1, zero, e32, mf2, ta, ma
63; CHECK-NEXT:    vwmulu.vx v9, v8, a0
64; CHECK-NEXT:    vmv1r.v v8, v9
65; CHECK-NEXT:    ret
66  %head = insertelement <vscale x 1 x i32> undef, i32 %b, i32 0
67  %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
68  %vc = zext <vscale x 1 x i32> %va to <vscale x 1 x i64>
69  %vd = zext <vscale x 1 x i32> %splat to <vscale x 1 x i64>
70  %ve = mul <vscale x 1 x i64> %vc, %vd
71  ret <vscale x 1 x i64> %ve
72}
73
74define <vscale x 1 x i64> @vwmulsu_vx_nxv1i64_nxv1i32(<vscale x 1 x i32> %va, i32 %b) {
75; CHECK-LABEL: vwmulsu_vx_nxv1i64_nxv1i32:
76; CHECK:       # %bb.0:
77; CHECK-NEXT:    vsetvli a1, zero, e32, mf2, ta, ma
78; CHECK-NEXT:    vwmulsu.vx v9, v8, a0
79; CHECK-NEXT:    vmv1r.v v8, v9
80; CHECK-NEXT:    ret
81  %head = insertelement <vscale x 1 x i32> undef, i32 %b, i32 0
82  %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
83  %vc = sext <vscale x 1 x i32> %va to <vscale x 1 x i64>
84  %vd = zext <vscale x 1 x i32> %splat to <vscale x 1 x i64>
85  %ve = mul <vscale x 1 x i64> %vc, %vd
86  ret <vscale x 1 x i64> %ve
87}
88
89define <vscale x 2 x i64> @vwmul_vv_nxv2i64_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb) {
90; CHECK-LABEL: vwmul_vv_nxv2i64_nxv2i32:
91; CHECK:       # %bb.0:
92; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, ma
93; CHECK-NEXT:    vwmul.vv v10, v8, v9
94; CHECK-NEXT:    vmv2r.v v8, v10
95; CHECK-NEXT:    ret
96  %vc = sext <vscale x 2 x i32> %va to <vscale x 2 x i64>
97  %vd = sext <vscale x 2 x i32> %vb to <vscale x 2 x i64>
98  %ve = mul <vscale x 2 x i64> %vc, %vd
99  ret <vscale x 2 x i64> %ve
100}
101
102define <vscale x 2 x i64> @vwmulu_vv_nxv2i64_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb) {
103; CHECK-LABEL: vwmulu_vv_nxv2i64_nxv2i32:
104; CHECK:       # %bb.0:
105; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, ma
106; CHECK-NEXT:    vwmulu.vv v10, v8, v9
107; CHECK-NEXT:    vmv2r.v v8, v10
108; CHECK-NEXT:    ret
109  %vc = zext <vscale x 2 x i32> %va to <vscale x 2 x i64>
110  %vd = zext <vscale x 2 x i32> %vb to <vscale x 2 x i64>
111  %ve = mul <vscale x 2 x i64> %vc, %vd
112  ret <vscale x 2 x i64> %ve
113}
114
115define <vscale x 2 x i64> @vwmulsu_vv_nxv2i64_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb) {
116; CHECK-LABEL: vwmulsu_vv_nxv2i64_nxv2i32:
117; CHECK:       # %bb.0:
118; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, ma
119; CHECK-NEXT:    vwmulsu.vv v10, v8, v9
120; CHECK-NEXT:    vmv2r.v v8, v10
121; CHECK-NEXT:    ret
122  %vc = sext <vscale x 2 x i32> %va to <vscale x 2 x i64>
123  %vd = zext <vscale x 2 x i32> %vb to <vscale x 2 x i64>
124  %ve = mul <vscale x 2 x i64> %vc, %vd
125  ret <vscale x 2 x i64> %ve
126}
127
128define <vscale x 2 x i64> @vwmul_vx_nxv2i64_nxv2i32(<vscale x 2 x i32> %va, i32 %b) {
129; CHECK-LABEL: vwmul_vx_nxv2i64_nxv2i32:
130; CHECK:       # %bb.0:
131; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, ma
132; CHECK-NEXT:    vwmul.vx v10, v8, a0
133; CHECK-NEXT:    vmv2r.v v8, v10
134; CHECK-NEXT:    ret
135  %head = insertelement <vscale x 2 x i32> undef, i32 %b, i32 0
136  %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
137  %vc = sext <vscale x 2 x i32> %va to <vscale x 2 x i64>
138  %vd = sext <vscale x 2 x i32> %splat to <vscale x 2 x i64>
139  %ve = mul <vscale x 2 x i64> %vc, %vd
140  ret <vscale x 2 x i64> %ve
141}
142
143define <vscale x 2 x i64> @vwmulu_vx_nxv2i64_nxv2i32(<vscale x 2 x i32> %va, i32 %b) {
144; CHECK-LABEL: vwmulu_vx_nxv2i64_nxv2i32:
145; CHECK:       # %bb.0:
146; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, ma
147; CHECK-NEXT:    vwmulu.vx v10, v8, a0
148; CHECK-NEXT:    vmv2r.v v8, v10
149; CHECK-NEXT:    ret
150  %head = insertelement <vscale x 2 x i32> undef, i32 %b, i32 0
151  %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
152  %vc = zext <vscale x 2 x i32> %va to <vscale x 2 x i64>
153  %vd = zext <vscale x 2 x i32> %splat to <vscale x 2 x i64>
154  %ve = mul <vscale x 2 x i64> %vc, %vd
155  ret <vscale x 2 x i64> %ve
156}
157
158define <vscale x 2 x i64> @vwmulsu_vx_nxv2i64_nxv2i32(<vscale x 2 x i32> %va, i32 %b) {
159; CHECK-LABEL: vwmulsu_vx_nxv2i64_nxv2i32:
160; CHECK:       # %bb.0:
161; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, ma
162; CHECK-NEXT:    vwmulsu.vx v10, v8, a0
163; CHECK-NEXT:    vmv2r.v v8, v10
164; CHECK-NEXT:    ret
165  %head = insertelement <vscale x 2 x i32> undef, i32 %b, i32 0
166  %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
167  %vc = sext <vscale x 2 x i32> %va to <vscale x 2 x i64>
168  %vd = zext <vscale x 2 x i32> %splat to <vscale x 2 x i64>
169  %ve = mul <vscale x 2 x i64> %vc, %vd
170  ret <vscale x 2 x i64> %ve
171}
172
173define <vscale x 4 x i64> @vwmul_vv_nxv4i64_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb) {
174; CHECK-LABEL: vwmul_vv_nxv4i64_nxv4i32:
175; CHECK:       # %bb.0:
176; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, ma
177; CHECK-NEXT:    vwmul.vv v12, v8, v10
178; CHECK-NEXT:    vmv4r.v v8, v12
179; CHECK-NEXT:    ret
180  %vc = sext <vscale x 4 x i32> %va to <vscale x 4 x i64>
181  %vd = sext <vscale x 4 x i32> %vb to <vscale x 4 x i64>
182  %ve = mul <vscale x 4 x i64> %vc, %vd
183  ret <vscale x 4 x i64> %ve
184}
185
186define <vscale x 4 x i64> @vwmulu_vv_nxv4i64_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb) {
187; CHECK-LABEL: vwmulu_vv_nxv4i64_nxv4i32:
188; CHECK:       # %bb.0:
189; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, ma
190; CHECK-NEXT:    vwmulu.vv v12, v8, v10
191; CHECK-NEXT:    vmv4r.v v8, v12
192; CHECK-NEXT:    ret
193  %vc = zext <vscale x 4 x i32> %va to <vscale x 4 x i64>
194  %vd = zext <vscale x 4 x i32> %vb to <vscale x 4 x i64>
195  %ve = mul <vscale x 4 x i64> %vc, %vd
196  ret <vscale x 4 x i64> %ve
197}
198
199define <vscale x 4 x i64> @vwmulsu_vv_nxv4i64_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb) {
200; CHECK-LABEL: vwmulsu_vv_nxv4i64_nxv4i32:
201; CHECK:       # %bb.0:
202; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, ma
203; CHECK-NEXT:    vwmulsu.vv v12, v8, v10
204; CHECK-NEXT:    vmv4r.v v8, v12
205; CHECK-NEXT:    ret
206  %vc = sext <vscale x 4 x i32> %va to <vscale x 4 x i64>
207  %vd = zext <vscale x 4 x i32> %vb to <vscale x 4 x i64>
208  %ve = mul <vscale x 4 x i64> %vc, %vd
209  ret <vscale x 4 x i64> %ve
210}
211
212define <vscale x 4 x i64> @vwmul_vx_nxv4i64_nxv4i32(<vscale x 4 x i32> %va, i32 %b) {
213; CHECK-LABEL: vwmul_vx_nxv4i64_nxv4i32:
214; CHECK:       # %bb.0:
215; CHECK-NEXT:    vsetvli a1, zero, e32, m2, ta, ma
216; CHECK-NEXT:    vwmul.vx v12, v8, a0
217; CHECK-NEXT:    vmv4r.v v8, v12
218; CHECK-NEXT:    ret
219  %head = insertelement <vscale x 4 x i32> undef, i32 %b, i32 0
220  %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
221  %vc = sext <vscale x 4 x i32> %va to <vscale x 4 x i64>
222  %vd = sext <vscale x 4 x i32> %splat to <vscale x 4 x i64>
223  %ve = mul <vscale x 4 x i64> %vc, %vd
224  ret <vscale x 4 x i64> %ve
225}
226
227define <vscale x 4 x i64> @vwmulu_vx_nxv4i64_nxv4i32(<vscale x 4 x i32> %va, i32 %b) {
228; CHECK-LABEL: vwmulu_vx_nxv4i64_nxv4i32:
229; CHECK:       # %bb.0:
230; CHECK-NEXT:    vsetvli a1, zero, e32, m2, ta, ma
231; CHECK-NEXT:    vwmulu.vx v12, v8, a0
232; CHECK-NEXT:    vmv4r.v v8, v12
233; CHECK-NEXT:    ret
234  %head = insertelement <vscale x 4 x i32> undef, i32 %b, i32 0
235  %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
236  %vc = zext <vscale x 4 x i32> %va to <vscale x 4 x i64>
237  %vd = zext <vscale x 4 x i32> %splat to <vscale x 4 x i64>
238  %ve = mul <vscale x 4 x i64> %vc, %vd
239  ret <vscale x 4 x i64> %ve
240}
241
242define <vscale x 4 x i64> @vwmulsu_vx_nxv4i64_nxv4i32(<vscale x 4 x i32> %va, i32 %b) {
243; CHECK-LABEL: vwmulsu_vx_nxv4i64_nxv4i32:
244; CHECK:       # %bb.0:
245; CHECK-NEXT:    vsetvli a1, zero, e32, m2, ta, ma
246; CHECK-NEXT:    vwmulsu.vx v12, v8, a0
247; CHECK-NEXT:    vmv4r.v v8, v12
248; CHECK-NEXT:    ret
249  %head = insertelement <vscale x 4 x i32> undef, i32 %b, i32 0
250  %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
251  %vc = sext <vscale x 4 x i32> %va to <vscale x 4 x i64>
252  %vd = zext <vscale x 4 x i32> %splat to <vscale x 4 x i64>
253  %ve = mul <vscale x 4 x i64> %vc, %vd
254  ret <vscale x 4 x i64> %ve
255}
256
257define <vscale x 8 x i64> @vwmul_vv_nxv8i64_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {
258; CHECK-LABEL: vwmul_vv_nxv8i64_nxv8i32:
259; CHECK:       # %bb.0:
260; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, ma
261; CHECK-NEXT:    vwmul.vv v16, v8, v12
262; CHECK-NEXT:    vmv8r.v v8, v16
263; CHECK-NEXT:    ret
264  %vc = sext <vscale x 8 x i32> %va to <vscale x 8 x i64>
265  %vd = sext <vscale x 8 x i32> %vb to <vscale x 8 x i64>
266  %ve = mul <vscale x 8 x i64> %vc, %vd
267  ret <vscale x 8 x i64> %ve
268}
269
270define <vscale x 8 x i64> @vwmulu_vv_nxv8i64_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {
271; CHECK-LABEL: vwmulu_vv_nxv8i64_nxv8i32:
272; CHECK:       # %bb.0:
273; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, ma
274; CHECK-NEXT:    vwmulu.vv v16, v8, v12
275; CHECK-NEXT:    vmv8r.v v8, v16
276; CHECK-NEXT:    ret
277  %vc = zext <vscale x 8 x i32> %va to <vscale x 8 x i64>
278  %vd = zext <vscale x 8 x i32> %vb to <vscale x 8 x i64>
279  %ve = mul <vscale x 8 x i64> %vc, %vd
280  ret <vscale x 8 x i64> %ve
281}
282
283define <vscale x 8 x i64> @vwmulsu_vv_nxv8i64_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {
284; CHECK-LABEL: vwmulsu_vv_nxv8i64_nxv8i32:
285; CHECK:       # %bb.0:
286; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, ma
287; CHECK-NEXT:    vwmulsu.vv v16, v8, v12
288; CHECK-NEXT:    vmv8r.v v8, v16
289; CHECK-NEXT:    ret
290  %vc = sext <vscale x 8 x i32> %va to <vscale x 8 x i64>
291  %vd = zext <vscale x 8 x i32> %vb to <vscale x 8 x i64>
292  %ve = mul <vscale x 8 x i64> %vc, %vd
293  ret <vscale x 8 x i64> %ve
294}
295
296define <vscale x 8 x i64> @vwmul_vx_nxv8i64_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
297; CHECK-LABEL: vwmul_vx_nxv8i64_nxv8i32:
298; CHECK:       # %bb.0:
299; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, ma
300; CHECK-NEXT:    vwmul.vx v16, v8, a0
301; CHECK-NEXT:    vmv8r.v v8, v16
302; CHECK-NEXT:    ret
303  %head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
304  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
305  %vc = sext <vscale x 8 x i32> %va to <vscale x 8 x i64>
306  %vd = sext <vscale x 8 x i32> %splat to <vscale x 8 x i64>
307  %ve = mul <vscale x 8 x i64> %vc, %vd
308  ret <vscale x 8 x i64> %ve
309}
310
311define <vscale x 8 x i64> @vwmulu_vx_nxv8i64_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
312; CHECK-LABEL: vwmulu_vx_nxv8i64_nxv8i32:
313; CHECK:       # %bb.0:
314; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, ma
315; CHECK-NEXT:    vwmulu.vx v16, v8, a0
316; CHECK-NEXT:    vmv8r.v v8, v16
317; CHECK-NEXT:    ret
318  %head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
319  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
320  %vc = zext <vscale x 8 x i32> %va to <vscale x 8 x i64>
321  %vd = zext <vscale x 8 x i32> %splat to <vscale x 8 x i64>
322  %ve = mul <vscale x 8 x i64> %vc, %vd
323  ret <vscale x 8 x i64> %ve
324}
325
326define <vscale x 8 x i64> @vwmulsu_vx_nxv8i64_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
327; CHECK-LABEL: vwmulsu_vx_nxv8i64_nxv8i32:
328; CHECK:       # %bb.0:
329; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, ma
330; CHECK-NEXT:    vwmulsu.vx v16, v8, a0
331; CHECK-NEXT:    vmv8r.v v8, v16
332; CHECK-NEXT:    ret
333  %head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
334  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
335  %vc = sext <vscale x 8 x i32> %va to <vscale x 8 x i64>
336  %vd = zext <vscale x 8 x i32> %splat to <vscale x 8 x i64>
337  %ve = mul <vscale x 8 x i64> %vc, %vd
338  ret <vscale x 8 x i64> %ve
339}
340
341define <vscale x 1 x i64> @vwmul_vv_nxv1i64_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %vb) {
342; CHECK-LABEL: vwmul_vv_nxv1i64_nxv1i16:
343; CHECK:       # %bb.0:
344; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, ma
345; CHECK-NEXT:    vsext.vf2 v10, v8
346; CHECK-NEXT:    vsext.vf2 v11, v9
347; CHECK-NEXT:    vwmul.vv v8, v10, v11
348; CHECK-NEXT:    ret
349  %vc = sext <vscale x 1 x i16> %va to <vscale x 1 x i64>
350  %vd = sext <vscale x 1 x i16> %vb to <vscale x 1 x i64>
351  %ve = mul <vscale x 1 x i64> %vc, %vd
352  ret <vscale x 1 x i64> %ve
353}
354
355define <vscale x 1 x i64> @vwmulu_vv_nxv1i64_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %vb) {
356; CHECK-LABEL: vwmulu_vv_nxv1i64_nxv1i16:
357; CHECK:       # %bb.0:
358; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, ma
359; CHECK-NEXT:    vwmulu.vv v10, v8, v9
360; CHECK-NEXT:    vsetvli zero, zero, e64, m1, ta, ma
361; CHECK-NEXT:    vzext.vf2 v8, v10
362; CHECK-NEXT:    ret
363  %vc = zext <vscale x 1 x i16> %va to <vscale x 1 x i64>
364  %vd = zext <vscale x 1 x i16> %vb to <vscale x 1 x i64>
365  %ve = mul <vscale x 1 x i64> %vc, %vd
366  ret <vscale x 1 x i64> %ve
367}
368
369define <vscale x 1 x i64> @vwmulsu_vv_nxv1i64_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %vb) {
370; CHECK-LABEL: vwmulsu_vv_nxv1i64_nxv1i16:
371; CHECK:       # %bb.0:
372; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, ma
373; CHECK-NEXT:    vsext.vf2 v10, v8
374; CHECK-NEXT:    vzext.vf2 v11, v9
375; CHECK-NEXT:    vwmulsu.vv v8, v10, v11
376; CHECK-NEXT:    ret
377  %vc = sext <vscale x 1 x i16> %va to <vscale x 1 x i64>
378  %vd = zext <vscale x 1 x i16> %vb to <vscale x 1 x i64>
379  %ve = mul <vscale x 1 x i64> %vc, %vd
380  ret <vscale x 1 x i64> %ve
381}
382
383define <vscale x 1 x i64> @vwmul_vx_nxv1i64_nxv1i16(<vscale x 1 x i16> %va, i16 %b) {
384; CHECK-LABEL: vwmul_vx_nxv1i64_nxv1i16:
385; CHECK:       # %bb.0:
386; CHECK-NEXT:    vsetvli a1, zero, e16, mf4, ta, ma
387; CHECK-NEXT:    vmv.v.x v9, a0
388; CHECK-NEXT:    vsetvli zero, zero, e32, mf2, ta, ma
389; CHECK-NEXT:    vsext.vf2 v10, v8
390; CHECK-NEXT:    vsext.vf2 v11, v9
391; CHECK-NEXT:    vwmul.vv v8, v10, v11
392; CHECK-NEXT:    ret
393  %head = insertelement <vscale x 1 x i16> undef, i16 %b, i16 0
394  %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
395  %vc = sext <vscale x 1 x i16> %va to <vscale x 1 x i64>
396  %vd = sext <vscale x 1 x i16> %splat to <vscale x 1 x i64>
397  %ve = mul <vscale x 1 x i64> %vc, %vd
398  ret <vscale x 1 x i64> %ve
399}
400
401define <vscale x 1 x i64> @vwmulu_vx_nxv1i64_nxv1i16(<vscale x 1 x i16> %va, i16 %b) {
402; CHECK-LABEL: vwmulu_vx_nxv1i64_nxv1i16:
403; CHECK:       # %bb.0:
404; CHECK-NEXT:    vsetvli a1, zero, e16, mf4, ta, ma
405; CHECK-NEXT:    vwmulu.vx v9, v8, a0
406; CHECK-NEXT:    vsetvli zero, zero, e64, m1, ta, ma
407; CHECK-NEXT:    vzext.vf2 v8, v9
408; CHECK-NEXT:    ret
409  %head = insertelement <vscale x 1 x i16> undef, i16 %b, i16 0
410  %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
411  %vc = zext <vscale x 1 x i16> %va to <vscale x 1 x i64>
412  %vd = zext <vscale x 1 x i16> %splat to <vscale x 1 x i64>
413  %ve = mul <vscale x 1 x i64> %vc, %vd
414  ret <vscale x 1 x i64> %ve
415}
416
417define <vscale x 1 x i64> @vwmulsu_vx_nxv1i64_nxv1i16(<vscale x 1 x i16> %va, i16 %b) {
418; CHECK-LABEL: vwmulsu_vx_nxv1i64_nxv1i16:
419; CHECK:       # %bb.0:
420; CHECK-NEXT:    vsetvli a1, zero, e16, mf4, ta, ma
421; CHECK-NEXT:    vmv.v.x v9, a0
422; CHECK-NEXT:    vsetvli zero, zero, e32, mf2, ta, ma
423; CHECK-NEXT:    vsext.vf2 v10, v8
424; CHECK-NEXT:    vzext.vf2 v11, v9
425; CHECK-NEXT:    vwmulsu.vv v8, v10, v11
426; CHECK-NEXT:    ret
427  %head = insertelement <vscale x 1 x i16> undef, i16 %b, i16 0
428  %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
429  %vc = sext <vscale x 1 x i16> %va to <vscale x 1 x i64>
430  %vd = zext <vscale x 1 x i16> %splat to <vscale x 1 x i64>
431  %ve = mul <vscale x 1 x i64> %vc, %vd
432  ret <vscale x 1 x i64> %ve
433}
434
435define <vscale x 2 x i64> @vwmul_vv_nxv2i64_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %vb) {
436; CHECK-LABEL: vwmul_vv_nxv2i64_nxv2i16:
437; CHECK:       # %bb.0:
438; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, ma
439; CHECK-NEXT:    vsext.vf2 v10, v8
440; CHECK-NEXT:    vsext.vf2 v11, v9
441; CHECK-NEXT:    vwmul.vv v8, v10, v11
442; CHECK-NEXT:    ret
443  %vc = sext <vscale x 2 x i16> %va to <vscale x 2 x i64>
444  %vd = sext <vscale x 2 x i16> %vb to <vscale x 2 x i64>
445  %ve = mul <vscale x 2 x i64> %vc, %vd
446  ret <vscale x 2 x i64> %ve
447}
448
449define <vscale x 2 x i64> @vwmulu_vv_nxv2i64_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %vb) {
450; CHECK-LABEL: vwmulu_vv_nxv2i64_nxv2i16:
451; CHECK:       # %bb.0:
452; CHECK-NEXT:    vsetvli a0, zero, e16, mf2, ta, ma
453; CHECK-NEXT:    vwmulu.vv v10, v8, v9
454; CHECK-NEXT:    vsetvli zero, zero, e64, m2, ta, ma
455; CHECK-NEXT:    vzext.vf2 v8, v10
456; CHECK-NEXT:    ret
457  %vc = zext <vscale x 2 x i16> %va to <vscale x 2 x i64>
458  %vd = zext <vscale x 2 x i16> %vb to <vscale x 2 x i64>
459  %ve = mul <vscale x 2 x i64> %vc, %vd
460  ret <vscale x 2 x i64> %ve
461}
462
463define <vscale x 2 x i64> @vwmulsu_vv_nxv2i64_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %vb) {
464; CHECK-LABEL: vwmulsu_vv_nxv2i64_nxv2i16:
465; CHECK:       # %bb.0:
466; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, ma
467; CHECK-NEXT:    vsext.vf2 v10, v8
468; CHECK-NEXT:    vzext.vf2 v11, v9
469; CHECK-NEXT:    vwmulsu.vv v8, v10, v11
470; CHECK-NEXT:    ret
471  %vc = sext <vscale x 2 x i16> %va to <vscale x 2 x i64>
472  %vd = zext <vscale x 2 x i16> %vb to <vscale x 2 x i64>
473  %ve = mul <vscale x 2 x i64> %vc, %vd
474  ret <vscale x 2 x i64> %ve
475}
476
477define <vscale x 2 x i64> @vwmul_vx_nxv2i64_nxv2i16(<vscale x 2 x i16> %va, i16 %b) {
478; CHECK-LABEL: vwmul_vx_nxv2i64_nxv2i16:
479; CHECK:       # %bb.0:
480; CHECK-NEXT:    vsetvli a1, zero, e16, mf2, ta, ma
481; CHECK-NEXT:    vmv.v.x v9, a0
482; CHECK-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
483; CHECK-NEXT:    vsext.vf2 v10, v8
484; CHECK-NEXT:    vsext.vf2 v11, v9
485; CHECK-NEXT:    vwmul.vv v8, v10, v11
486; CHECK-NEXT:    ret
487  %head = insertelement <vscale x 2 x i16> undef, i16 %b, i16 0
488  %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
489  %vc = sext <vscale x 2 x i16> %va to <vscale x 2 x i64>
490  %vd = sext <vscale x 2 x i16> %splat to <vscale x 2 x i64>
491  %ve = mul <vscale x 2 x i64> %vc, %vd
492  ret <vscale x 2 x i64> %ve
493}
494
495define <vscale x 2 x i64> @vwmulu_vx_nxv2i64_nxv2i16(<vscale x 2 x i16> %va, i16 %b) {
496; CHECK-LABEL: vwmulu_vx_nxv2i64_nxv2i16:
497; CHECK:       # %bb.0:
498; CHECK-NEXT:    vsetvli a1, zero, e16, mf2, ta, ma
499; CHECK-NEXT:    vwmulu.vx v10, v8, a0
500; CHECK-NEXT:    vsetvli zero, zero, e64, m2, ta, ma
501; CHECK-NEXT:    vzext.vf2 v8, v10
502; CHECK-NEXT:    ret
503  %head = insertelement <vscale x 2 x i16> undef, i16 %b, i16 0
504  %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
505  %vc = zext <vscale x 2 x i16> %va to <vscale x 2 x i64>
506  %vd = zext <vscale x 2 x i16> %splat to <vscale x 2 x i64>
507  %ve = mul <vscale x 2 x i64> %vc, %vd
508  ret <vscale x 2 x i64> %ve
509}
510
511define <vscale x 2 x i64> @vwmulsu_vx_nxv2i64_nxv2i16(<vscale x 2 x i16> %va, i16 %b) {
512; CHECK-LABEL: vwmulsu_vx_nxv2i64_nxv2i16:
513; CHECK:       # %bb.0:
514; CHECK-NEXT:    vsetvli a1, zero, e16, mf2, ta, ma
515; CHECK-NEXT:    vmv.v.x v9, a0
516; CHECK-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
517; CHECK-NEXT:    vsext.vf2 v10, v8
518; CHECK-NEXT:    vzext.vf2 v11, v9
519; CHECK-NEXT:    vwmulsu.vv v8, v10, v11
520; CHECK-NEXT:    ret
521  %head = insertelement <vscale x 2 x i16> undef, i16 %b, i16 0
522  %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
523  %vc = sext <vscale x 2 x i16> %va to <vscale x 2 x i64>
524  %vd = zext <vscale x 2 x i16> %splat to <vscale x 2 x i64>
525  %ve = mul <vscale x 2 x i64> %vc, %vd
526  ret <vscale x 2 x i64> %ve
527}
528
529define <vscale x 4 x i64> @vwmul_vv_nxv4i64_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %vb) {
530; CHECK-LABEL: vwmul_vv_nxv4i64_nxv4i16:
531; CHECK:       # %bb.0:
532; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, ma
533; CHECK-NEXT:    vsext.vf2 v12, v8
534; CHECK-NEXT:    vsext.vf2 v14, v9
535; CHECK-NEXT:    vwmul.vv v8, v12, v14
536; CHECK-NEXT:    ret
537  %vc = sext <vscale x 4 x i16> %va to <vscale x 4 x i64>
538  %vd = sext <vscale x 4 x i16> %vb to <vscale x 4 x i64>
539  %ve = mul <vscale x 4 x i64> %vc, %vd
540  ret <vscale x 4 x i64> %ve
541}
542
543define <vscale x 4 x i64> @vwmulu_vv_nxv4i64_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %vb) {
544; CHECK-LABEL: vwmulu_vv_nxv4i64_nxv4i16:
545; CHECK:       # %bb.0:
546; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, ma
547; CHECK-NEXT:    vwmulu.vv v12, v8, v9
548; CHECK-NEXT:    vsetvli zero, zero, e64, m4, ta, ma
549; CHECK-NEXT:    vzext.vf2 v8, v12
550; CHECK-NEXT:    ret
551  %vc = zext <vscale x 4 x i16> %va to <vscale x 4 x i64>
552  %vd = zext <vscale x 4 x i16> %vb to <vscale x 4 x i64>
553  %ve = mul <vscale x 4 x i64> %vc, %vd
554  ret <vscale x 4 x i64> %ve
555}
556
557define <vscale x 4 x i64> @vwmulsu_vv_nxv4i64_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %vb) {
558; CHECK-LABEL: vwmulsu_vv_nxv4i64_nxv4i16:
559; CHECK:       # %bb.0:
560; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, ma
561; CHECK-NEXT:    vsext.vf2 v12, v8
562; CHECK-NEXT:    vzext.vf2 v14, v9
563; CHECK-NEXT:    vwmulsu.vv v8, v12, v14
564; CHECK-NEXT:    ret
565  %vc = sext <vscale x 4 x i16> %va to <vscale x 4 x i64>
566  %vd = zext <vscale x 4 x i16> %vb to <vscale x 4 x i64>
567  %ve = mul <vscale x 4 x i64> %vc, %vd
568  ret <vscale x 4 x i64> %ve
569}
570
571define <vscale x 4 x i64> @vwmul_vx_nxv4i64_nxv4i16(<vscale x 4 x i16> %va, i16 %b) {
572; CHECK-LABEL: vwmul_vx_nxv4i64_nxv4i16:
573; CHECK:       # %bb.0:
574; CHECK-NEXT:    vsetvli a1, zero, e16, m1, ta, ma
575; CHECK-NEXT:    vmv.v.x v9, a0
576; CHECK-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
577; CHECK-NEXT:    vsext.vf2 v12, v8
578; CHECK-NEXT:    vsext.vf2 v14, v9
579; CHECK-NEXT:    vwmul.vv v8, v12, v14
580; CHECK-NEXT:    ret
581  %head = insertelement <vscale x 4 x i16> undef, i16 %b, i16 0
582  %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
583  %vc = sext <vscale x 4 x i16> %va to <vscale x 4 x i64>
584  %vd = sext <vscale x 4 x i16> %splat to <vscale x 4 x i64>
585  %ve = mul <vscale x 4 x i64> %vc, %vd
586  ret <vscale x 4 x i64> %ve
587}
588
589define <vscale x 4 x i64> @vwmulu_vx_nxv4i64_nxv4i16(<vscale x 4 x i16> %va, i16 %b) {
590; CHECK-LABEL: vwmulu_vx_nxv4i64_nxv4i16:
591; CHECK:       # %bb.0:
592; CHECK-NEXT:    vsetvli a1, zero, e16, m1, ta, ma
593; CHECK-NEXT:    vwmulu.vx v12, v8, a0
594; CHECK-NEXT:    vsetvli zero, zero, e64, m4, ta, ma
595; CHECK-NEXT:    vzext.vf2 v8, v12
596; CHECK-NEXT:    ret
597  %head = insertelement <vscale x 4 x i16> undef, i16 %b, i16 0
598  %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
599  %vc = zext <vscale x 4 x i16> %va to <vscale x 4 x i64>
600  %vd = zext <vscale x 4 x i16> %splat to <vscale x 4 x i64>
601  %ve = mul <vscale x 4 x i64> %vc, %vd
602  ret <vscale x 4 x i64> %ve
603}
604
605define <vscale x 4 x i64> @vwmulsu_vx_nxv4i64_nxv4i16(<vscale x 4 x i16> %va, i16 %b) {
606; CHECK-LABEL: vwmulsu_vx_nxv4i64_nxv4i16:
607; CHECK:       # %bb.0:
608; CHECK-NEXT:    vsetvli a1, zero, e16, m1, ta, ma
609; CHECK-NEXT:    vmv.v.x v9, a0
610; CHECK-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
611; CHECK-NEXT:    vsext.vf2 v12, v8
612; CHECK-NEXT:    vzext.vf2 v14, v9
613; CHECK-NEXT:    vwmulsu.vv v8, v12, v14
614; CHECK-NEXT:    ret
615  %head = insertelement <vscale x 4 x i16> undef, i16 %b, i16 0
616  %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
617  %vc = sext <vscale x 4 x i16> %va to <vscale x 4 x i64>
618  %vd = zext <vscale x 4 x i16> %splat to <vscale x 4 x i64>
619  %ve = mul <vscale x 4 x i64> %vc, %vd
620  ret <vscale x 4 x i64> %ve
621}
622
623define <vscale x 8 x i64> @vwmul_vv_nxv8i64_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) {
624; CHECK-LABEL: vwmul_vv_nxv8i64_nxv8i16:
625; CHECK:       # %bb.0:
626; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, ma
627; CHECK-NEXT:    vsext.vf2 v16, v8
628; CHECK-NEXT:    vsext.vf2 v20, v10
629; CHECK-NEXT:    vwmul.vv v8, v16, v20
630; CHECK-NEXT:    ret
631  %vc = sext <vscale x 8 x i16> %va to <vscale x 8 x i64>
632  %vd = sext <vscale x 8 x i16> %vb to <vscale x 8 x i64>
633  %ve = mul <vscale x 8 x i64> %vc, %vd
634  ret <vscale x 8 x i64> %ve
635}
636
637define <vscale x 8 x i64> @vwmulu_vv_nxv8i64_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) {
638; CHECK-LABEL: vwmulu_vv_nxv8i64_nxv8i16:
639; CHECK:       # %bb.0:
640; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, ma
641; CHECK-NEXT:    vwmulu.vv v16, v8, v10
642; CHECK-NEXT:    vsetvli zero, zero, e64, m8, ta, ma
643; CHECK-NEXT:    vzext.vf2 v8, v16
644; CHECK-NEXT:    ret
645  %vc = zext <vscale x 8 x i16> %va to <vscale x 8 x i64>
646  %vd = zext <vscale x 8 x i16> %vb to <vscale x 8 x i64>
647  %ve = mul <vscale x 8 x i64> %vc, %vd
648  ret <vscale x 8 x i64> %ve
649}
650
651define <vscale x 8 x i64> @vwmulsu_vv_nxv8i64_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) {
652; CHECK-LABEL: vwmulsu_vv_nxv8i64_nxv8i16:
653; CHECK:       # %bb.0:
654; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, ma
655; CHECK-NEXT:    vsext.vf2 v16, v8
656; CHECK-NEXT:    vzext.vf2 v20, v10
657; CHECK-NEXT:    vwmulsu.vv v8, v16, v20
658; CHECK-NEXT:    ret
659  %vc = sext <vscale x 8 x i16> %va to <vscale x 8 x i64>
660  %vd = zext <vscale x 8 x i16> %vb to <vscale x 8 x i64>
661  %ve = mul <vscale x 8 x i64> %vc, %vd
662  ret <vscale x 8 x i64> %ve
663}
664
665define <vscale x 8 x i64> @vwmul_vx_nxv8i64_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {
666; CHECK-LABEL: vwmul_vx_nxv8i64_nxv8i16:
667; CHECK:       # %bb.0:
668; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, ma
669; CHECK-NEXT:    vmv.v.x v10, a0
670; CHECK-NEXT:    vsetvli zero, zero, e32, m4, ta, ma
671; CHECK-NEXT:    vsext.vf2 v16, v8
672; CHECK-NEXT:    vsext.vf2 v20, v10
673; CHECK-NEXT:    vwmul.vv v8, v16, v20
674; CHECK-NEXT:    ret
675  %head = insertelement <vscale x 8 x i16> undef, i16 %b, i16 0
676  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
677  %vc = sext <vscale x 8 x i16> %va to <vscale x 8 x i64>
678  %vd = sext <vscale x 8 x i16> %splat to <vscale x 8 x i64>
679  %ve = mul <vscale x 8 x i64> %vc, %vd
680  ret <vscale x 8 x i64> %ve
681}
682
683define <vscale x 8 x i64> @vwmulu_vx_nxv8i64_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {
684; CHECK-LABEL: vwmulu_vx_nxv8i64_nxv8i16:
685; CHECK:       # %bb.0:
686; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, ma
687; CHECK-NEXT:    vwmulu.vx v16, v8, a0
688; CHECK-NEXT:    vsetvli zero, zero, e64, m8, ta, ma
689; CHECK-NEXT:    vzext.vf2 v8, v16
690; CHECK-NEXT:    ret
691  %head = insertelement <vscale x 8 x i16> undef, i16 %b, i16 0
692  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
693  %vc = zext <vscale x 8 x i16> %va to <vscale x 8 x i64>
694  %vd = zext <vscale x 8 x i16> %splat to <vscale x 8 x i64>
695  %ve = mul <vscale x 8 x i64> %vc, %vd
696  ret <vscale x 8 x i64> %ve
697}
698
699define <vscale x 8 x i64> @vwmulsu_vx_nxv8i64_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {
700; CHECK-LABEL: vwmulsu_vx_nxv8i64_nxv8i16:
701; CHECK:       # %bb.0:
702; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, ma
703; CHECK-NEXT:    vmv.v.x v10, a0
704; CHECK-NEXT:    vsetvli zero, zero, e32, m4, ta, ma
705; CHECK-NEXT:    vsext.vf2 v16, v8
706; CHECK-NEXT:    vzext.vf2 v20, v10
707; CHECK-NEXT:    vwmulsu.vv v8, v16, v20
708; CHECK-NEXT:    ret
709  %head = insertelement <vscale x 8 x i16> undef, i16 %b, i16 0
710  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
711  %vc = sext <vscale x 8 x i16> %va to <vscale x 8 x i64>
712  %vd = zext <vscale x 8 x i16> %splat to <vscale x 8 x i64>
713  %ve = mul <vscale x 8 x i64> %vc, %vd
714  ret <vscale x 8 x i64> %ve
715}
716
717define <vscale x 1 x i64> @vwmul_vv_nxv1i64_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %vb) {
718; CHECK-LABEL: vwmul_vv_nxv1i64_nxv1i8:
719; CHECK:       # %bb.0:
720; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, ma
721; CHECK-NEXT:    vsext.vf4 v10, v8
722; CHECK-NEXT:    vsext.vf4 v11, v9
723; CHECK-NEXT:    vwmul.vv v8, v10, v11
724; CHECK-NEXT:    ret
725  %vc = sext <vscale x 1 x i8> %va to <vscale x 1 x i64>
726  %vd = sext <vscale x 1 x i8> %vb to <vscale x 1 x i64>
727  %ve = mul <vscale x 1 x i64> %vc, %vd
728  ret <vscale x 1 x i64> %ve
729}
730
731define <vscale x 1 x i64> @vwmulu_vv_nxv1i64_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %vb) {
732; CHECK-LABEL: vwmulu_vv_nxv1i64_nxv1i8:
733; CHECK:       # %bb.0:
734; CHECK-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
735; CHECK-NEXT:    vwmulu.vv v10, v8, v9
736; CHECK-NEXT:    vsetvli zero, zero, e64, m1, ta, ma
737; CHECK-NEXT:    vzext.vf4 v8, v10
738; CHECK-NEXT:    ret
739  %vc = zext <vscale x 1 x i8> %va to <vscale x 1 x i64>
740  %vd = zext <vscale x 1 x i8> %vb to <vscale x 1 x i64>
741  %ve = mul <vscale x 1 x i64> %vc, %vd
742  ret <vscale x 1 x i64> %ve
743}
744
745define <vscale x 1 x i64> @vwmulsu_vv_nxv1i64_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %vb) {
746; CHECK-LABEL: vwmulsu_vv_nxv1i64_nxv1i8:
747; CHECK:       # %bb.0:
748; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, ma
749; CHECK-NEXT:    vsext.vf4 v10, v8
750; CHECK-NEXT:    vzext.vf4 v11, v9
751; CHECK-NEXT:    vwmulsu.vv v8, v10, v11
752; CHECK-NEXT:    ret
753  %vc = sext <vscale x 1 x i8> %va to <vscale x 1 x i64>
754  %vd = zext <vscale x 1 x i8> %vb to <vscale x 1 x i64>
755  %ve = mul <vscale x 1 x i64> %vc, %vd
756  ret <vscale x 1 x i64> %ve
757}
758
759define <vscale x 1 x i64> @vwmul_vx_nxv1i64_nxv1i8(<vscale x 1 x i8> %va, i8 %b) {
760; CHECK-LABEL: vwmul_vx_nxv1i64_nxv1i8:
761; CHECK:       # %bb.0:
762; CHECK-NEXT:    vsetvli a1, zero, e8, mf8, ta, ma
763; CHECK-NEXT:    vmv.v.x v9, a0
764; CHECK-NEXT:    vsetvli zero, zero, e32, mf2, ta, ma
765; CHECK-NEXT:    vsext.vf4 v10, v8
766; CHECK-NEXT:    vsext.vf4 v11, v9
767; CHECK-NEXT:    vwmul.vv v8, v10, v11
768; CHECK-NEXT:    ret
769  %head = insertelement <vscale x 1 x i8> undef, i8 %b, i8 0
770  %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
771  %vc = sext <vscale x 1 x i8> %va to <vscale x 1 x i64>
772  %vd = sext <vscale x 1 x i8> %splat to <vscale x 1 x i64>
773  %ve = mul <vscale x 1 x i64> %vc, %vd
774  ret <vscale x 1 x i64> %ve
775}
776
777define <vscale x 1 x i64> @vwmulu_vx_nxv1i64_nxv1i8(<vscale x 1 x i8> %va, i8 %b) {
778; CHECK-LABEL: vwmulu_vx_nxv1i64_nxv1i8:
779; CHECK:       # %bb.0:
780; CHECK-NEXT:    vsetvli a1, zero, e8, mf8, ta, ma
781; CHECK-NEXT:    vwmulu.vx v9, v8, a0
782; CHECK-NEXT:    vsetvli zero, zero, e64, m1, ta, ma
783; CHECK-NEXT:    vzext.vf4 v8, v9
784; CHECK-NEXT:    ret
785  %head = insertelement <vscale x 1 x i8> undef, i8 %b, i8 0
786  %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
787  %vc = zext <vscale x 1 x i8> %va to <vscale x 1 x i64>
788  %vd = zext <vscale x 1 x i8> %splat to <vscale x 1 x i64>
789  %ve = mul <vscale x 1 x i64> %vc, %vd
790  ret <vscale x 1 x i64> %ve
791}
792
793define <vscale x 1 x i64> @vwmulsu_vx_nxv1i64_nxv1i8(<vscale x 1 x i8> %va, i8 %b) {
794; CHECK-LABEL: vwmulsu_vx_nxv1i64_nxv1i8:
795; CHECK:       # %bb.0:
796; CHECK-NEXT:    vsetvli a1, zero, e8, mf8, ta, ma
797; CHECK-NEXT:    vmv.v.x v9, a0
798; CHECK-NEXT:    vsetvli zero, zero, e32, mf2, ta, ma
799; CHECK-NEXT:    vsext.vf4 v10, v8
800; CHECK-NEXT:    vzext.vf4 v11, v9
801; CHECK-NEXT:    vwmulsu.vv v8, v10, v11
802; CHECK-NEXT:    ret
803  %head = insertelement <vscale x 1 x i8> undef, i8 %b, i8 0
804  %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
805  %vc = sext <vscale x 1 x i8> %va to <vscale x 1 x i64>
806  %vd = zext <vscale x 1 x i8> %splat to <vscale x 1 x i64>
807  %ve = mul <vscale x 1 x i64> %vc, %vd
808  ret <vscale x 1 x i64> %ve
809}
810
811define <vscale x 2 x i64> @vwmul_vv_nxv2i64_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %vb) {
812; CHECK-LABEL: vwmul_vv_nxv2i64_nxv2i8:
813; CHECK:       # %bb.0:
814; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, ma
815; CHECK-NEXT:    vsext.vf4 v10, v8
816; CHECK-NEXT:    vsext.vf4 v11, v9
817; CHECK-NEXT:    vwmul.vv v8, v10, v11
818; CHECK-NEXT:    ret
819  %vc = sext <vscale x 2 x i8> %va to <vscale x 2 x i64>
820  %vd = sext <vscale x 2 x i8> %vb to <vscale x 2 x i64>
821  %ve = mul <vscale x 2 x i64> %vc, %vd
822  ret <vscale x 2 x i64> %ve
823}
824
825define <vscale x 2 x i64> @vwmulu_vv_nxv2i64_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %vb) {
826; CHECK-LABEL: vwmulu_vv_nxv2i64_nxv2i8:
827; CHECK:       # %bb.0:
828; CHECK-NEXT:    vsetvli a0, zero, e8, mf4, ta, ma
829; CHECK-NEXT:    vwmulu.vv v10, v8, v9
830; CHECK-NEXT:    vsetvli zero, zero, e64, m2, ta, ma
831; CHECK-NEXT:    vzext.vf4 v8, v10
832; CHECK-NEXT:    ret
833  %vc = zext <vscale x 2 x i8> %va to <vscale x 2 x i64>
834  %vd = zext <vscale x 2 x i8> %vb to <vscale x 2 x i64>
835  %ve = mul <vscale x 2 x i64> %vc, %vd
836  ret <vscale x 2 x i64> %ve
837}
838
839define <vscale x 2 x i64> @vwmulsu_vv_nxv2i64_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %vb) {
840; CHECK-LABEL: vwmulsu_vv_nxv2i64_nxv2i8:
841; CHECK:       # %bb.0:
842; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, ma
843; CHECK-NEXT:    vsext.vf4 v10, v8
844; CHECK-NEXT:    vzext.vf4 v11, v9
845; CHECK-NEXT:    vwmulsu.vv v8, v10, v11
846; CHECK-NEXT:    ret
847  %vc = sext <vscale x 2 x i8> %va to <vscale x 2 x i64>
848  %vd = zext <vscale x 2 x i8> %vb to <vscale x 2 x i64>
849  %ve = mul <vscale x 2 x i64> %vc, %vd
850  ret <vscale x 2 x i64> %ve
851}
852
853define <vscale x 2 x i64> @vwmul_vx_nxv2i64_nxv2i8(<vscale x 2 x i8> %va, i8 %b) {
854; CHECK-LABEL: vwmul_vx_nxv2i64_nxv2i8:
855; CHECK:       # %bb.0:
856; CHECK-NEXT:    vsetvli a1, zero, e8, mf4, ta, ma
857; CHECK-NEXT:    vmv.v.x v9, a0
858; CHECK-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
859; CHECK-NEXT:    vsext.vf4 v10, v8
860; CHECK-NEXT:    vsext.vf4 v11, v9
861; CHECK-NEXT:    vwmul.vv v8, v10, v11
862; CHECK-NEXT:    ret
863  %head = insertelement <vscale x 2 x i8> undef, i8 %b, i8 0
864  %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
865  %vc = sext <vscale x 2 x i8> %va to <vscale x 2 x i64>
866  %vd = sext <vscale x 2 x i8> %splat to <vscale x 2 x i64>
867  %ve = mul <vscale x 2 x i64> %vc, %vd
868  ret <vscale x 2 x i64> %ve
869}
870
871define <vscale x 2 x i64> @vwmulu_vx_nxv2i64_nxv2i8(<vscale x 2 x i8> %va, i8 %b) {
872; CHECK-LABEL: vwmulu_vx_nxv2i64_nxv2i8:
873; CHECK:       # %bb.0:
874; CHECK-NEXT:    vsetvli a1, zero, e8, mf4, ta, ma
875; CHECK-NEXT:    vwmulu.vx v10, v8, a0
876; CHECK-NEXT:    vsetvli zero, zero, e64, m2, ta, ma
877; CHECK-NEXT:    vzext.vf4 v8, v10
878; CHECK-NEXT:    ret
879  %head = insertelement <vscale x 2 x i8> undef, i8 %b, i8 0
880  %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
881  %vc = zext <vscale x 2 x i8> %va to <vscale x 2 x i64>
882  %vd = zext <vscale x 2 x i8> %splat to <vscale x 2 x i64>
883  %ve = mul <vscale x 2 x i64> %vc, %vd
884  ret <vscale x 2 x i64> %ve
885}
886
887define <vscale x 2 x i64> @vwmulsu_vx_nxv2i64_nxv2i8(<vscale x 2 x i8> %va, i8 %b) {
888; CHECK-LABEL: vwmulsu_vx_nxv2i64_nxv2i8:
889; CHECK:       # %bb.0:
890; CHECK-NEXT:    vsetvli a1, zero, e8, mf4, ta, ma
891; CHECK-NEXT:    vmv.v.x v9, a0
892; CHECK-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
893; CHECK-NEXT:    vsext.vf4 v10, v8
894; CHECK-NEXT:    vzext.vf4 v11, v9
895; CHECK-NEXT:    vwmulsu.vv v8, v10, v11
896; CHECK-NEXT:    ret
897  %head = insertelement <vscale x 2 x i8> undef, i8 %b, i8 0
898  %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
899  %vc = sext <vscale x 2 x i8> %va to <vscale x 2 x i64>
900  %vd = zext <vscale x 2 x i8> %splat to <vscale x 2 x i64>
901  %ve = mul <vscale x 2 x i64> %vc, %vd
902  ret <vscale x 2 x i64> %ve
903}
904
905define <vscale x 4 x i64> @vwmul_vv_nxv4i64_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %vb) {
906; CHECK-LABEL: vwmul_vv_nxv4i64_nxv4i8:
907; CHECK:       # %bb.0:
908; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, ma
909; CHECK-NEXT:    vsext.vf4 v12, v8
910; CHECK-NEXT:    vsext.vf4 v14, v9
911; CHECK-NEXT:    vwmul.vv v8, v12, v14
912; CHECK-NEXT:    ret
913  %vc = sext <vscale x 4 x i8> %va to <vscale x 4 x i64>
914  %vd = sext <vscale x 4 x i8> %vb to <vscale x 4 x i64>
915  %ve = mul <vscale x 4 x i64> %vc, %vd
916  ret <vscale x 4 x i64> %ve
917}
918
919define <vscale x 4 x i64> @vwmulu_vv_nxv4i64_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %vb) {
920; CHECK-LABEL: vwmulu_vv_nxv4i64_nxv4i8:
921; CHECK:       # %bb.0:
922; CHECK-NEXT:    vsetvli a0, zero, e8, mf2, ta, ma
923; CHECK-NEXT:    vwmulu.vv v12, v8, v9
924; CHECK-NEXT:    vsetvli zero, zero, e64, m4, ta, ma
925; CHECK-NEXT:    vzext.vf4 v8, v12
926; CHECK-NEXT:    ret
927  %vc = zext <vscale x 4 x i8> %va to <vscale x 4 x i64>
928  %vd = zext <vscale x 4 x i8> %vb to <vscale x 4 x i64>
929  %ve = mul <vscale x 4 x i64> %vc, %vd
930  ret <vscale x 4 x i64> %ve
931}
932
933define <vscale x 4 x i64> @vwmulsu_vv_nxv4i64_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %vb) {
934; CHECK-LABEL: vwmulsu_vv_nxv4i64_nxv4i8:
935; CHECK:       # %bb.0:
936; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, ma
937; CHECK-NEXT:    vsext.vf4 v12, v8
938; CHECK-NEXT:    vzext.vf4 v14, v9
939; CHECK-NEXT:    vwmulsu.vv v8, v12, v14
940; CHECK-NEXT:    ret
941  %vc = sext <vscale x 4 x i8> %va to <vscale x 4 x i64>
942  %vd = zext <vscale x 4 x i8> %vb to <vscale x 4 x i64>
943  %ve = mul <vscale x 4 x i64> %vc, %vd
944  ret <vscale x 4 x i64> %ve
945}
946
947define <vscale x 4 x i64> @vwmul_vx_nxv4i64_nxv4i8(<vscale x 4 x i8> %va, i8 %b) {
948; CHECK-LABEL: vwmul_vx_nxv4i64_nxv4i8:
949; CHECK:       # %bb.0:
950; CHECK-NEXT:    vsetvli a1, zero, e8, mf2, ta, ma
951; CHECK-NEXT:    vmv.v.x v9, a0
952; CHECK-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
953; CHECK-NEXT:    vsext.vf4 v12, v8
954; CHECK-NEXT:    vsext.vf4 v14, v9
955; CHECK-NEXT:    vwmul.vv v8, v12, v14
956; CHECK-NEXT:    ret
957  %head = insertelement <vscale x 4 x i8> undef, i8 %b, i8 0
958  %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
959  %vc = sext <vscale x 4 x i8> %va to <vscale x 4 x i64>
960  %vd = sext <vscale x 4 x i8> %splat to <vscale x 4 x i64>
961  %ve = mul <vscale x 4 x i64> %vc, %vd
962  ret <vscale x 4 x i64> %ve
963}
964
965define <vscale x 4 x i64> @vwmulu_vx_nxv4i64_nxv4i8(<vscale x 4 x i8> %va, i8 %b) {
966; CHECK-LABEL: vwmulu_vx_nxv4i64_nxv4i8:
967; CHECK:       # %bb.0:
968; CHECK-NEXT:    vsetvli a1, zero, e8, mf2, ta, ma
969; CHECK-NEXT:    vwmulu.vx v12, v8, a0
970; CHECK-NEXT:    vsetvli zero, zero, e64, m4, ta, ma
971; CHECK-NEXT:    vzext.vf4 v8, v12
972; CHECK-NEXT:    ret
973  %head = insertelement <vscale x 4 x i8> undef, i8 %b, i8 0
974  %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
975  %vc = zext <vscale x 4 x i8> %va to <vscale x 4 x i64>
976  %vd = zext <vscale x 4 x i8> %splat to <vscale x 4 x i64>
977  %ve = mul <vscale x 4 x i64> %vc, %vd
978  ret <vscale x 4 x i64> %ve
979}
980
981define <vscale x 4 x i64> @vwmulsu_vx_nxv4i64_nxv4i8(<vscale x 4 x i8> %va, i8 %b) {
982; CHECK-LABEL: vwmulsu_vx_nxv4i64_nxv4i8:
983; CHECK:       # %bb.0:
984; CHECK-NEXT:    vsetvli a1, zero, e8, mf2, ta, ma
985; CHECK-NEXT:    vmv.v.x v9, a0
986; CHECK-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
987; CHECK-NEXT:    vsext.vf4 v12, v8
988; CHECK-NEXT:    vzext.vf4 v14, v9
989; CHECK-NEXT:    vwmulsu.vv v8, v12, v14
990; CHECK-NEXT:    ret
991  %head = insertelement <vscale x 4 x i8> undef, i8 %b, i8 0
992  %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
993  %vc = sext <vscale x 4 x i8> %va to <vscale x 4 x i64>
994  %vd = zext <vscale x 4 x i8> %splat to <vscale x 4 x i64>
995  %ve = mul <vscale x 4 x i64> %vc, %vd
996  ret <vscale x 4 x i64> %ve
997}
998
999define <vscale x 8 x i64> @vwmul_vv_nxv8i64_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) {
1000; CHECK-LABEL: vwmul_vv_nxv8i64_nxv8i8:
1001; CHECK:       # %bb.0:
1002; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, ma
1003; CHECK-NEXT:    vsext.vf4 v16, v8
1004; CHECK-NEXT:    vsext.vf4 v20, v9
1005; CHECK-NEXT:    vwmul.vv v8, v16, v20
1006; CHECK-NEXT:    ret
1007  %vc = sext <vscale x 8 x i8> %va to <vscale x 8 x i64>
1008  %vd = sext <vscale x 8 x i8> %vb to <vscale x 8 x i64>
1009  %ve = mul <vscale x 8 x i64> %vc, %vd
1010  ret <vscale x 8 x i64> %ve
1011}
1012
1013define <vscale x 8 x i64> @vwmulu_vv_nxv8i64_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) {
1014; CHECK-LABEL: vwmulu_vv_nxv8i64_nxv8i8:
1015; CHECK:       # %bb.0:
1016; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, ma
1017; CHECK-NEXT:    vwmulu.vv v16, v8, v9
1018; CHECK-NEXT:    vsetvli zero, zero, e64, m8, ta, ma
1019; CHECK-NEXT:    vzext.vf4 v8, v16
1020; CHECK-NEXT:    ret
1021  %vc = zext <vscale x 8 x i8> %va to <vscale x 8 x i64>
1022  %vd = zext <vscale x 8 x i8> %vb to <vscale x 8 x i64>
1023  %ve = mul <vscale x 8 x i64> %vc, %vd
1024  ret <vscale x 8 x i64> %ve
1025}
1026
1027define <vscale x 8 x i64> @vwmulsu_vv_nxv8i64_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) {
1028; CHECK-LABEL: vwmulsu_vv_nxv8i64_nxv8i8:
1029; CHECK:       # %bb.0:
1030; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, ma
1031; CHECK-NEXT:    vsext.vf4 v16, v8
1032; CHECK-NEXT:    vzext.vf4 v20, v9
1033; CHECK-NEXT:    vwmulsu.vv v8, v16, v20
1034; CHECK-NEXT:    ret
1035  %vc = sext <vscale x 8 x i8> %va to <vscale x 8 x i64>
1036  %vd = zext <vscale x 8 x i8> %vb to <vscale x 8 x i64>
1037  %ve = mul <vscale x 8 x i64> %vc, %vd
1038  ret <vscale x 8 x i64> %ve
1039}
1040
1041define <vscale x 8 x i64> @vwmul_vx_nxv8i64_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {
1042; CHECK-LABEL: vwmul_vx_nxv8i64_nxv8i8:
1043; CHECK:       # %bb.0:
1044; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, ma
1045; CHECK-NEXT:    vmv.v.x v9, a0
1046; CHECK-NEXT:    vsetvli zero, zero, e32, m4, ta, ma
1047; CHECK-NEXT:    vsext.vf4 v16, v8
1048; CHECK-NEXT:    vsext.vf4 v20, v9
1049; CHECK-NEXT:    vwmul.vv v8, v16, v20
1050; CHECK-NEXT:    ret
1051  %head = insertelement <vscale x 8 x i8> undef, i8 %b, i8 0
1052  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
1053  %vc = sext <vscale x 8 x i8> %va to <vscale x 8 x i64>
1054  %vd = sext <vscale x 8 x i8> %splat to <vscale x 8 x i64>
1055  %ve = mul <vscale x 8 x i64> %vc, %vd
1056  ret <vscale x 8 x i64> %ve
1057}
1058
1059define <vscale x 8 x i64> @vwmulu_vx_nxv8i64_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {
1060; CHECK-LABEL: vwmulu_vx_nxv8i64_nxv8i8:
1061; CHECK:       # %bb.0:
1062; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, ma
1063; CHECK-NEXT:    vwmulu.vx v16, v8, a0
1064; CHECK-NEXT:    vsetvli zero, zero, e64, m8, ta, ma
1065; CHECK-NEXT:    vzext.vf4 v8, v16
1066; CHECK-NEXT:    ret
1067  %head = insertelement <vscale x 8 x i8> undef, i8 %b, i8 0
1068  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
1069  %vc = zext <vscale x 8 x i8> %va to <vscale x 8 x i64>
1070  %vd = zext <vscale x 8 x i8> %splat to <vscale x 8 x i64>
1071  %ve = mul <vscale x 8 x i64> %vc, %vd
1072  ret <vscale x 8 x i64> %ve
1073}
1074
1075define <vscale x 8 x i64> @vwmulsu_vx_nxv8i64_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {
1076; CHECK-LABEL: vwmulsu_vx_nxv8i64_nxv8i8:
1077; CHECK:       # %bb.0:
1078; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, ma
1079; CHECK-NEXT:    vmv.v.x v9, a0
1080; CHECK-NEXT:    vsetvli zero, zero, e32, m4, ta, ma
1081; CHECK-NEXT:    vsext.vf4 v16, v8
1082; CHECK-NEXT:    vzext.vf4 v20, v9
1083; CHECK-NEXT:    vwmulsu.vv v8, v16, v20
1084; CHECK-NEXT:    ret
1085  %head = insertelement <vscale x 8 x i8> undef, i8 %b, i8 0
1086  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
1087  %vc = sext <vscale x 8 x i8> %va to <vscale x 8 x i64>
1088  %vd = zext <vscale x 8 x i8> %splat to <vscale x 8 x i64>
1089  %ve = mul <vscale x 8 x i64> %vc, %vd
1090  ret <vscale x 8 x i64> %ve
1091}
1092