xref: /llvm-project/llvm/test/CodeGen/RISCV/rvv/vwadd-sdnode.ll (revision 9122c5235ec85ce0c0ad337e862b006e7b349d84) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck -check-prefixes=CHECK,RV32 %s
3; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck -check-prefixes=CHECK,RV64 %s
4
5define <vscale x 1 x i64> @vwadd_vv_nxv1i64_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb) {
6; CHECK-LABEL: vwadd_vv_nxv1i64_nxv1i32:
7; CHECK:       # %bb.0:
8; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, ma
9; CHECK-NEXT:    vwadd.vv v10, v8, v9
10; CHECK-NEXT:    vmv1r.v v8, v10
11; CHECK-NEXT:    ret
12  %vc = sext <vscale x 1 x i32> %va to <vscale x 1 x i64>
13  %vd = sext <vscale x 1 x i32> %vb to <vscale x 1 x i64>
14  %ve = add <vscale x 1 x i64> %vc, %vd
15  ret <vscale x 1 x i64> %ve
16}
17
18define <vscale x 1 x i64> @vwaddu_vv_nxv1i64_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb) {
19; CHECK-LABEL: vwaddu_vv_nxv1i64_nxv1i32:
20; CHECK:       # %bb.0:
21; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, ma
22; CHECK-NEXT:    vwaddu.vv v10, v8, v9
23; CHECK-NEXT:    vmv1r.v v8, v10
24; CHECK-NEXT:    ret
25  %vc = zext <vscale x 1 x i32> %va to <vscale x 1 x i64>
26  %vd = zext <vscale x 1 x i32> %vb to <vscale x 1 x i64>
27  %ve = add <vscale x 1 x i64> %vc, %vd
28  ret <vscale x 1 x i64> %ve
29}
30
31define <vscale x 1 x i64> @vwadd_vx_nxv1i64_nxv1i32(<vscale x 1 x i32> %va, i32 %b) {
32; CHECK-LABEL: vwadd_vx_nxv1i64_nxv1i32:
33; CHECK:       # %bb.0:
34; CHECK-NEXT:    vsetvli a1, zero, e32, mf2, ta, ma
35; CHECK-NEXT:    vwadd.vx v9, v8, a0
36; CHECK-NEXT:    vmv1r.v v8, v9
37; CHECK-NEXT:    ret
38  %head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 0
39  %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer
40  %vc = sext <vscale x 1 x i32> %va to <vscale x 1 x i64>
41  %vd = sext <vscale x 1 x i32> %splat to <vscale x 1 x i64>
42  %ve = add <vscale x 1 x i64> %vc, %vd
43  ret <vscale x 1 x i64> %ve
44}
45
46define <vscale x 1 x i64> @vwaddu_vx_nxv1i64_nxv1i32(<vscale x 1 x i32> %va, i32 %b) {
47; CHECK-LABEL: vwaddu_vx_nxv1i64_nxv1i32:
48; CHECK:       # %bb.0:
49; CHECK-NEXT:    vsetvli a1, zero, e32, mf2, ta, ma
50; CHECK-NEXT:    vwaddu.vx v9, v8, a0
51; CHECK-NEXT:    vmv1r.v v8, v9
52; CHECK-NEXT:    ret
53  %head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 0
54  %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer
55  %vc = zext <vscale x 1 x i32> %va to <vscale x 1 x i64>
56  %vd = zext <vscale x 1 x i32> %splat to <vscale x 1 x i64>
57  %ve = add <vscale x 1 x i64> %vc, %vd
58  ret <vscale x 1 x i64> %ve
59}
60
61define <vscale x 1 x i64> @vwadd_wv_nxv1i64_nxv1i32(<vscale x 1 x i64> %va, <vscale x 1 x i32> %vb) {
62; CHECK-LABEL: vwadd_wv_nxv1i64_nxv1i32:
63; CHECK:       # %bb.0:
64; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, ma
65; CHECK-NEXT:    vwadd.wv v8, v8, v9
66; CHECK-NEXT:    ret
67  %vc = sext <vscale x 1 x i32> %vb to <vscale x 1 x i64>
68  %vd = add <vscale x 1 x i64> %va, %vc
69  ret <vscale x 1 x i64> %vd
70}
71
72define <vscale x 1 x i64> @vwaddu_wv_nxv1i64_nxv1i32(<vscale x 1 x i64> %va, <vscale x 1 x i32> %vb) {
73; CHECK-LABEL: vwaddu_wv_nxv1i64_nxv1i32:
74; CHECK:       # %bb.0:
75; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, ma
76; CHECK-NEXT:    vwaddu.wv v8, v8, v9
77; CHECK-NEXT:    ret
78  %vc = zext <vscale x 1 x i32> %vb to <vscale x 1 x i64>
79  %vd = add <vscale x 1 x i64> %va, %vc
80  ret <vscale x 1 x i64> %vd
81}
82
83define <vscale x 1 x i64> @vwadd_wx_nxv1i64_nxv1i32(<vscale x 1 x i64> %va, i32 %b) {
84; CHECK-LABEL: vwadd_wx_nxv1i64_nxv1i32:
85; CHECK:       # %bb.0:
86; CHECK-NEXT:    vsetvli a1, zero, e32, mf2, ta, ma
87; CHECK-NEXT:    vwadd.wx v8, v8, a0
88; CHECK-NEXT:    ret
89  %head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 0
90  %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer
91  %vb = sext <vscale x 1 x i32> %splat to <vscale x 1 x i64>
92  %vc = add <vscale x 1 x i64> %va, %vb
93  ret <vscale x 1 x i64> %vc
94}
95
96define <vscale x 1 x i64> @vwaddu_wx_nxv1i64_nxv1i32(<vscale x 1 x i64> %va, i32 %b) {
97; CHECK-LABEL: vwaddu_wx_nxv1i64_nxv1i32:
98; CHECK:       # %bb.0:
99; CHECK-NEXT:    vsetvli a1, zero, e32, mf2, ta, ma
100; CHECK-NEXT:    vwaddu.wx v8, v8, a0
101; CHECK-NEXT:    ret
102  %head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 0
103  %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer
104  %vb = zext <vscale x 1 x i32> %splat to <vscale x 1 x i64>
105  %vc = add <vscale x 1 x i64> %va, %vb
106  ret <vscale x 1 x i64> %vc
107}
108
109define <vscale x 2 x i64> @vwadd_vv_nxv2i64_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb) {
110; CHECK-LABEL: vwadd_vv_nxv2i64_nxv2i32:
111; CHECK:       # %bb.0:
112; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, ma
113; CHECK-NEXT:    vwadd.vv v10, v8, v9
114; CHECK-NEXT:    vmv2r.v v8, v10
115; CHECK-NEXT:    ret
116  %vc = sext <vscale x 2 x i32> %va to <vscale x 2 x i64>
117  %vd = sext <vscale x 2 x i32> %vb to <vscale x 2 x i64>
118  %ve = add <vscale x 2 x i64> %vc, %vd
119  ret <vscale x 2 x i64> %ve
120}
121
122define <vscale x 2 x i64> @vwaddu_vv_nxv2i64_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb) {
123; CHECK-LABEL: vwaddu_vv_nxv2i64_nxv2i32:
124; CHECK:       # %bb.0:
125; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, ma
126; CHECK-NEXT:    vwaddu.vv v10, v8, v9
127; CHECK-NEXT:    vmv2r.v v8, v10
128; CHECK-NEXT:    ret
129  %vc = zext <vscale x 2 x i32> %va to <vscale x 2 x i64>
130  %vd = zext <vscale x 2 x i32> %vb to <vscale x 2 x i64>
131  %ve = add <vscale x 2 x i64> %vc, %vd
132  ret <vscale x 2 x i64> %ve
133}
134
135define <vscale x 2 x i64> @vwadd_vx_nxv2i64_nxv2i32(<vscale x 2 x i32> %va, i32 %b) {
136; CHECK-LABEL: vwadd_vx_nxv2i64_nxv2i32:
137; CHECK:       # %bb.0:
138; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, ma
139; CHECK-NEXT:    vwadd.vx v10, v8, a0
140; CHECK-NEXT:    vmv2r.v v8, v10
141; CHECK-NEXT:    ret
142  %head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0
143  %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer
144  %vc = sext <vscale x 2 x i32> %va to <vscale x 2 x i64>
145  %vd = sext <vscale x 2 x i32> %splat to <vscale x 2 x i64>
146  %ve = add <vscale x 2 x i64> %vc, %vd
147  ret <vscale x 2 x i64> %ve
148}
149
150define <vscale x 2 x i64> @vwaddu_vx_nxv2i64_nxv2i32(<vscale x 2 x i32> %va, i32 %b) {
151; CHECK-LABEL: vwaddu_vx_nxv2i64_nxv2i32:
152; CHECK:       # %bb.0:
153; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, ma
154; CHECK-NEXT:    vwaddu.vx v10, v8, a0
155; CHECK-NEXT:    vmv2r.v v8, v10
156; CHECK-NEXT:    ret
157  %head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0
158  %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer
159  %vc = zext <vscale x 2 x i32> %va to <vscale x 2 x i64>
160  %vd = zext <vscale x 2 x i32> %splat to <vscale x 2 x i64>
161  %ve = add <vscale x 2 x i64> %vc, %vd
162  ret <vscale x 2 x i64> %ve
163}
164
165define <vscale x 2 x i64> @vwadd_wv_nxv2i64_nxv2i32(<vscale x 2 x i64> %va, <vscale x 2 x i32> %vb) {
166; CHECK-LABEL: vwadd_wv_nxv2i64_nxv2i32:
167; CHECK:       # %bb.0:
168; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, ma
169; CHECK-NEXT:    vwadd.wv v8, v8, v10
170; CHECK-NEXT:    ret
171  %vc = sext <vscale x 2 x i32> %vb to <vscale x 2 x i64>
172  %vd = add <vscale x 2 x i64> %va, %vc
173  ret <vscale x 2 x i64> %vd
174}
175
176define <vscale x 2 x i64> @vwaddu_wv_nxv2i64_nxv2i32(<vscale x 2 x i64> %va, <vscale x 2 x i32> %vb) {
177; CHECK-LABEL: vwaddu_wv_nxv2i64_nxv2i32:
178; CHECK:       # %bb.0:
179; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, ma
180; CHECK-NEXT:    vwaddu.wv v8, v8, v10
181; CHECK-NEXT:    ret
182  %vc = zext <vscale x 2 x i32> %vb to <vscale x 2 x i64>
183  %vd = add <vscale x 2 x i64> %va, %vc
184  ret <vscale x 2 x i64> %vd
185}
186
187define <vscale x 2 x i64> @vwadd_wx_nxv2i64_nxv2i32(<vscale x 2 x i64> %va, i32 %b) {
188; CHECK-LABEL: vwadd_wx_nxv2i64_nxv2i32:
189; CHECK:       # %bb.0:
190; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, ma
191; CHECK-NEXT:    vwadd.wx v8, v8, a0
192; CHECK-NEXT:    ret
193  %head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0
194  %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer
195  %vb = sext <vscale x 2 x i32> %splat to <vscale x 2 x i64>
196  %vc = add <vscale x 2 x i64> %va, %vb
197  ret <vscale x 2 x i64> %vc
198}
199
200define <vscale x 2 x i64> @vwaddu_wx_nxv2i64_nxv2i32(<vscale x 2 x i64> %va, i32 %b) {
201; CHECK-LABEL: vwaddu_wx_nxv2i64_nxv2i32:
202; CHECK:       # %bb.0:
203; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, ma
204; CHECK-NEXT:    vwaddu.wx v8, v8, a0
205; CHECK-NEXT:    ret
206  %head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0
207  %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer
208  %vb = zext <vscale x 2 x i32> %splat to <vscale x 2 x i64>
209  %vc = add <vscale x 2 x i64> %va, %vb
210  ret <vscale x 2 x i64> %vc
211}
212
213define <vscale x 4 x i64> @vwadd_vv_nxv4i64_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb) {
214; CHECK-LABEL: vwadd_vv_nxv4i64_nxv4i32:
215; CHECK:       # %bb.0:
216; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, ma
217; CHECK-NEXT:    vwadd.vv v12, v8, v10
218; CHECK-NEXT:    vmv4r.v v8, v12
219; CHECK-NEXT:    ret
220  %vc = sext <vscale x 4 x i32> %va to <vscale x 4 x i64>
221  %vd = sext <vscale x 4 x i32> %vb to <vscale x 4 x i64>
222  %ve = add <vscale x 4 x i64> %vc, %vd
223  ret <vscale x 4 x i64> %ve
224}
225
226define <vscale x 4 x i64> @vwaddu_vv_nxv4i64_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb) {
227; CHECK-LABEL: vwaddu_vv_nxv4i64_nxv4i32:
228; CHECK:       # %bb.0:
229; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, ma
230; CHECK-NEXT:    vwaddu.vv v12, v8, v10
231; CHECK-NEXT:    vmv4r.v v8, v12
232; CHECK-NEXT:    ret
233  %vc = zext <vscale x 4 x i32> %va to <vscale x 4 x i64>
234  %vd = zext <vscale x 4 x i32> %vb to <vscale x 4 x i64>
235  %ve = add <vscale x 4 x i64> %vc, %vd
236  ret <vscale x 4 x i64> %ve
237}
238
239define <vscale x 4 x i64> @vwadd_vx_nxv4i64_nxv4i32(<vscale x 4 x i32> %va, i32 %b) {
240; CHECK-LABEL: vwadd_vx_nxv4i64_nxv4i32:
241; CHECK:       # %bb.0:
242; CHECK-NEXT:    vsetvli a1, zero, e32, m2, ta, ma
243; CHECK-NEXT:    vwadd.vx v12, v8, a0
244; CHECK-NEXT:    vmv4r.v v8, v12
245; CHECK-NEXT:    ret
246  %head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0
247  %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
248  %vc = sext <vscale x 4 x i32> %va to <vscale x 4 x i64>
249  %vd = sext <vscale x 4 x i32> %splat to <vscale x 4 x i64>
250  %ve = add <vscale x 4 x i64> %vc, %vd
251  ret <vscale x 4 x i64> %ve
252}
253
254define <vscale x 4 x i64> @vwaddu_vx_nxv4i64_nxv4i32(<vscale x 4 x i32> %va, i32 %b) {
255; CHECK-LABEL: vwaddu_vx_nxv4i64_nxv4i32:
256; CHECK:       # %bb.0:
257; CHECK-NEXT:    vsetvli a1, zero, e32, m2, ta, ma
258; CHECK-NEXT:    vwaddu.vx v12, v8, a0
259; CHECK-NEXT:    vmv4r.v v8, v12
260; CHECK-NEXT:    ret
261  %head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0
262  %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
263  %vc = zext <vscale x 4 x i32> %va to <vscale x 4 x i64>
264  %vd = zext <vscale x 4 x i32> %splat to <vscale x 4 x i64>
265  %ve = add <vscale x 4 x i64> %vc, %vd
266  ret <vscale x 4 x i64> %ve
267}
268
269define <vscale x 4 x i64> @vwadd_wv_nxv4i64_nxv4i32(<vscale x 4 x i64> %va, <vscale x 4 x i32> %vb) {
270; CHECK-LABEL: vwadd_wv_nxv4i64_nxv4i32:
271; CHECK:       # %bb.0:
272; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, ma
273; CHECK-NEXT:    vwadd.wv v8, v8, v12
274; CHECK-NEXT:    ret
275  %vc = sext <vscale x 4 x i32> %vb to <vscale x 4 x i64>
276  %vd = add <vscale x 4 x i64> %va, %vc
277  ret <vscale x 4 x i64> %vd
278}
279
280define <vscale x 4 x i64> @vwaddu_wv_nxv4i64_nxv4i32(<vscale x 4 x i64> %va, <vscale x 4 x i32> %vb) {
281; CHECK-LABEL: vwaddu_wv_nxv4i64_nxv4i32:
282; CHECK:       # %bb.0:
283; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, ma
284; CHECK-NEXT:    vwaddu.wv v8, v8, v12
285; CHECK-NEXT:    ret
286  %vc = zext <vscale x 4 x i32> %vb to <vscale x 4 x i64>
287  %vd = add <vscale x 4 x i64> %va, %vc
288  ret <vscale x 4 x i64> %vd
289}
290
291define <vscale x 4 x i64> @vwadd_wx_nxv4i64_nxv4i32(<vscale x 4 x i64> %va, i32 %b) {
292; CHECK-LABEL: vwadd_wx_nxv4i64_nxv4i32:
293; CHECK:       # %bb.0:
294; CHECK-NEXT:    vsetvli a1, zero, e32, m2, ta, ma
295; CHECK-NEXT:    vwadd.wx v8, v8, a0
296; CHECK-NEXT:    ret
297  %head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0
298  %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
299  %vb = sext <vscale x 4 x i32> %splat to <vscale x 4 x i64>
300  %vc = add <vscale x 4 x i64> %va, %vb
301  ret <vscale x 4 x i64> %vc
302}
303
304define <vscale x 4 x i64> @vwaddu_wx_nxv4i64_nxv4i32(<vscale x 4 x i64> %va, i32 %b) {
305; CHECK-LABEL: vwaddu_wx_nxv4i64_nxv4i32:
306; CHECK:       # %bb.0:
307; CHECK-NEXT:    vsetvli a1, zero, e32, m2, ta, ma
308; CHECK-NEXT:    vwaddu.wx v8, v8, a0
309; CHECK-NEXT:    ret
310  %head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0
311  %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
312  %vb = zext <vscale x 4 x i32> %splat to <vscale x 4 x i64>
313  %vc = add <vscale x 4 x i64> %va, %vb
314  ret <vscale x 4 x i64> %vc
315}
316
317define <vscale x 8 x i64> @vwadd_vv_nxv8i64_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {
318; CHECK-LABEL: vwadd_vv_nxv8i64_nxv8i32:
319; CHECK:       # %bb.0:
320; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, ma
321; CHECK-NEXT:    vwadd.vv v16, v8, v12
322; CHECK-NEXT:    vmv8r.v v8, v16
323; CHECK-NEXT:    ret
324  %vc = sext <vscale x 8 x i32> %va to <vscale x 8 x i64>
325  %vd = sext <vscale x 8 x i32> %vb to <vscale x 8 x i64>
326  %ve = add <vscale x 8 x i64> %vc, %vd
327  ret <vscale x 8 x i64> %ve
328}
329
330define <vscale x 8 x i64> @vwaddu_vv_nxv8i64_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {
331; CHECK-LABEL: vwaddu_vv_nxv8i64_nxv8i32:
332; CHECK:       # %bb.0:
333; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, ma
334; CHECK-NEXT:    vwaddu.vv v16, v8, v12
335; CHECK-NEXT:    vmv8r.v v8, v16
336; CHECK-NEXT:    ret
337  %vc = zext <vscale x 8 x i32> %va to <vscale x 8 x i64>
338  %vd = zext <vscale x 8 x i32> %vb to <vscale x 8 x i64>
339  %ve = add <vscale x 8 x i64> %vc, %vd
340  ret <vscale x 8 x i64> %ve
341}
342
343define <vscale x 8 x i64> @vwadd_vx_nxv8i64_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
344; CHECK-LABEL: vwadd_vx_nxv8i64_nxv8i32:
345; CHECK:       # %bb.0:
346; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, ma
347; CHECK-NEXT:    vwadd.vx v16, v8, a0
348; CHECK-NEXT:    vmv8r.v v8, v16
349; CHECK-NEXT:    ret
350  %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
351  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
352  %vc = sext <vscale x 8 x i32> %va to <vscale x 8 x i64>
353  %vd = sext <vscale x 8 x i32> %splat to <vscale x 8 x i64>
354  %ve = add <vscale x 8 x i64> %vc, %vd
355  ret <vscale x 8 x i64> %ve
356}
357
358define <vscale x 8 x i64> @vwaddu_vx_nxv8i64_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
359; CHECK-LABEL: vwaddu_vx_nxv8i64_nxv8i32:
360; CHECK:       # %bb.0:
361; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, ma
362; CHECK-NEXT:    vwaddu.vx v16, v8, a0
363; CHECK-NEXT:    vmv8r.v v8, v16
364; CHECK-NEXT:    ret
365  %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
366  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
367  %vc = zext <vscale x 8 x i32> %va to <vscale x 8 x i64>
368  %vd = zext <vscale x 8 x i32> %splat to <vscale x 8 x i64>
369  %ve = add <vscale x 8 x i64> %vc, %vd
370  ret <vscale x 8 x i64> %ve
371}
372
373define <vscale x 8 x i64> @vwadd_wv_nxv8i64_nxv8i32(<vscale x 8 x i64> %va, <vscale x 8 x i32> %vb) {
374; CHECK-LABEL: vwadd_wv_nxv8i64_nxv8i32:
375; CHECK:       # %bb.0:
376; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, ma
377; CHECK-NEXT:    vwadd.wv v8, v8, v16
378; CHECK-NEXT:    ret
379  %vc = sext <vscale x 8 x i32> %vb to <vscale x 8 x i64>
380  %vd = add <vscale x 8 x i64> %va, %vc
381  ret <vscale x 8 x i64> %vd
382}
383
384define <vscale x 8 x i64> @vwaddu_wv_nxv8i64_nxv8i32(<vscale x 8 x i64> %va, <vscale x 8 x i32> %vb) {
385; CHECK-LABEL: vwaddu_wv_nxv8i64_nxv8i32:
386; CHECK:       # %bb.0:
387; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, ma
388; CHECK-NEXT:    vwaddu.wv v8, v8, v16
389; CHECK-NEXT:    ret
390  %vc = zext <vscale x 8 x i32> %vb to <vscale x 8 x i64>
391  %vd = add <vscale x 8 x i64> %va, %vc
392  ret <vscale x 8 x i64> %vd
393}
394
395define <vscale x 8 x i64> @vwadd_wx_nxv8i64_nxv8i32(<vscale x 8 x i64> %va, i32 %b) {
396; CHECK-LABEL: vwadd_wx_nxv8i64_nxv8i32:
397; CHECK:       # %bb.0:
398; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, ma
399; CHECK-NEXT:    vwadd.wx v8, v8, a0
400; CHECK-NEXT:    ret
401  %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
402  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
403  %vb = sext <vscale x 8 x i32> %splat to <vscale x 8 x i64>
404  %vc = add <vscale x 8 x i64> %va, %vb
405  ret <vscale x 8 x i64> %vc
406}
407
408define <vscale x 8 x i64> @vwaddu_wx_nxv8i64_nxv8i32(<vscale x 8 x i64> %va, i32 %b) {
409; CHECK-LABEL: vwaddu_wx_nxv8i64_nxv8i32:
410; CHECK:       # %bb.0:
411; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, ma
412; CHECK-NEXT:    vwaddu.wx v8, v8, a0
413; CHECK-NEXT:    ret
414  %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
415  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
416  %vb = zext <vscale x 8 x i32> %splat to <vscale x 8 x i64>
417  %vc = add <vscale x 8 x i64> %va, %vb
418  ret <vscale x 8 x i64> %vc
419}
420
421define <vscale x 1 x i64> @vwadd_vv_nxv1i64_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %vb) {
422; CHECK-LABEL: vwadd_vv_nxv1i64_nxv1i16:
423; CHECK:       # %bb.0:
424; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, ma
425; CHECK-NEXT:    vsext.vf2 v10, v8
426; CHECK-NEXT:    vsext.vf2 v11, v9
427; CHECK-NEXT:    vwadd.vv v8, v10, v11
428; CHECK-NEXT:    ret
429  %vc = sext <vscale x 1 x i16> %va to <vscale x 1 x i64>
430  %vd = sext <vscale x 1 x i16> %vb to <vscale x 1 x i64>
431  %ve = add <vscale x 1 x i64> %vc, %vd
432  ret <vscale x 1 x i64> %ve
433}
434
435define <vscale x 1 x i64> @vwaddu_vv_nxv1i64_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %vb) {
436; CHECK-LABEL: vwaddu_vv_nxv1i64_nxv1i16:
437; CHECK:       # %bb.0:
438; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, ma
439; CHECK-NEXT:    vwaddu.vv v10, v8, v9
440; CHECK-NEXT:    vsetvli zero, zero, e64, m1, ta, ma
441; CHECK-NEXT:    vzext.vf2 v8, v10
442; CHECK-NEXT:    ret
443  %vc = zext <vscale x 1 x i16> %va to <vscale x 1 x i64>
444  %vd = zext <vscale x 1 x i16> %vb to <vscale x 1 x i64>
445  %ve = add <vscale x 1 x i64> %vc, %vd
446  ret <vscale x 1 x i64> %ve
447}
448
449define <vscale x 1 x i64> @vwadd_vx_nxv1i64_nxv1i16(<vscale x 1 x i16> %va, i16 %b) {
450; CHECK-LABEL: vwadd_vx_nxv1i64_nxv1i16:
451; CHECK:       # %bb.0:
452; CHECK-NEXT:    vsetvli a1, zero, e16, mf4, ta, ma
453; CHECK-NEXT:    vmv.v.x v9, a0
454; CHECK-NEXT:    vsetvli zero, zero, e32, mf2, ta, ma
455; CHECK-NEXT:    vsext.vf2 v10, v8
456; CHECK-NEXT:    vsext.vf2 v11, v9
457; CHECK-NEXT:    vwadd.vv v8, v10, v11
458; CHECK-NEXT:    ret
459  %head = insertelement <vscale x 1 x i16> poison, i16 %b, i16 0
460  %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer
461  %vc = sext <vscale x 1 x i16> %va to <vscale x 1 x i64>
462  %vd = sext <vscale x 1 x i16> %splat to <vscale x 1 x i64>
463  %ve = add <vscale x 1 x i64> %vc, %vd
464  ret <vscale x 1 x i64> %ve
465}
466
467define <vscale x 1 x i64> @vwaddu_vx_nxv1i64_nxv1i16(<vscale x 1 x i16> %va, i16 %b) {
468; CHECK-LABEL: vwaddu_vx_nxv1i64_nxv1i16:
469; CHECK:       # %bb.0:
470; CHECK-NEXT:    vsetvli a1, zero, e16, mf4, ta, ma
471; CHECK-NEXT:    vwaddu.vx v9, v8, a0
472; CHECK-NEXT:    vsetvli zero, zero, e64, m1, ta, ma
473; CHECK-NEXT:    vzext.vf2 v8, v9
474; CHECK-NEXT:    ret
475  %head = insertelement <vscale x 1 x i16> poison, i16 %b, i16 0
476  %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer
477  %vc = zext <vscale x 1 x i16> %va to <vscale x 1 x i64>
478  %vd = zext <vscale x 1 x i16> %splat to <vscale x 1 x i64>
479  %ve = add <vscale x 1 x i64> %vc, %vd
480  ret <vscale x 1 x i64> %ve
481}
482
483define <vscale x 1 x i64> @vwadd_wv_nxv1i64_nxv1i16(<vscale x 1 x i64> %va, <vscale x 1 x i16> %vb) {
484; CHECK-LABEL: vwadd_wv_nxv1i64_nxv1i16:
485; CHECK:       # %bb.0:
486; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, ma
487; CHECK-NEXT:    vsext.vf2 v10, v9
488; CHECK-NEXT:    vwadd.wv v8, v8, v10
489; CHECK-NEXT:    ret
490  %vc = sext <vscale x 1 x i16> %vb to <vscale x 1 x i64>
491  %vd = add <vscale x 1 x i64> %va, %vc
492  ret <vscale x 1 x i64> %vd
493}
494
495define <vscale x 1 x i64> @vwaddu_wv_nxv1i64_nxv1i16(<vscale x 1 x i64> %va, <vscale x 1 x i16> %vb) {
496; CHECK-LABEL: vwaddu_wv_nxv1i64_nxv1i16:
497; CHECK:       # %bb.0:
498; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, ma
499; CHECK-NEXT:    vzext.vf2 v10, v9
500; CHECK-NEXT:    vwaddu.wv v8, v8, v10
501; CHECK-NEXT:    ret
502  %vc = zext <vscale x 1 x i16> %vb to <vscale x 1 x i64>
503  %vd = add <vscale x 1 x i64> %va, %vc
504  ret <vscale x 1 x i64> %vd
505}
506
507define <vscale x 1 x i64> @vwadd_wx_nxv1i64_nxv1i16(<vscale x 1 x i64> %va, i16 %b) {
508; CHECK-LABEL: vwadd_wx_nxv1i64_nxv1i16:
509; CHECK:       # %bb.0:
510; CHECK-NEXT:    vsetvli a1, zero, e16, mf4, ta, ma
511; CHECK-NEXT:    vmv.v.x v9, a0
512; CHECK-NEXT:    vsetvli zero, zero, e32, mf2, ta, ma
513; CHECK-NEXT:    vsext.vf2 v10, v9
514; CHECK-NEXT:    vwadd.wv v8, v8, v10
515; CHECK-NEXT:    ret
516  %head = insertelement <vscale x 1 x i16> poison, i16 %b, i16 0
517  %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer
518  %vb = sext <vscale x 1 x i16> %splat to <vscale x 1 x i64>
519  %vc = add <vscale x 1 x i64> %va, %vb
520  ret <vscale x 1 x i64> %vc
521}
522
523define <vscale x 1 x i64> @vwaddu_wx_nxv1i64_nxv1i16(<vscale x 1 x i64> %va, i16 %b) {
524; CHECK-LABEL: vwaddu_wx_nxv1i64_nxv1i16:
525; CHECK:       # %bb.0:
526; CHECK-NEXT:    vsetvli a1, zero, e16, mf4, ta, ma
527; CHECK-NEXT:    vmv.v.x v9, a0
528; CHECK-NEXT:    vsetvli zero, zero, e32, mf2, ta, ma
529; CHECK-NEXT:    vzext.vf2 v10, v9
530; CHECK-NEXT:    vwaddu.wv v8, v8, v10
531; CHECK-NEXT:    ret
532  %head = insertelement <vscale x 1 x i16> poison, i16 %b, i16 0
533  %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer
534  %vb = zext <vscale x 1 x i16> %splat to <vscale x 1 x i64>
535  %vc = add <vscale x 1 x i64> %va, %vb
536  ret <vscale x 1 x i64> %vc
537}
538
539define <vscale x 2 x i64> @vwadd_vv_nxv2i64_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %vb) {
540; CHECK-LABEL: vwadd_vv_nxv2i64_nxv2i16:
541; CHECK:       # %bb.0:
542; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, ma
543; CHECK-NEXT:    vsext.vf2 v10, v8
544; CHECK-NEXT:    vsext.vf2 v11, v9
545; CHECK-NEXT:    vwadd.vv v8, v10, v11
546; CHECK-NEXT:    ret
547  %vc = sext <vscale x 2 x i16> %va to <vscale x 2 x i64>
548  %vd = sext <vscale x 2 x i16> %vb to <vscale x 2 x i64>
549  %ve = add <vscale x 2 x i64> %vc, %vd
550  ret <vscale x 2 x i64> %ve
551}
552
553define <vscale x 2 x i64> @vwaddu_vv_nxv2i64_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %vb) {
554; CHECK-LABEL: vwaddu_vv_nxv2i64_nxv2i16:
555; CHECK:       # %bb.0:
556; CHECK-NEXT:    vsetvli a0, zero, e16, mf2, ta, ma
557; CHECK-NEXT:    vwaddu.vv v10, v8, v9
558; CHECK-NEXT:    vsetvli zero, zero, e64, m2, ta, ma
559; CHECK-NEXT:    vzext.vf2 v8, v10
560; CHECK-NEXT:    ret
561  %vc = zext <vscale x 2 x i16> %va to <vscale x 2 x i64>
562  %vd = zext <vscale x 2 x i16> %vb to <vscale x 2 x i64>
563  %ve = add <vscale x 2 x i64> %vc, %vd
564  ret <vscale x 2 x i64> %ve
565}
566
567define <vscale x 2 x i64> @vwadd_vx_nxv2i64_nxv2i16(<vscale x 2 x i16> %va, i16 %b) {
568; CHECK-LABEL: vwadd_vx_nxv2i64_nxv2i16:
569; CHECK:       # %bb.0:
570; CHECK-NEXT:    vsetvli a1, zero, e16, mf2, ta, ma
571; CHECK-NEXT:    vmv.v.x v9, a0
572; CHECK-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
573; CHECK-NEXT:    vsext.vf2 v10, v8
574; CHECK-NEXT:    vsext.vf2 v11, v9
575; CHECK-NEXT:    vwadd.vv v8, v10, v11
576; CHECK-NEXT:    ret
577  %head = insertelement <vscale x 2 x i16> poison, i16 %b, i16 0
578  %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer
579  %vc = sext <vscale x 2 x i16> %va to <vscale x 2 x i64>
580  %vd = sext <vscale x 2 x i16> %splat to <vscale x 2 x i64>
581  %ve = add <vscale x 2 x i64> %vc, %vd
582  ret <vscale x 2 x i64> %ve
583}
584
585define <vscale x 2 x i64> @vwaddu_vx_nxv2i64_nxv2i16(<vscale x 2 x i16> %va, i16 %b) {
586; CHECK-LABEL: vwaddu_vx_nxv2i64_nxv2i16:
587; CHECK:       # %bb.0:
588; CHECK-NEXT:    vsetvli a1, zero, e16, mf2, ta, ma
589; CHECK-NEXT:    vwaddu.vx v10, v8, a0
590; CHECK-NEXT:    vsetvli zero, zero, e64, m2, ta, ma
591; CHECK-NEXT:    vzext.vf2 v8, v10
592; CHECK-NEXT:    ret
593  %head = insertelement <vscale x 2 x i16> poison, i16 %b, i16 0
594  %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer
595  %vc = zext <vscale x 2 x i16> %va to <vscale x 2 x i64>
596  %vd = zext <vscale x 2 x i16> %splat to <vscale x 2 x i64>
597  %ve = add <vscale x 2 x i64> %vc, %vd
598  ret <vscale x 2 x i64> %ve
599}
600
601define <vscale x 2 x i64> @vwadd_wv_nxv2i64_nxv2i16(<vscale x 2 x i64> %va, <vscale x 2 x i16> %vb) {
602; CHECK-LABEL: vwadd_wv_nxv2i64_nxv2i16:
603; CHECK:       # %bb.0:
604; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, ma
605; CHECK-NEXT:    vsext.vf2 v11, v10
606; CHECK-NEXT:    vwadd.wv v8, v8, v11
607; CHECK-NEXT:    ret
608  %vc = sext <vscale x 2 x i16> %vb to <vscale x 2 x i64>
609  %vd = add <vscale x 2 x i64> %va, %vc
610  ret <vscale x 2 x i64> %vd
611}
612
613define <vscale x 2 x i64> @vwaddu_wv_nxv2i64_nxv2i16(<vscale x 2 x i64> %va, <vscale x 2 x i16> %vb) {
614; CHECK-LABEL: vwaddu_wv_nxv2i64_nxv2i16:
615; CHECK:       # %bb.0:
616; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, ma
617; CHECK-NEXT:    vzext.vf2 v11, v10
618; CHECK-NEXT:    vwaddu.wv v8, v8, v11
619; CHECK-NEXT:    ret
620  %vc = zext <vscale x 2 x i16> %vb to <vscale x 2 x i64>
621  %vd = add <vscale x 2 x i64> %va, %vc
622  ret <vscale x 2 x i64> %vd
623}
624
625define <vscale x 2 x i64> @vwadd_wx_nxv2i64_nxv2i16(<vscale x 2 x i64> %va, i16 %b) {
626; CHECK-LABEL: vwadd_wx_nxv2i64_nxv2i16:
627; CHECK:       # %bb.0:
628; CHECK-NEXT:    vsetvli a1, zero, e16, mf2, ta, ma
629; CHECK-NEXT:    vmv.v.x v10, a0
630; CHECK-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
631; CHECK-NEXT:    vsext.vf2 v11, v10
632; CHECK-NEXT:    vwadd.wv v8, v8, v11
633; CHECK-NEXT:    ret
634  %head = insertelement <vscale x 2 x i16> poison, i16 %b, i16 0
635  %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer
636  %vb = sext <vscale x 2 x i16> %splat to <vscale x 2 x i64>
637  %vc = add <vscale x 2 x i64> %va, %vb
638  ret <vscale x 2 x i64> %vc
639}
640
641define <vscale x 2 x i64> @vwaddu_wx_nxv2i64_nxv2i16(<vscale x 2 x i64> %va, i16 %b) {
642; CHECK-LABEL: vwaddu_wx_nxv2i64_nxv2i16:
643; CHECK:       # %bb.0:
644; CHECK-NEXT:    vsetvli a1, zero, e16, mf2, ta, ma
645; CHECK-NEXT:    vmv.v.x v10, a0
646; CHECK-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
647; CHECK-NEXT:    vzext.vf2 v11, v10
648; CHECK-NEXT:    vwaddu.wv v8, v8, v11
649; CHECK-NEXT:    ret
650  %head = insertelement <vscale x 2 x i16> poison, i16 %b, i16 0
651  %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer
652  %vb = zext <vscale x 2 x i16> %splat to <vscale x 2 x i64>
653  %vc = add <vscale x 2 x i64> %va, %vb
654  ret <vscale x 2 x i64> %vc
655}
656
657define <vscale x 4 x i64> @vwadd_vv_nxv4i64_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %vb) {
658; CHECK-LABEL: vwadd_vv_nxv4i64_nxv4i16:
659; CHECK:       # %bb.0:
660; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, ma
661; CHECK-NEXT:    vsext.vf2 v12, v8
662; CHECK-NEXT:    vsext.vf2 v14, v9
663; CHECK-NEXT:    vwadd.vv v8, v12, v14
664; CHECK-NEXT:    ret
665  %vc = sext <vscale x 4 x i16> %va to <vscale x 4 x i64>
666  %vd = sext <vscale x 4 x i16> %vb to <vscale x 4 x i64>
667  %ve = add <vscale x 4 x i64> %vc, %vd
668  ret <vscale x 4 x i64> %ve
669}
670
671define <vscale x 4 x i64> @vwaddu_vv_nxv4i64_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %vb) {
672; CHECK-LABEL: vwaddu_vv_nxv4i64_nxv4i16:
673; CHECK:       # %bb.0:
674; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, ma
675; CHECK-NEXT:    vwaddu.vv v12, v8, v9
676; CHECK-NEXT:    vsetvli zero, zero, e64, m4, ta, ma
677; CHECK-NEXT:    vzext.vf2 v8, v12
678; CHECK-NEXT:    ret
679  %vc = zext <vscale x 4 x i16> %va to <vscale x 4 x i64>
680  %vd = zext <vscale x 4 x i16> %vb to <vscale x 4 x i64>
681  %ve = add <vscale x 4 x i64> %vc, %vd
682  ret <vscale x 4 x i64> %ve
683}
684
685define <vscale x 4 x i64> @vwadd_vx_nxv4i64_nxv4i16(<vscale x 4 x i16> %va, i16 %b) {
686; CHECK-LABEL: vwadd_vx_nxv4i64_nxv4i16:
687; CHECK:       # %bb.0:
688; CHECK-NEXT:    vsetvli a1, zero, e16, m1, ta, ma
689; CHECK-NEXT:    vmv.v.x v9, a0
690; CHECK-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
691; CHECK-NEXT:    vsext.vf2 v12, v8
692; CHECK-NEXT:    vsext.vf2 v14, v9
693; CHECK-NEXT:    vwadd.vv v8, v12, v14
694; CHECK-NEXT:    ret
695  %head = insertelement <vscale x 4 x i16> poison, i16 %b, i16 0
696  %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> poison, <vscale x 4 x i32> zeroinitializer
697  %vc = sext <vscale x 4 x i16> %va to <vscale x 4 x i64>
698  %vd = sext <vscale x 4 x i16> %splat to <vscale x 4 x i64>
699  %ve = add <vscale x 4 x i64> %vc, %vd
700  ret <vscale x 4 x i64> %ve
701}
702
703define <vscale x 4 x i64> @vwaddu_vx_nxv4i64_nxv4i16(<vscale x 4 x i16> %va, i16 %b) {
704; CHECK-LABEL: vwaddu_vx_nxv4i64_nxv4i16:
705; CHECK:       # %bb.0:
706; CHECK-NEXT:    vsetvli a1, zero, e16, m1, ta, ma
707; CHECK-NEXT:    vwaddu.vx v12, v8, a0
708; CHECK-NEXT:    vsetvli zero, zero, e64, m4, ta, ma
709; CHECK-NEXT:    vzext.vf2 v8, v12
710; CHECK-NEXT:    ret
711  %head = insertelement <vscale x 4 x i16> poison, i16 %b, i16 0
712  %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> poison, <vscale x 4 x i32> zeroinitializer
713  %vc = zext <vscale x 4 x i16> %va to <vscale x 4 x i64>
714  %vd = zext <vscale x 4 x i16> %splat to <vscale x 4 x i64>
715  %ve = add <vscale x 4 x i64> %vc, %vd
716  ret <vscale x 4 x i64> %ve
717}
718
719define <vscale x 4 x i64> @vwadd_wv_nxv4i64_nxv4i16(<vscale x 4 x i64> %va, <vscale x 4 x i16> %vb) {
720; CHECK-LABEL: vwadd_wv_nxv4i64_nxv4i16:
721; CHECK:       # %bb.0:
722; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, ma
723; CHECK-NEXT:    vsext.vf2 v14, v12
724; CHECK-NEXT:    vwadd.wv v8, v8, v14
725; CHECK-NEXT:    ret
726  %vc = sext <vscale x 4 x i16> %vb to <vscale x 4 x i64>
727  %vd = add <vscale x 4 x i64> %va, %vc
728  ret <vscale x 4 x i64> %vd
729}
730
731define <vscale x 4 x i64> @vwaddu_wv_nxv4i64_nxv4i16(<vscale x 4 x i64> %va, <vscale x 4 x i16> %vb) {
732; CHECK-LABEL: vwaddu_wv_nxv4i64_nxv4i16:
733; CHECK:       # %bb.0:
734; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, ma
735; CHECK-NEXT:    vzext.vf2 v14, v12
736; CHECK-NEXT:    vwaddu.wv v8, v8, v14
737; CHECK-NEXT:    ret
738  %vc = zext <vscale x 4 x i16> %vb to <vscale x 4 x i64>
739  %vd = add <vscale x 4 x i64> %va, %vc
740  ret <vscale x 4 x i64> %vd
741}
742
743define <vscale x 4 x i64> @vwadd_wx_nxv4i64_nxv4i16(<vscale x 4 x i64> %va, i16 %b) {
744; CHECK-LABEL: vwadd_wx_nxv4i64_nxv4i16:
745; CHECK:       # %bb.0:
746; CHECK-NEXT:    vsetvli a1, zero, e16, m1, ta, ma
747; CHECK-NEXT:    vmv.v.x v12, a0
748; CHECK-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
749; CHECK-NEXT:    vsext.vf2 v14, v12
750; CHECK-NEXT:    vwadd.wv v8, v8, v14
751; CHECK-NEXT:    ret
752  %head = insertelement <vscale x 4 x i16> poison, i16 %b, i16 0
753  %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> poison, <vscale x 4 x i32> zeroinitializer
754  %vb = sext <vscale x 4 x i16> %splat to <vscale x 4 x i64>
755  %vc = add <vscale x 4 x i64> %va, %vb
756  ret <vscale x 4 x i64> %vc
757}
758
759define <vscale x 4 x i64> @vwaddu_wx_nxv4i64_nxv4i16(<vscale x 4 x i64> %va, i16 %b) {
760; CHECK-LABEL: vwaddu_wx_nxv4i64_nxv4i16:
761; CHECK:       # %bb.0:
762; CHECK-NEXT:    vsetvli a1, zero, e16, m1, ta, ma
763; CHECK-NEXT:    vmv.v.x v12, a0
764; CHECK-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
765; CHECK-NEXT:    vzext.vf2 v14, v12
766; CHECK-NEXT:    vwaddu.wv v8, v8, v14
767; CHECK-NEXT:    ret
768  %head = insertelement <vscale x 4 x i16> poison, i16 %b, i16 0
769  %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> poison, <vscale x 4 x i32> zeroinitializer
770  %vb = zext <vscale x 4 x i16> %splat to <vscale x 4 x i64>
771  %vc = add <vscale x 4 x i64> %va, %vb
772  ret <vscale x 4 x i64> %vc
773}
774
775define <vscale x 8 x i64> @vwadd_vv_nxv8i64_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) {
776; CHECK-LABEL: vwadd_vv_nxv8i64_nxv8i16:
777; CHECK:       # %bb.0:
778; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, ma
779; CHECK-NEXT:    vsext.vf2 v16, v8
780; CHECK-NEXT:    vsext.vf2 v20, v10
781; CHECK-NEXT:    vwadd.vv v8, v16, v20
782; CHECK-NEXT:    ret
783  %vc = sext <vscale x 8 x i16> %va to <vscale x 8 x i64>
784  %vd = sext <vscale x 8 x i16> %vb to <vscale x 8 x i64>
785  %ve = add <vscale x 8 x i64> %vc, %vd
786  ret <vscale x 8 x i64> %ve
787}
788
789define <vscale x 8 x i64> @vwaddu_vv_nxv8i64_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) {
790; CHECK-LABEL: vwaddu_vv_nxv8i64_nxv8i16:
791; CHECK:       # %bb.0:
792; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, ma
793; CHECK-NEXT:    vwaddu.vv v16, v8, v10
794; CHECK-NEXT:    vsetvli zero, zero, e64, m8, ta, ma
795; CHECK-NEXT:    vzext.vf2 v8, v16
796; CHECK-NEXT:    ret
797  %vc = zext <vscale x 8 x i16> %va to <vscale x 8 x i64>
798  %vd = zext <vscale x 8 x i16> %vb to <vscale x 8 x i64>
799  %ve = add <vscale x 8 x i64> %vc, %vd
800  ret <vscale x 8 x i64> %ve
801}
802
803define <vscale x 8 x i64> @vwadd_vx_nxv8i64_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {
804; CHECK-LABEL: vwadd_vx_nxv8i64_nxv8i16:
805; CHECK:       # %bb.0:
806; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, ma
807; CHECK-NEXT:    vmv.v.x v10, a0
808; CHECK-NEXT:    vsetvli zero, zero, e32, m4, ta, ma
809; CHECK-NEXT:    vsext.vf2 v16, v8
810; CHECK-NEXT:    vsext.vf2 v20, v10
811; CHECK-NEXT:    vwadd.vv v8, v16, v20
812; CHECK-NEXT:    ret
813  %head = insertelement <vscale x 8 x i16> poison, i16 %b, i16 0
814  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
815  %vc = sext <vscale x 8 x i16> %va to <vscale x 8 x i64>
816  %vd = sext <vscale x 8 x i16> %splat to <vscale x 8 x i64>
817  %ve = add <vscale x 8 x i64> %vc, %vd
818  ret <vscale x 8 x i64> %ve
819}
820
821define <vscale x 8 x i64> @vwaddu_vx_nxv8i64_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {
822; CHECK-LABEL: vwaddu_vx_nxv8i64_nxv8i16:
823; CHECK:       # %bb.0:
824; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, ma
825; CHECK-NEXT:    vwaddu.vx v16, v8, a0
826; CHECK-NEXT:    vsetvli zero, zero, e64, m8, ta, ma
827; CHECK-NEXT:    vzext.vf2 v8, v16
828; CHECK-NEXT:    ret
829  %head = insertelement <vscale x 8 x i16> poison, i16 %b, i16 0
830  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
831  %vc = zext <vscale x 8 x i16> %va to <vscale x 8 x i64>
832  %vd = zext <vscale x 8 x i16> %splat to <vscale x 8 x i64>
833  %ve = add <vscale x 8 x i64> %vc, %vd
834  ret <vscale x 8 x i64> %ve
835}
836
837define <vscale x 8 x i64> @vwadd_wv_nxv8i64_nxv8i16(<vscale x 8 x i64> %va, <vscale x 8 x i16> %vb) {
838; CHECK-LABEL: vwadd_wv_nxv8i64_nxv8i16:
839; CHECK:       # %bb.0:
840; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, ma
841; CHECK-NEXT:    vsext.vf2 v20, v16
842; CHECK-NEXT:    vwadd.wv v8, v8, v20
843; CHECK-NEXT:    ret
844  %vc = sext <vscale x 8 x i16> %vb to <vscale x 8 x i64>
845  %vd = add <vscale x 8 x i64> %va, %vc
846  ret <vscale x 8 x i64> %vd
847}
848
849define <vscale x 8 x i64> @vwaddu_wv_nxv8i64_nxv8i16(<vscale x 8 x i64> %va, <vscale x 8 x i16> %vb) {
850; CHECK-LABEL: vwaddu_wv_nxv8i64_nxv8i16:
851; CHECK:       # %bb.0:
852; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, ma
853; CHECK-NEXT:    vzext.vf2 v20, v16
854; CHECK-NEXT:    vwaddu.wv v8, v8, v20
855; CHECK-NEXT:    ret
856  %vc = zext <vscale x 8 x i16> %vb to <vscale x 8 x i64>
857  %vd = add <vscale x 8 x i64> %va, %vc
858  ret <vscale x 8 x i64> %vd
859}
860
861define <vscale x 8 x i64> @vwadd_wx_nxv8i64_nxv8i16(<vscale x 8 x i64> %va, i16 %b) {
862; CHECK-LABEL: vwadd_wx_nxv8i64_nxv8i16:
863; CHECK:       # %bb.0:
864; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, ma
865; CHECK-NEXT:    vmv.v.x v16, a0
866; CHECK-NEXT:    vsetvli zero, zero, e32, m4, ta, ma
867; CHECK-NEXT:    vsext.vf2 v20, v16
868; CHECK-NEXT:    vwadd.wv v8, v8, v20
869; CHECK-NEXT:    ret
870  %head = insertelement <vscale x 8 x i16> poison, i16 %b, i16 0
871  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
872  %vb = sext <vscale x 8 x i16> %splat to <vscale x 8 x i64>
873  %vc = add <vscale x 8 x i64> %va, %vb
874  ret <vscale x 8 x i64> %vc
875}
876
877define <vscale x 8 x i64> @vwaddu_wx_nxv8i64_nxv8i16(<vscale x 8 x i64> %va, i16 %b) {
878; CHECK-LABEL: vwaddu_wx_nxv8i64_nxv8i16:
879; CHECK:       # %bb.0:
880; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, ma
881; CHECK-NEXT:    vmv.v.x v16, a0
882; CHECK-NEXT:    vsetvli zero, zero, e32, m4, ta, ma
883; CHECK-NEXT:    vzext.vf2 v20, v16
884; CHECK-NEXT:    vwaddu.wv v8, v8, v20
885; CHECK-NEXT:    ret
886  %head = insertelement <vscale x 8 x i16> poison, i16 %b, i16 0
887  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
888  %vb = zext <vscale x 8 x i16> %splat to <vscale x 8 x i64>
889  %vc = add <vscale x 8 x i64> %va, %vb
890  ret <vscale x 8 x i64> %vc
891}
892
893define <vscale x 1 x i64> @vwadd_vv_nxv1i64_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %vb) {
894; CHECK-LABEL: vwadd_vv_nxv1i64_nxv1i8:
895; CHECK:       # %bb.0:
896; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, ma
897; CHECK-NEXT:    vsext.vf4 v10, v8
898; CHECK-NEXT:    vsext.vf4 v11, v9
899; CHECK-NEXT:    vwadd.vv v8, v10, v11
900; CHECK-NEXT:    ret
901  %vc = sext <vscale x 1 x i8> %va to <vscale x 1 x i64>
902  %vd = sext <vscale x 1 x i8> %vb to <vscale x 1 x i64>
903  %ve = add <vscale x 1 x i64> %vc, %vd
904  ret <vscale x 1 x i64> %ve
905}
906
907define <vscale x 1 x i64> @vwaddu_vv_nxv1i64_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %vb) {
908; CHECK-LABEL: vwaddu_vv_nxv1i64_nxv1i8:
909; CHECK:       # %bb.0:
910; CHECK-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
911; CHECK-NEXT:    vwaddu.vv v10, v8, v9
912; CHECK-NEXT:    vsetvli zero, zero, e64, m1, ta, ma
913; CHECK-NEXT:    vzext.vf4 v8, v10
914; CHECK-NEXT:    ret
915  %vc = zext <vscale x 1 x i8> %va to <vscale x 1 x i64>
916  %vd = zext <vscale x 1 x i8> %vb to <vscale x 1 x i64>
917  %ve = add <vscale x 1 x i64> %vc, %vd
918  ret <vscale x 1 x i64> %ve
919}
920
921define <vscale x 1 x i64> @vwadd_vx_nxv1i64_nxv1i8(<vscale x 1 x i8> %va, i8 %b) {
922; CHECK-LABEL: vwadd_vx_nxv1i64_nxv1i8:
923; CHECK:       # %bb.0:
924; CHECK-NEXT:    vsetvli a1, zero, e8, mf8, ta, ma
925; CHECK-NEXT:    vmv.v.x v9, a0
926; CHECK-NEXT:    vsetvli zero, zero, e32, mf2, ta, ma
927; CHECK-NEXT:    vsext.vf4 v10, v8
928; CHECK-NEXT:    vsext.vf4 v11, v9
929; CHECK-NEXT:    vwadd.vv v8, v10, v11
930; CHECK-NEXT:    ret
931  %head = insertelement <vscale x 1 x i8> poison, i8 %b, i8 0
932  %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer
933  %vc = sext <vscale x 1 x i8> %va to <vscale x 1 x i64>
934  %vd = sext <vscale x 1 x i8> %splat to <vscale x 1 x i64>
935  %ve = add <vscale x 1 x i64> %vc, %vd
936  ret <vscale x 1 x i64> %ve
937}
938
939define <vscale x 1 x i64> @vwaddu_vx_nxv1i64_nxv1i8(<vscale x 1 x i8> %va, i8 %b) {
940; CHECK-LABEL: vwaddu_vx_nxv1i64_nxv1i8:
941; CHECK:       # %bb.0:
942; CHECK-NEXT:    vsetvli a1, zero, e8, mf8, ta, ma
943; CHECK-NEXT:    vwaddu.vx v9, v8, a0
944; CHECK-NEXT:    vsetvli zero, zero, e64, m1, ta, ma
945; CHECK-NEXT:    vzext.vf4 v8, v9
946; CHECK-NEXT:    ret
947  %head = insertelement <vscale x 1 x i8> poison, i8 %b, i8 0
948  %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer
949  %vc = zext <vscale x 1 x i8> %va to <vscale x 1 x i64>
950  %vd = zext <vscale x 1 x i8> %splat to <vscale x 1 x i64>
951  %ve = add <vscale x 1 x i64> %vc, %vd
952  ret <vscale x 1 x i64> %ve
953}
954
955define <vscale x 1 x i64> @vwadd_wv_nxv1i64_nxv1i8(<vscale x 1 x i64> %va, <vscale x 1 x i8> %vb) {
956; CHECK-LABEL: vwadd_wv_nxv1i64_nxv1i8:
957; CHECK:       # %bb.0:
958; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, ma
959; CHECK-NEXT:    vsext.vf4 v10, v9
960; CHECK-NEXT:    vwadd.wv v8, v8, v10
961; CHECK-NEXT:    ret
962  %vc = sext <vscale x 1 x i8> %vb to <vscale x 1 x i64>
963  %vd = add <vscale x 1 x i64> %va, %vc
964  ret <vscale x 1 x i64> %vd
965}
966
967define <vscale x 1 x i64> @vwaddu_wv_nxv1i64_nxv1i8(<vscale x 1 x i64> %va, <vscale x 1 x i8> %vb) {
968; CHECK-LABEL: vwaddu_wv_nxv1i64_nxv1i8:
969; CHECK:       # %bb.0:
970; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, ma
971; CHECK-NEXT:    vzext.vf4 v10, v9
972; CHECK-NEXT:    vwaddu.wv v8, v8, v10
973; CHECK-NEXT:    ret
974  %vc = zext <vscale x 1 x i8> %vb to <vscale x 1 x i64>
975  %vd = add <vscale x 1 x i64> %va, %vc
976  ret <vscale x 1 x i64> %vd
977}
978
979define <vscale x 1 x i64> @vwadd_wx_nxv1i64_nxv1i8(<vscale x 1 x i64> %va, i8 %b) {
980; CHECK-LABEL: vwadd_wx_nxv1i64_nxv1i8:
981; CHECK:       # %bb.0:
982; CHECK-NEXT:    vsetvli a1, zero, e8, mf8, ta, ma
983; CHECK-NEXT:    vmv.v.x v9, a0
984; CHECK-NEXT:    vsetvli zero, zero, e32, mf2, ta, ma
985; CHECK-NEXT:    vsext.vf4 v10, v9
986; CHECK-NEXT:    vwadd.wv v8, v8, v10
987; CHECK-NEXT:    ret
988  %head = insertelement <vscale x 1 x i8> poison, i8 %b, i8 0
989  %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer
990  %vb = sext <vscale x 1 x i8> %splat to <vscale x 1 x i64>
991  %vc = add <vscale x 1 x i64> %va, %vb
992  ret <vscale x 1 x i64> %vc
993}
994
995define <vscale x 1 x i64> @vwaddu_wx_nxv1i64_nxv1i8(<vscale x 1 x i64> %va, i8 %b) {
996; CHECK-LABEL: vwaddu_wx_nxv1i64_nxv1i8:
997; CHECK:       # %bb.0:
998; CHECK-NEXT:    vsetvli a1, zero, e8, mf8, ta, ma
999; CHECK-NEXT:    vmv.v.x v9, a0
1000; CHECK-NEXT:    vsetvli zero, zero, e32, mf2, ta, ma
1001; CHECK-NEXT:    vzext.vf4 v10, v9
1002; CHECK-NEXT:    vwaddu.wv v8, v8, v10
1003; CHECK-NEXT:    ret
1004  %head = insertelement <vscale x 1 x i8> poison, i8 %b, i8 0
1005  %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer
1006  %vb = zext <vscale x 1 x i8> %splat to <vscale x 1 x i64>
1007  %vc = add <vscale x 1 x i64> %va, %vb
1008  ret <vscale x 1 x i64> %vc
1009}
1010
1011define <vscale x 2 x i64> @vwadd_vv_nxv2i64_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %vb) {
1012; CHECK-LABEL: vwadd_vv_nxv2i64_nxv2i8:
1013; CHECK:       # %bb.0:
1014; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, ma
1015; CHECK-NEXT:    vsext.vf4 v10, v8
1016; CHECK-NEXT:    vsext.vf4 v11, v9
1017; CHECK-NEXT:    vwadd.vv v8, v10, v11
1018; CHECK-NEXT:    ret
1019  %vc = sext <vscale x 2 x i8> %va to <vscale x 2 x i64>
1020  %vd = sext <vscale x 2 x i8> %vb to <vscale x 2 x i64>
1021  %ve = add <vscale x 2 x i64> %vc, %vd
1022  ret <vscale x 2 x i64> %ve
1023}
1024
1025define <vscale x 2 x i64> @vwaddu_vv_nxv2i64_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %vb) {
1026; CHECK-LABEL: vwaddu_vv_nxv2i64_nxv2i8:
1027; CHECK:       # %bb.0:
1028; CHECK-NEXT:    vsetvli a0, zero, e8, mf4, ta, ma
1029; CHECK-NEXT:    vwaddu.vv v10, v8, v9
1030; CHECK-NEXT:    vsetvli zero, zero, e64, m2, ta, ma
1031; CHECK-NEXT:    vzext.vf4 v8, v10
1032; CHECK-NEXT:    ret
1033  %vc = zext <vscale x 2 x i8> %va to <vscale x 2 x i64>
1034  %vd = zext <vscale x 2 x i8> %vb to <vscale x 2 x i64>
1035  %ve = add <vscale x 2 x i64> %vc, %vd
1036  ret <vscale x 2 x i64> %ve
1037}
1038
1039define <vscale x 2 x i64> @vwadd_vx_nxv2i64_nxv2i8(<vscale x 2 x i8> %va, i8 %b) {
1040; CHECK-LABEL: vwadd_vx_nxv2i64_nxv2i8:
1041; CHECK:       # %bb.0:
1042; CHECK-NEXT:    vsetvli a1, zero, e8, mf4, ta, ma
1043; CHECK-NEXT:    vmv.v.x v9, a0
1044; CHECK-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
1045; CHECK-NEXT:    vsext.vf4 v10, v8
1046; CHECK-NEXT:    vsext.vf4 v11, v9
1047; CHECK-NEXT:    vwadd.vv v8, v10, v11
1048; CHECK-NEXT:    ret
1049  %head = insertelement <vscale x 2 x i8> poison, i8 %b, i8 0
1050  %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> poison, <vscale x 2 x i32> zeroinitializer
1051  %vc = sext <vscale x 2 x i8> %va to <vscale x 2 x i64>
1052  %vd = sext <vscale x 2 x i8> %splat to <vscale x 2 x i64>
1053  %ve = add <vscale x 2 x i64> %vc, %vd
1054  ret <vscale x 2 x i64> %ve
1055}
1056
1057define <vscale x 2 x i64> @vwaddu_vx_nxv2i64_nxv2i8(<vscale x 2 x i8> %va, i8 %b) {
1058; CHECK-LABEL: vwaddu_vx_nxv2i64_nxv2i8:
1059; CHECK:       # %bb.0:
1060; CHECK-NEXT:    vsetvli a1, zero, e8, mf4, ta, ma
1061; CHECK-NEXT:    vwaddu.vx v10, v8, a0
1062; CHECK-NEXT:    vsetvli zero, zero, e64, m2, ta, ma
1063; CHECK-NEXT:    vzext.vf4 v8, v10
1064; CHECK-NEXT:    ret
1065  %head = insertelement <vscale x 2 x i8> poison, i8 %b, i8 0
1066  %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> poison, <vscale x 2 x i32> zeroinitializer
1067  %vc = zext <vscale x 2 x i8> %va to <vscale x 2 x i64>
1068  %vd = zext <vscale x 2 x i8> %splat to <vscale x 2 x i64>
1069  %ve = add <vscale x 2 x i64> %vc, %vd
1070  ret <vscale x 2 x i64> %ve
1071}
1072
1073define <vscale x 2 x i64> @vwadd_wv_nxv2i64_nxv2i8(<vscale x 2 x i64> %va, <vscale x 2 x i8> %vb) {
1074; CHECK-LABEL: vwadd_wv_nxv2i64_nxv2i8:
1075; CHECK:       # %bb.0:
1076; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, ma
1077; CHECK-NEXT:    vsext.vf4 v11, v10
1078; CHECK-NEXT:    vwadd.wv v8, v8, v11
1079; CHECK-NEXT:    ret
1080  %vc = sext <vscale x 2 x i8> %vb to <vscale x 2 x i64>
1081  %vd = add <vscale x 2 x i64> %va, %vc
1082  ret <vscale x 2 x i64> %vd
1083}
1084
1085define <vscale x 2 x i64> @vwaddu_wv_nxv2i64_nxv2i8(<vscale x 2 x i64> %va, <vscale x 2 x i8> %vb) {
1086; CHECK-LABEL: vwaddu_wv_nxv2i64_nxv2i8:
1087; CHECK:       # %bb.0:
1088; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, ma
1089; CHECK-NEXT:    vzext.vf4 v11, v10
1090; CHECK-NEXT:    vwaddu.wv v8, v8, v11
1091; CHECK-NEXT:    ret
1092  %vc = zext <vscale x 2 x i8> %vb to <vscale x 2 x i64>
1093  %vd = add <vscale x 2 x i64> %va, %vc
1094  ret <vscale x 2 x i64> %vd
1095}
1096
1097define <vscale x 2 x i64> @vwadd_wx_nxv2i64_nxv2i8(<vscale x 2 x i64> %va, i8 %b) {
1098; CHECK-LABEL: vwadd_wx_nxv2i64_nxv2i8:
1099; CHECK:       # %bb.0:
1100; CHECK-NEXT:    vsetvli a1, zero, e8, mf4, ta, ma
1101; CHECK-NEXT:    vmv.v.x v10, a0
1102; CHECK-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
1103; CHECK-NEXT:    vsext.vf4 v11, v10
1104; CHECK-NEXT:    vwadd.wv v8, v8, v11
1105; CHECK-NEXT:    ret
1106  %head = insertelement <vscale x 2 x i8> poison, i8 %b, i8 0
1107  %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> poison, <vscale x 2 x i32> zeroinitializer
1108  %vb = sext <vscale x 2 x i8> %splat to <vscale x 2 x i64>
1109  %vc = add <vscale x 2 x i64> %va, %vb
1110  ret <vscale x 2 x i64> %vc
1111}
1112
1113define <vscale x 2 x i64> @vwaddu_wx_nxv2i64_nxv2i8(<vscale x 2 x i64> %va, i8 %b) {
1114; CHECK-LABEL: vwaddu_wx_nxv2i64_nxv2i8:
1115; CHECK:       # %bb.0:
1116; CHECK-NEXT:    vsetvli a1, zero, e8, mf4, ta, ma
1117; CHECK-NEXT:    vmv.v.x v10, a0
1118; CHECK-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
1119; CHECK-NEXT:    vzext.vf4 v11, v10
1120; CHECK-NEXT:    vwaddu.wv v8, v8, v11
1121; CHECK-NEXT:    ret
1122  %head = insertelement <vscale x 2 x i8> poison, i8 %b, i8 0
1123  %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> poison, <vscale x 2 x i32> zeroinitializer
1124  %vb = zext <vscale x 2 x i8> %splat to <vscale x 2 x i64>
1125  %vc = add <vscale x 2 x i64> %va, %vb
1126  ret <vscale x 2 x i64> %vc
1127}
1128
1129define <vscale x 4 x i64> @vwadd_vv_nxv4i64_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %vb) {
1130; CHECK-LABEL: vwadd_vv_nxv4i64_nxv4i8:
1131; CHECK:       # %bb.0:
1132; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, ma
1133; CHECK-NEXT:    vsext.vf4 v12, v8
1134; CHECK-NEXT:    vsext.vf4 v14, v9
1135; CHECK-NEXT:    vwadd.vv v8, v12, v14
1136; CHECK-NEXT:    ret
1137  %vc = sext <vscale x 4 x i8> %va to <vscale x 4 x i64>
1138  %vd = sext <vscale x 4 x i8> %vb to <vscale x 4 x i64>
1139  %ve = add <vscale x 4 x i64> %vc, %vd
1140  ret <vscale x 4 x i64> %ve
1141}
1142
1143define <vscale x 4 x i64> @vwaddu_vv_nxv4i64_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %vb) {
1144; CHECK-LABEL: vwaddu_vv_nxv4i64_nxv4i8:
1145; CHECK:       # %bb.0:
1146; CHECK-NEXT:    vsetvli a0, zero, e8, mf2, ta, ma
1147; CHECK-NEXT:    vwaddu.vv v12, v8, v9
1148; CHECK-NEXT:    vsetvli zero, zero, e64, m4, ta, ma
1149; CHECK-NEXT:    vzext.vf4 v8, v12
1150; CHECK-NEXT:    ret
1151  %vc = zext <vscale x 4 x i8> %va to <vscale x 4 x i64>
1152  %vd = zext <vscale x 4 x i8> %vb to <vscale x 4 x i64>
1153  %ve = add <vscale x 4 x i64> %vc, %vd
1154  ret <vscale x 4 x i64> %ve
1155}
1156
1157define <vscale x 4 x i64> @vwadd_vx_nxv4i64_nxv4i8(<vscale x 4 x i8> %va, i8 %b) {
1158; CHECK-LABEL: vwadd_vx_nxv4i64_nxv4i8:
1159; CHECK:       # %bb.0:
1160; CHECK-NEXT:    vsetvli a1, zero, e8, mf2, ta, ma
1161; CHECK-NEXT:    vmv.v.x v9, a0
1162; CHECK-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
1163; CHECK-NEXT:    vsext.vf4 v12, v8
1164; CHECK-NEXT:    vsext.vf4 v14, v9
1165; CHECK-NEXT:    vwadd.vv v8, v12, v14
1166; CHECK-NEXT:    ret
1167  %head = insertelement <vscale x 4 x i8> poison, i8 %b, i8 0
1168  %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> poison, <vscale x 4 x i32> zeroinitializer
1169  %vc = sext <vscale x 4 x i8> %va to <vscale x 4 x i64>
1170  %vd = sext <vscale x 4 x i8> %splat to <vscale x 4 x i64>
1171  %ve = add <vscale x 4 x i64> %vc, %vd
1172  ret <vscale x 4 x i64> %ve
1173}
1174
1175define <vscale x 4 x i64> @vwaddu_vx_nxv4i64_nxv4i8(<vscale x 4 x i8> %va, i8 %b) {
1176; CHECK-LABEL: vwaddu_vx_nxv4i64_nxv4i8:
1177; CHECK:       # %bb.0:
1178; CHECK-NEXT:    vsetvli a1, zero, e8, mf2, ta, ma
1179; CHECK-NEXT:    vwaddu.vx v12, v8, a0
1180; CHECK-NEXT:    vsetvli zero, zero, e64, m4, ta, ma
1181; CHECK-NEXT:    vzext.vf4 v8, v12
1182; CHECK-NEXT:    ret
1183  %head = insertelement <vscale x 4 x i8> poison, i8 %b, i8 0
1184  %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> poison, <vscale x 4 x i32> zeroinitializer
1185  %vc = zext <vscale x 4 x i8> %va to <vscale x 4 x i64>
1186  %vd = zext <vscale x 4 x i8> %splat to <vscale x 4 x i64>
1187  %ve = add <vscale x 4 x i64> %vc, %vd
1188  ret <vscale x 4 x i64> %ve
1189}
1190
1191define <vscale x 4 x i64> @vwadd_wv_nxv4i64_nxv4i8(<vscale x 4 x i64> %va, <vscale x 4 x i8> %vb) {
1192; CHECK-LABEL: vwadd_wv_nxv4i64_nxv4i8:
1193; CHECK:       # %bb.0:
1194; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, ma
1195; CHECK-NEXT:    vsext.vf4 v14, v12
1196; CHECK-NEXT:    vwadd.wv v8, v8, v14
1197; CHECK-NEXT:    ret
1198  %vc = sext <vscale x 4 x i8> %vb to <vscale x 4 x i64>
1199  %vd = add <vscale x 4 x i64> %va, %vc
1200  ret <vscale x 4 x i64> %vd
1201}
1202
1203define <vscale x 4 x i64> @vwaddu_wv_nxv4i64_nxv4i8(<vscale x 4 x i64> %va, <vscale x 4 x i8> %vb) {
1204; CHECK-LABEL: vwaddu_wv_nxv4i64_nxv4i8:
1205; CHECK:       # %bb.0:
1206; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, ma
1207; CHECK-NEXT:    vzext.vf4 v14, v12
1208; CHECK-NEXT:    vwaddu.wv v8, v8, v14
1209; CHECK-NEXT:    ret
1210  %vc = zext <vscale x 4 x i8> %vb to <vscale x 4 x i64>
1211  %vd = add <vscale x 4 x i64> %va, %vc
1212  ret <vscale x 4 x i64> %vd
1213}
1214
1215define <vscale x 4 x i64> @vwadd_wx_nxv4i64_nxv4i8(<vscale x 4 x i64> %va, i8 %b) {
1216; CHECK-LABEL: vwadd_wx_nxv4i64_nxv4i8:
1217; CHECK:       # %bb.0:
1218; CHECK-NEXT:    vsetvli a1, zero, e8, mf2, ta, ma
1219; CHECK-NEXT:    vmv.v.x v12, a0
1220; CHECK-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
1221; CHECK-NEXT:    vsext.vf4 v14, v12
1222; CHECK-NEXT:    vwadd.wv v8, v8, v14
1223; CHECK-NEXT:    ret
1224  %head = insertelement <vscale x 4 x i8> poison, i8 %b, i8 0
1225  %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> poison, <vscale x 4 x i32> zeroinitializer
1226  %vb = sext <vscale x 4 x i8> %splat to <vscale x 4 x i64>
1227  %vc = add <vscale x 4 x i64> %va, %vb
1228  ret <vscale x 4 x i64> %vc
1229}
1230
1231define <vscale x 4 x i64> @vwaddu_wx_nxv4i64_nxv4i8(<vscale x 4 x i64> %va, i8 %b) {
1232; CHECK-LABEL: vwaddu_wx_nxv4i64_nxv4i8:
1233; CHECK:       # %bb.0:
1234; CHECK-NEXT:    vsetvli a1, zero, e8, mf2, ta, ma
1235; CHECK-NEXT:    vmv.v.x v12, a0
1236; CHECK-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
1237; CHECK-NEXT:    vzext.vf4 v14, v12
1238; CHECK-NEXT:    vwaddu.wv v8, v8, v14
1239; CHECK-NEXT:    ret
1240  %head = insertelement <vscale x 4 x i8> poison, i8 %b, i8 0
1241  %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> poison, <vscale x 4 x i32> zeroinitializer
1242  %vb = zext <vscale x 4 x i8> %splat to <vscale x 4 x i64>
1243  %vc = add <vscale x 4 x i64> %va, %vb
1244  ret <vscale x 4 x i64> %vc
1245}
1246
1247define <vscale x 8 x i64> @vwadd_vv_nxv8i64_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) {
1248; CHECK-LABEL: vwadd_vv_nxv8i64_nxv8i8:
1249; CHECK:       # %bb.0:
1250; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, ma
1251; CHECK-NEXT:    vsext.vf4 v16, v8
1252; CHECK-NEXT:    vsext.vf4 v20, v9
1253; CHECK-NEXT:    vwadd.vv v8, v16, v20
1254; CHECK-NEXT:    ret
1255  %vc = sext <vscale x 8 x i8> %va to <vscale x 8 x i64>
1256  %vd = sext <vscale x 8 x i8> %vb to <vscale x 8 x i64>
1257  %ve = add <vscale x 8 x i64> %vc, %vd
1258  ret <vscale x 8 x i64> %ve
1259}
1260
1261define <vscale x 8 x i64> @vwaddu_vv_nxv8i64_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) {
1262; CHECK-LABEL: vwaddu_vv_nxv8i64_nxv8i8:
1263; CHECK:       # %bb.0:
1264; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, ma
1265; CHECK-NEXT:    vwaddu.vv v16, v8, v9
1266; CHECK-NEXT:    vsetvli zero, zero, e64, m8, ta, ma
1267; CHECK-NEXT:    vzext.vf4 v8, v16
1268; CHECK-NEXT:    ret
1269  %vc = zext <vscale x 8 x i8> %va to <vscale x 8 x i64>
1270  %vd = zext <vscale x 8 x i8> %vb to <vscale x 8 x i64>
1271  %ve = add <vscale x 8 x i64> %vc, %vd
1272  ret <vscale x 8 x i64> %ve
1273}
1274
1275define <vscale x 8 x i64> @vwadd_vx_nxv8i64_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {
1276; CHECK-LABEL: vwadd_vx_nxv8i64_nxv8i8:
1277; CHECK:       # %bb.0:
1278; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, ma
1279; CHECK-NEXT:    vmv.v.x v9, a0
1280; CHECK-NEXT:    vsetvli zero, zero, e32, m4, ta, ma
1281; CHECK-NEXT:    vsext.vf4 v16, v8
1282; CHECK-NEXT:    vsext.vf4 v20, v9
1283; CHECK-NEXT:    vwadd.vv v8, v16, v20
1284; CHECK-NEXT:    ret
1285  %head = insertelement <vscale x 8 x i8> poison, i8 %b, i8 0
1286  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
1287  %vc = sext <vscale x 8 x i8> %va to <vscale x 8 x i64>
1288  %vd = sext <vscale x 8 x i8> %splat to <vscale x 8 x i64>
1289  %ve = add <vscale x 8 x i64> %vc, %vd
1290  ret <vscale x 8 x i64> %ve
1291}
1292
1293define <vscale x 8 x i64> @vwaddu_vx_nxv8i64_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {
1294; CHECK-LABEL: vwaddu_vx_nxv8i64_nxv8i8:
1295; CHECK:       # %bb.0:
1296; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, ma
1297; CHECK-NEXT:    vwaddu.vx v16, v8, a0
1298; CHECK-NEXT:    vsetvli zero, zero, e64, m8, ta, ma
1299; CHECK-NEXT:    vzext.vf4 v8, v16
1300; CHECK-NEXT:    ret
1301  %head = insertelement <vscale x 8 x i8> poison, i8 %b, i8 0
1302  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
1303  %vc = zext <vscale x 8 x i8> %va to <vscale x 8 x i64>
1304  %vd = zext <vscale x 8 x i8> %splat to <vscale x 8 x i64>
1305  %ve = add <vscale x 8 x i64> %vc, %vd
1306  ret <vscale x 8 x i64> %ve
1307}
1308
1309define <vscale x 8 x i64> @vwadd_wv_nxv8i64_nxv8i8(<vscale x 8 x i64> %va, <vscale x 8 x i8> %vb) {
1310; CHECK-LABEL: vwadd_wv_nxv8i64_nxv8i8:
1311; CHECK:       # %bb.0:
1312; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, ma
1313; CHECK-NEXT:    vsext.vf4 v20, v16
1314; CHECK-NEXT:    vwadd.wv v8, v8, v20
1315; CHECK-NEXT:    ret
1316  %vc = sext <vscale x 8 x i8> %vb to <vscale x 8 x i64>
1317  %vd = add <vscale x 8 x i64> %va, %vc
1318  ret <vscale x 8 x i64> %vd
1319}
1320
1321define <vscale x 8 x i64> @vwaddu_wv_nxv8i64_nxv8i8(<vscale x 8 x i64> %va, <vscale x 8 x i8> %vb) {
1322; CHECK-LABEL: vwaddu_wv_nxv8i64_nxv8i8:
1323; CHECK:       # %bb.0:
1324; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, ma
1325; CHECK-NEXT:    vzext.vf4 v20, v16
1326; CHECK-NEXT:    vwaddu.wv v8, v8, v20
1327; CHECK-NEXT:    ret
1328  %vc = zext <vscale x 8 x i8> %vb to <vscale x 8 x i64>
1329  %vd = add <vscale x 8 x i64> %va, %vc
1330  ret <vscale x 8 x i64> %vd
1331}
1332
1333define <vscale x 8 x i64> @vwadd_wx_nxv8i64_nxv8i8(<vscale x 8 x i64> %va, i8 %b) {
1334; CHECK-LABEL: vwadd_wx_nxv8i64_nxv8i8:
1335; CHECK:       # %bb.0:
1336; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, ma
1337; CHECK-NEXT:    vmv.v.x v16, a0
1338; CHECK-NEXT:    vsetvli zero, zero, e32, m4, ta, ma
1339; CHECK-NEXT:    vsext.vf4 v20, v16
1340; CHECK-NEXT:    vwadd.wv v8, v8, v20
1341; CHECK-NEXT:    ret
1342  %head = insertelement <vscale x 8 x i8> poison, i8 %b, i8 0
1343  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
1344  %vb = sext <vscale x 8 x i8> %splat to <vscale x 8 x i64>
1345  %vc = add <vscale x 8 x i64> %va, %vb
1346  ret <vscale x 8 x i64> %vc
1347}
1348
1349define <vscale x 8 x i64> @vwaddu_wx_nxv8i64_nxv8i8(<vscale x 8 x i64> %va, i8 %b) {
1350; CHECK-LABEL: vwaddu_wx_nxv8i64_nxv8i8:
1351; CHECK:       # %bb.0:
1352; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, ma
1353; CHECK-NEXT:    vmv.v.x v16, a0
1354; CHECK-NEXT:    vsetvli zero, zero, e32, m4, ta, ma
1355; CHECK-NEXT:    vzext.vf4 v20, v16
1356; CHECK-NEXT:    vwaddu.wv v8, v8, v20
1357; CHECK-NEXT:    ret
1358  %head = insertelement <vscale x 8 x i8> poison, i8 %b, i8 0
1359  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
1360  %vb = zext <vscale x 8 x i8> %splat to <vscale x 8 x i64>
1361  %vc = add <vscale x 8 x i64> %va, %vb
1362  ret <vscale x 8 x i64> %vc
1363}
1364
1365; Make sure that we don't introduce any V{S,Z}EXT_VL nodes with i1 types from
1366; combineBinOp_VLToVWBinOp_VL, since they can't be selected.
1367define <vscale x 1 x i64> @i1_zext(<vscale x 1 x i1> %va, <vscale x 1 x i64> %vb, ptr %p) {
1368; RV32-LABEL: i1_zext:
1369; RV32:       # %bb.0:
1370; RV32-NEXT:    vsetvli a1, zero, e64, m1, ta, ma
1371; RV32-NEXT:    vmv.v.i v9, 0
1372; RV32-NEXT:    vmerge.vim v9, v9, 1, v0
1373; RV32-NEXT:    vadd.vv v8, v9, v8
1374; RV32-NEXT:    li a1, 42
1375; RV32-NEXT:    sh a1, 0(a0)
1376; RV32-NEXT:    ret
1377;
1378; RV64-LABEL: i1_zext:
1379; RV64:       # %bb.0:
1380; RV64-NEXT:    li a1, 42
1381; RV64-NEXT:    vsetvli a2, zero, e64, m1, ta, mu
1382; RV64-NEXT:    vadd.vi v8, v8, 1, v0.t
1383; RV64-NEXT:    sh a1, 0(a0)
1384; RV64-NEXT:    ret
1385  %vc = zext <vscale x 1 x i1> %va to <vscale x 1 x i64>
1386  %vd = add <vscale x 1 x i64> %vc, %vb
1387
1388; Introduce an illegal type so that the DAG changes after legalizing
1389; types. Otherwise the legalize vector ops phase will be run immediately after
1390; the legalize types phase, and the zext will already be in non-i1 form by the
1391; time combineBinOp_VLToVWBinOp_VL is called.
1392  store i9 42, ptr %p
1393  ret <vscale x 1 x i64> %vd
1394}
1395
1396; %x.i32 and %y.i32 are disjoint, so DAGCombiner will combine it into an or.
1397define <vscale x 2 x i32> @vwaddu_vv_disjoint_or_add(<vscale x 2 x i8> %x.i8, <vscale x 2 x i8> %y.i8) {
1398; CHECK-LABEL: vwaddu_vv_disjoint_or_add:
1399; CHECK:       # %bb.0:
1400; CHECK-NEXT:    vsetvli a0, zero, e16, mf2, ta, ma
1401; CHECK-NEXT:    vzext.vf2 v10, v8
1402; CHECK-NEXT:    vsll.vi v10, v10, 8
1403; CHECK-NEXT:    vzext.vf2 v11, v9
1404; CHECK-NEXT:    vwaddu.vv v8, v10, v11
1405; CHECK-NEXT:    ret
1406  %x.i16 = zext <vscale x 2 x i8> %x.i8 to <vscale x 2 x i16>
1407  %x.shl = shl <vscale x 2 x i16> %x.i16, splat (i16 8)
1408  %x.i32 = zext <vscale x 2 x i16> %x.shl to <vscale x 2 x i32>
1409  %y.i32 = zext <vscale x 2 x i8> %y.i8 to <vscale x 2 x i32>
1410  %add = add <vscale x 2 x i32> %x.i32, %y.i32
1411  ret <vscale x 2 x i32> %add
1412}
1413
1414; TODO: We could select vwaddu.vv, but when both arms of the or are the same
1415; DAGCombiner::hoistLogicOpWithSameOpcodeHands moves the zext above the or.
1416define <vscale x 2 x i32> @vwaddu_vv_disjoint_or(<vscale x 2 x i16> %x.i16, <vscale x 2 x i16> %y.i16) {
1417; CHECK-LABEL: vwaddu_vv_disjoint_or:
1418; CHECK:       # %bb.0:
1419; CHECK-NEXT:    vsetvli a0, zero, e16, mf2, ta, ma
1420; CHECK-NEXT:    vor.vv v9, v8, v9
1421; CHECK-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
1422; CHECK-NEXT:    vzext.vf2 v8, v9
1423; CHECK-NEXT:    ret
1424  %x.i32 = zext <vscale x 2 x i16> %x.i16 to <vscale x 2 x i32>
1425  %y.i32 = zext <vscale x 2 x i16> %y.i16 to <vscale x 2 x i32>
1426  %or = or disjoint <vscale x 2 x i32> %x.i32, %y.i32
1427  ret <vscale x 2 x i32> %or
1428}
1429
1430; TODO: We could select vwadd.vv, but when both arms of the or are the same
1431; DAGCombiner::hoistLogicOpWithSameOpcodeHands moves the zext above the or.
1432define <vscale x 2 x i32> @vwadd_vv_disjoint_or(<vscale x 2 x i16> %x.i16, <vscale x 2 x i16> %y.i16) {
1433; CHECK-LABEL: vwadd_vv_disjoint_or:
1434; CHECK:       # %bb.0:
1435; CHECK-NEXT:    vsetvli a0, zero, e16, mf2, ta, ma
1436; CHECK-NEXT:    vor.vv v9, v8, v9
1437; CHECK-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
1438; CHECK-NEXT:    vsext.vf2 v8, v9
1439; CHECK-NEXT:    ret
1440  %x.i32 = sext <vscale x 2 x i16> %x.i16 to <vscale x 2 x i32>
1441  %y.i32 = sext <vscale x 2 x i16> %y.i16 to <vscale x 2 x i32>
1442  %or = or disjoint <vscale x 2 x i32> %x.i32, %y.i32
1443  ret <vscale x 2 x i32> %or
1444}
1445
1446define <vscale x 2 x i32> @vwaddu_wv_disjoint_or(<vscale x 2 x i32> %x.i32, <vscale x 2 x i16> %y.i16) {
1447; CHECK-LABEL: vwaddu_wv_disjoint_or:
1448; CHECK:       # %bb.0:
1449; CHECK-NEXT:    vsetvli a0, zero, e16, mf2, ta, ma
1450; CHECK-NEXT:    vwaddu.wv v8, v8, v9
1451; CHECK-NEXT:    ret
1452  %y.i32 = zext <vscale x 2 x i16> %y.i16 to <vscale x 2 x i32>
1453  %or = or disjoint <vscale x 2 x i32> %x.i32, %y.i32
1454  ret <vscale x 2 x i32> %or
1455}
1456
1457define <vscale x 2 x i32> @vwadd_wv_disjoint_or(<vscale x 2 x i32> %x.i32, <vscale x 2 x i16> %y.i16) {
1458; CHECK-LABEL: vwadd_wv_disjoint_or:
1459; CHECK:       # %bb.0:
1460; CHECK-NEXT:    vsetvli a0, zero, e16, mf2, ta, ma
1461; CHECK-NEXT:    vwadd.wv v8, v8, v9
1462; CHECK-NEXT:    ret
1463  %y.i32 = sext <vscale x 2 x i16> %y.i16 to <vscale x 2 x i32>
1464  %or = or disjoint <vscale x 2 x i32> %x.i32, %y.i32
1465  ret <vscale x 2 x i32> %or
1466}
1467
1468define <vscale x 8 x i64> @vwadd_vx_splat_zext(<vscale x 8 x i32> %va, i32 %b) {
1469; RV32-LABEL: vwadd_vx_splat_zext:
1470; RV32:       # %bb.0:
1471; RV32-NEXT:    addi sp, sp, -16
1472; RV32-NEXT:    .cfi_def_cfa_offset 16
1473; RV32-NEXT:    sw a0, 8(sp)
1474; RV32-NEXT:    sw zero, 12(sp)
1475; RV32-NEXT:    addi a0, sp, 8
1476; RV32-NEXT:    vsetvli a1, zero, e32, m4, ta, ma
1477; RV32-NEXT:    vlse64.v v16, (a0), zero
1478; RV32-NEXT:    vwaddu.wv v16, v16, v8
1479; RV32-NEXT:    vmv8r.v v8, v16
1480; RV32-NEXT:    addi sp, sp, 16
1481; RV32-NEXT:    .cfi_def_cfa_offset 0
1482; RV32-NEXT:    ret
1483;
1484; RV64-LABEL: vwadd_vx_splat_zext:
1485; RV64:       # %bb.0:
1486; RV64-NEXT:    vsetvli a1, zero, e32, m4, ta, ma
1487; RV64-NEXT:    vwaddu.vx v16, v8, a0
1488; RV64-NEXT:    vmv8r.v v8, v16
1489; RV64-NEXT:    ret
1490  %zb = zext i32 %b to i64
1491  %head = insertelement <vscale x 8 x i64> poison, i64 %zb, i32 0
1492  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
1493  %vc = zext <vscale x 8 x i32> %va to <vscale x 8 x i64>
1494  %ve = add <vscale x 8 x i64> %vc, %splat
1495  ret <vscale x 8 x i64> %ve
1496}
1497
1498define <vscale x 8 x i32> @vwadd_vx_splat_zext_i1(<vscale x 8 x i1> %va, i16 %b) {
1499; RV32-LABEL: vwadd_vx_splat_zext_i1:
1500; RV32:       # %bb.0:
1501; RV32-NEXT:    slli a0, a0, 16
1502; RV32-NEXT:    srli a0, a0, 16
1503; RV32-NEXT:    vsetvli a1, zero, e32, m4, ta, ma
1504; RV32-NEXT:    vmv.v.x v8, a0
1505; RV32-NEXT:    addi a0, a0, 1
1506; RV32-NEXT:    vmerge.vxm v8, v8, a0, v0
1507; RV32-NEXT:    ret
1508;
1509; RV64-LABEL: vwadd_vx_splat_zext_i1:
1510; RV64:       # %bb.0:
1511; RV64-NEXT:    slli a0, a0, 48
1512; RV64-NEXT:    srli a0, a0, 48
1513; RV64-NEXT:    vsetvli a1, zero, e16, m2, ta, ma
1514; RV64-NEXT:    vmv.v.x v12, a0
1515; RV64-NEXT:    vsetvli zero, zero, e32, m4, ta, ma
1516; RV64-NEXT:    vmv.v.x v8, a0
1517; RV64-NEXT:    li a0, 1
1518; RV64-NEXT:    vsetvli zero, zero, e16, m2, ta, mu
1519; RV64-NEXT:    vwaddu.vx v8, v12, a0, v0.t
1520; RV64-NEXT:    ret
1521  %zb = zext i16 %b to i32
1522  %head = insertelement <vscale x 8 x i32> poison, i32 %zb, i32 0
1523  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
1524  %vc = zext <vscale x 8 x i1> %va to <vscale x 8 x i32>
1525  %ve = add <vscale x 8 x i32> %vc, %splat
1526  ret <vscale x 8 x i32> %ve
1527}
1528
1529define <vscale x 8 x i64> @vwadd_wx_splat_zext(<vscale x 8 x i64> %va, i32 %b) {
1530; RV32-LABEL: vwadd_wx_splat_zext:
1531; RV32:       # %bb.0:
1532; RV32-NEXT:    addi sp, sp, -16
1533; RV32-NEXT:    .cfi_def_cfa_offset 16
1534; RV32-NEXT:    sw a0, 8(sp)
1535; RV32-NEXT:    sw zero, 12(sp)
1536; RV32-NEXT:    addi a0, sp, 8
1537; RV32-NEXT:    vsetvli a1, zero, e64, m8, ta, ma
1538; RV32-NEXT:    vlse64.v v16, (a0), zero
1539; RV32-NEXT:    vadd.vv v8, v8, v16
1540; RV32-NEXT:    addi sp, sp, 16
1541; RV32-NEXT:    .cfi_def_cfa_offset 0
1542; RV32-NEXT:    ret
1543;
1544; RV64-LABEL: vwadd_wx_splat_zext:
1545; RV64:       # %bb.0:
1546; RV64-NEXT:    slli a0, a0, 32
1547; RV64-NEXT:    srli a0, a0, 32
1548; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, ma
1549; RV64-NEXT:    vadd.vx v8, v8, a0
1550; RV64-NEXT:    ret
1551  %zb = zext i32 %b to i64
1552  %head = insertelement <vscale x 8 x i64> poison, i64 %zb, i32 0
1553  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
1554  %ve = add <vscale x 8 x i64> %va, %splat
1555  ret <vscale x 8 x i64> %ve
1556}
1557
1558define <vscale x 8 x i64> @vwadd_vx_splat_sext(<vscale x 8 x i32> %va, i32 %b) {
1559; CHECK-LABEL: vwadd_vx_splat_sext:
1560; CHECK:       # %bb.0:
1561; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, ma
1562; CHECK-NEXT:    vwadd.vx v16, v8, a0
1563; CHECK-NEXT:    vmv8r.v v8, v16
1564; CHECK-NEXT:    ret
1565  %sb = sext i32 %b to i64
1566  %head = insertelement <vscale x 8 x i64> poison, i64 %sb, i32 0
1567  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
1568  %vc = sext <vscale x 8 x i32> %va to <vscale x 8 x i64>
1569  %ve = add <vscale x 8 x i64> %vc, %splat
1570  ret <vscale x 8 x i64> %ve
1571}
1572
1573define <vscale x 8 x i32> @vwadd_vx_splat_sext_i1(<vscale x 8 x i1> %va, i16 %b) {
1574; RV32-LABEL: vwadd_vx_splat_sext_i1:
1575; RV32:       # %bb.0:
1576; RV32-NEXT:    slli a0, a0, 16
1577; RV32-NEXT:    srai a0, a0, 16
1578; RV32-NEXT:    vsetvli a1, zero, e32, m4, ta, ma
1579; RV32-NEXT:    vmv.v.x v8, a0
1580; RV32-NEXT:    addi a0, a0, -1
1581; RV32-NEXT:    vmerge.vxm v8, v8, a0, v0
1582; RV32-NEXT:    ret
1583;
1584; RV64-LABEL: vwadd_vx_splat_sext_i1:
1585; RV64:       # %bb.0:
1586; RV64-NEXT:    slli a0, a0, 48
1587; RV64-NEXT:    srai a0, a0, 48
1588; RV64-NEXT:    vsetvli a1, zero, e16, m2, ta, ma
1589; RV64-NEXT:    vmv.v.x v12, a0
1590; RV64-NEXT:    vsetvli zero, zero, e32, m4, ta, ma
1591; RV64-NEXT:    vmv.v.x v8, a0
1592; RV64-NEXT:    li a0, 1
1593; RV64-NEXT:    vsetvli zero, zero, e16, m2, ta, mu
1594; RV64-NEXT:    vwsub.vx v8, v12, a0, v0.t
1595; RV64-NEXT:    ret
1596  %sb = sext i16 %b to i32
1597  %head = insertelement <vscale x 8 x i32> poison, i32 %sb, i32 0
1598  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
1599  %vc = sext <vscale x 8 x i1> %va to <vscale x 8 x i32>
1600  %ve = add <vscale x 8 x i32> %vc, %splat
1601  ret <vscale x 8 x i32> %ve
1602}
1603
1604define <vscale x 8 x i64> @vwadd_wx_splat_sext(<vscale x 8 x i64> %va, i32 %b) {
1605; RV32-LABEL: vwadd_wx_splat_sext:
1606; RV32:       # %bb.0:
1607; RV32-NEXT:    vsetvli a1, zero, e64, m8, ta, ma
1608; RV32-NEXT:    vadd.vx v8, v8, a0
1609; RV32-NEXT:    ret
1610;
1611; RV64-LABEL: vwadd_wx_splat_sext:
1612; RV64:       # %bb.0:
1613; RV64-NEXT:    sext.w a0, a0
1614; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, ma
1615; RV64-NEXT:    vadd.vx v8, v8, a0
1616; RV64-NEXT:    ret
1617  %sb = sext i32 %b to i64
1618  %head = insertelement <vscale x 8 x i64> poison, i64 %sb, i32 0
1619  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
1620  %ve = add <vscale x 8 x i64> %va, %splat
1621  ret <vscale x 8 x i64> %ve
1622}
1623