1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s \ 3; RUN: | FileCheck %s --check-prefixes=CHECK,RV32 4; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s \ 5; RUN: | FileCheck %s --check-prefixes=CHECK,RV64 6 7declare <vscale x 8 x i7> @llvm.vp.usub.sat.nxv8i7(<vscale x 8 x i7>, <vscale x 8 x i7>, <vscale x 8 x i1>, i32) 8 9define <vscale x 8 x i7> @vssubu_vx_nxv8i7(<vscale x 8 x i7> %a, i7 signext %b, <vscale x 8 x i1> %mask, i32 zeroext %evl) { 10; CHECK-LABEL: vssubu_vx_nxv8i7: 11; CHECK: # %bb.0: 12; CHECK-NEXT: li a2, 127 13; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma 14; CHECK-NEXT: vmv.v.x v9, a0 15; CHECK-NEXT: vand.vx v8, v8, a2 16; CHECK-NEXT: vand.vx v9, v9, a2 17; CHECK-NEXT: vssubu.vv v8, v8, v9, v0.t 18; CHECK-NEXT: ret 19 %elt.head = insertelement <vscale x 8 x i7> poison, i7 %b, i32 0 20 %vb = shufflevector <vscale x 8 x i7> %elt.head, <vscale x 8 x i7> poison, <vscale x 8 x i32> zeroinitializer 21 %v = call <vscale x 8 x i7> @llvm.vp.usub.sat.nxv8i7(<vscale x 8 x i7> %a, <vscale x 8 x i7> %vb, <vscale x 8 x i1> %mask, i32 %evl) 22 ret <vscale x 8 x i7> %v 23} 24 25declare <vscale x 1 x i8> @llvm.vp.usub.sat.nxv1i8(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i32) 26 27define <vscale x 1 x i8> @vssubu_vv_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %b, <vscale x 1 x i1> %m, i32 zeroext %evl) { 28; CHECK-LABEL: vssubu_vv_nxv1i8: 29; CHECK: # %bb.0: 30; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma 31; CHECK-NEXT: vssubu.vv v8, v8, v9, v0.t 32; CHECK-NEXT: ret 33 %v = call <vscale x 1 x i8> @llvm.vp.usub.sat.nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %b, <vscale x 1 x i1> %m, i32 %evl) 34 ret <vscale x 1 x i8> %v 35} 36 37define <vscale x 1 x i8> @vssubu_vv_nxv1i8_unmasked(<vscale x 1 x i8> %va, <vscale x 1 x i8> %b, i32 zeroext %evl) { 38; CHECK-LABEL: vssubu_vv_nxv1i8_unmasked: 39; CHECK: # %bb.0: 40; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma 41; CHECK-NEXT: vssubu.vv v8, v8, v9 42; CHECK-NEXT: ret 43 %v = call <vscale x 1 x i8> @llvm.vp.usub.sat.nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %b, <vscale x 1 x i1> splat (i1 true), i32 %evl) 44 ret <vscale x 1 x i8> %v 45} 46 47define <vscale x 1 x i8> @vssubu_vx_nxv1i8(<vscale x 1 x i8> %va, i8 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) { 48; CHECK-LABEL: vssubu_vx_nxv1i8: 49; CHECK: # %bb.0: 50; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma 51; CHECK-NEXT: vssubu.vx v8, v8, a0, v0.t 52; CHECK-NEXT: ret 53 %elt.head = insertelement <vscale x 1 x i8> poison, i8 %b, i32 0 54 %vb = shufflevector <vscale x 1 x i8> %elt.head, <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer 55 %v = call <vscale x 1 x i8> @llvm.vp.usub.sat.nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %vb, <vscale x 1 x i1> %m, i32 %evl) 56 ret <vscale x 1 x i8> %v 57} 58 59define <vscale x 1 x i8> @vssubu_vx_nxv1i8_commute(<vscale x 1 x i8> %va, i8 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) { 60; CHECK-LABEL: vssubu_vx_nxv1i8_commute: 61; CHECK: # %bb.0: 62; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma 63; CHECK-NEXT: vmv.v.x v9, a0 64; CHECK-NEXT: vssubu.vv v8, v9, v8, v0.t 65; CHECK-NEXT: ret 66 %elt.head = insertelement <vscale x 1 x i8> poison, i8 %b, i32 0 67 %vb = shufflevector <vscale x 1 x i8> %elt.head, <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer 68 %v = call <vscale x 1 x i8> @llvm.vp.usub.sat.nxv1i8(<vscale x 1 x i8> %vb, <vscale x 1 x i8> %va, <vscale x 1 x i1> %m, i32 %evl) 69 ret <vscale x 1 x i8> %v 70} 71 72define <vscale x 1 x i8> @vssubu_vx_nxv1i8_unmasked(<vscale x 1 x i8> %va, i8 %b, i32 zeroext %evl) { 73; CHECK-LABEL: vssubu_vx_nxv1i8_unmasked: 74; CHECK: # %bb.0: 75; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma 76; CHECK-NEXT: vssubu.vx v8, v8, a0 77; CHECK-NEXT: ret 78 %elt.head = insertelement <vscale x 1 x i8> poison, i8 %b, i32 0 79 %vb = shufflevector <vscale x 1 x i8> %elt.head, <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer 80 %v = call <vscale x 1 x i8> @llvm.vp.usub.sat.nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %vb, <vscale x 1 x i1> splat (i1 true), i32 %evl) 81 ret <vscale x 1 x i8> %v 82} 83 84define <vscale x 1 x i8> @vssubu_vi_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) { 85; CHECK-LABEL: vssubu_vi_nxv1i8: 86; CHECK: # %bb.0: 87; CHECK-NEXT: li a1, -1 88; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma 89; CHECK-NEXT: vssubu.vx v8, v8, a1, v0.t 90; CHECK-NEXT: ret 91 %v = call <vscale x 1 x i8> @llvm.vp.usub.sat.nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> splat (i8 -1), <vscale x 1 x i1> %m, i32 %evl) 92 ret <vscale x 1 x i8> %v 93} 94 95define <vscale x 1 x i8> @vssubu_vi_nxv1i8_unmasked(<vscale x 1 x i8> %va, i32 zeroext %evl) { 96; CHECK-LABEL: vssubu_vi_nxv1i8_unmasked: 97; CHECK: # %bb.0: 98; CHECK-NEXT: li a1, -1 99; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma 100; CHECK-NEXT: vssubu.vx v8, v8, a1 101; CHECK-NEXT: ret 102 %v = call <vscale x 1 x i8> @llvm.vp.usub.sat.nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> splat (i8 -1), <vscale x 1 x i1> splat (i1 true), i32 %evl) 103 ret <vscale x 1 x i8> %v 104} 105 106declare <vscale x 2 x i8> @llvm.vp.usub.sat.nxv2i8(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i32) 107 108define <vscale x 2 x i8> @vssubu_vv_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %b, <vscale x 2 x i1> %m, i32 zeroext %evl) { 109; CHECK-LABEL: vssubu_vv_nxv2i8: 110; CHECK: # %bb.0: 111; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma 112; CHECK-NEXT: vssubu.vv v8, v8, v9, v0.t 113; CHECK-NEXT: ret 114 %v = call <vscale x 2 x i8> @llvm.vp.usub.sat.nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %b, <vscale x 2 x i1> %m, i32 %evl) 115 ret <vscale x 2 x i8> %v 116} 117 118define <vscale x 2 x i8> @vssubu_vv_nxv2i8_unmasked(<vscale x 2 x i8> %va, <vscale x 2 x i8> %b, i32 zeroext %evl) { 119; CHECK-LABEL: vssubu_vv_nxv2i8_unmasked: 120; CHECK: # %bb.0: 121; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma 122; CHECK-NEXT: vssubu.vv v8, v8, v9 123; CHECK-NEXT: ret 124 %v = call <vscale x 2 x i8> @llvm.vp.usub.sat.nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %b, <vscale x 2 x i1> splat (i1 true), i32 %evl) 125 ret <vscale x 2 x i8> %v 126} 127 128define <vscale x 2 x i8> @vssubu_vx_nxv2i8(<vscale x 2 x i8> %va, i8 %b, <vscale x 2 x i1> %m, i32 zeroext %evl) { 129; CHECK-LABEL: vssubu_vx_nxv2i8: 130; CHECK: # %bb.0: 131; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma 132; CHECK-NEXT: vssubu.vx v8, v8, a0, v0.t 133; CHECK-NEXT: ret 134 %elt.head = insertelement <vscale x 2 x i8> poison, i8 %b, i32 0 135 %vb = shufflevector <vscale x 2 x i8> %elt.head, <vscale x 2 x i8> poison, <vscale x 2 x i32> zeroinitializer 136 %v = call <vscale x 2 x i8> @llvm.vp.usub.sat.nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %vb, <vscale x 2 x i1> %m, i32 %evl) 137 ret <vscale x 2 x i8> %v 138} 139 140define <vscale x 2 x i8> @vssubu_vx_nxv2i8_unmasked(<vscale x 2 x i8> %va, i8 %b, i32 zeroext %evl) { 141; CHECK-LABEL: vssubu_vx_nxv2i8_unmasked: 142; CHECK: # %bb.0: 143; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma 144; CHECK-NEXT: vssubu.vx v8, v8, a0 145; CHECK-NEXT: ret 146 %elt.head = insertelement <vscale x 2 x i8> poison, i8 %b, i32 0 147 %vb = shufflevector <vscale x 2 x i8> %elt.head, <vscale x 2 x i8> poison, <vscale x 2 x i32> zeroinitializer 148 %v = call <vscale x 2 x i8> @llvm.vp.usub.sat.nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %vb, <vscale x 2 x i1> splat (i1 true), i32 %evl) 149 ret <vscale x 2 x i8> %v 150} 151 152define <vscale x 2 x i8> @vssubu_vi_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) { 153; CHECK-LABEL: vssubu_vi_nxv2i8: 154; CHECK: # %bb.0: 155; CHECK-NEXT: li a1, -1 156; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma 157; CHECK-NEXT: vssubu.vx v8, v8, a1, v0.t 158; CHECK-NEXT: ret 159 %v = call <vscale x 2 x i8> @llvm.vp.usub.sat.nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> splat (i8 -1), <vscale x 2 x i1> %m, i32 %evl) 160 ret <vscale x 2 x i8> %v 161} 162 163define <vscale x 2 x i8> @vssubu_vi_nxv2i8_unmasked(<vscale x 2 x i8> %va, i32 zeroext %evl) { 164; CHECK-LABEL: vssubu_vi_nxv2i8_unmasked: 165; CHECK: # %bb.0: 166; CHECK-NEXT: li a1, -1 167; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma 168; CHECK-NEXT: vssubu.vx v8, v8, a1 169; CHECK-NEXT: ret 170 %v = call <vscale x 2 x i8> @llvm.vp.usub.sat.nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> splat (i8 -1), <vscale x 2 x i1> splat (i1 true), i32 %evl) 171 ret <vscale x 2 x i8> %v 172} 173 174declare <vscale x 3 x i8> @llvm.vp.usub.sat.nxv3i8(<vscale x 3 x i8>, <vscale x 3 x i8>, <vscale x 3 x i1>, i32) 175 176define <vscale x 3 x i8> @vssubu_vv_nxv3i8(<vscale x 3 x i8> %va, <vscale x 3 x i8> %b, <vscale x 3 x i1> %m, i32 zeroext %evl) { 177; CHECK-LABEL: vssubu_vv_nxv3i8: 178; CHECK: # %bb.0: 179; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma 180; CHECK-NEXT: vssubu.vv v8, v8, v9, v0.t 181; CHECK-NEXT: ret 182 %v = call <vscale x 3 x i8> @llvm.vp.usub.sat.nxv3i8(<vscale x 3 x i8> %va, <vscale x 3 x i8> %b, <vscale x 3 x i1> %m, i32 %evl) 183 ret <vscale x 3 x i8> %v 184} 185 186define <vscale x 3 x i8> @vssubu_vv_nxv3i8_unmasked(<vscale x 3 x i8> %va, <vscale x 3 x i8> %b, i32 zeroext %evl) { 187; CHECK-LABEL: vssubu_vv_nxv3i8_unmasked: 188; CHECK: # %bb.0: 189; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma 190; CHECK-NEXT: vssubu.vv v8, v8, v9 191; CHECK-NEXT: ret 192 %v = call <vscale x 3 x i8> @llvm.vp.usub.sat.nxv3i8(<vscale x 3 x i8> %va, <vscale x 3 x i8> %b, <vscale x 3 x i1> splat (i1 true), i32 %evl) 193 ret <vscale x 3 x i8> %v 194} 195 196define <vscale x 3 x i8> @vssubu_vx_nxv3i8(<vscale x 3 x i8> %va, i8 %b, <vscale x 3 x i1> %m, i32 zeroext %evl) { 197; CHECK-LABEL: vssubu_vx_nxv3i8: 198; CHECK: # %bb.0: 199; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma 200; CHECK-NEXT: vssubu.vx v8, v8, a0, v0.t 201; CHECK-NEXT: ret 202 %elt.head = insertelement <vscale x 3 x i8> poison, i8 %b, i32 0 203 %vb = shufflevector <vscale x 3 x i8> %elt.head, <vscale x 3 x i8> poison, <vscale x 3 x i32> zeroinitializer 204 %v = call <vscale x 3 x i8> @llvm.vp.usub.sat.nxv3i8(<vscale x 3 x i8> %va, <vscale x 3 x i8> %vb, <vscale x 3 x i1> %m, i32 %evl) 205 ret <vscale x 3 x i8> %v 206} 207 208define <vscale x 3 x i8> @vssubu_vx_nxv3i8_unmasked(<vscale x 3 x i8> %va, i8 %b, i32 zeroext %evl) { 209; CHECK-LABEL: vssubu_vx_nxv3i8_unmasked: 210; CHECK: # %bb.0: 211; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma 212; CHECK-NEXT: vssubu.vx v8, v8, a0 213; CHECK-NEXT: ret 214 %elt.head = insertelement <vscale x 3 x i8> poison, i8 %b, i32 0 215 %vb = shufflevector <vscale x 3 x i8> %elt.head, <vscale x 3 x i8> poison, <vscale x 3 x i32> zeroinitializer 216 %v = call <vscale x 3 x i8> @llvm.vp.usub.sat.nxv3i8(<vscale x 3 x i8> %va, <vscale x 3 x i8> %vb, <vscale x 3 x i1> splat (i1 true), i32 %evl) 217 ret <vscale x 3 x i8> %v 218} 219 220define <vscale x 3 x i8> @vssubu_vi_nxv3i8(<vscale x 3 x i8> %va, <vscale x 3 x i1> %m, i32 zeroext %evl) { 221; CHECK-LABEL: vssubu_vi_nxv3i8: 222; CHECK: # %bb.0: 223; CHECK-NEXT: li a1, -1 224; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma 225; CHECK-NEXT: vssubu.vx v8, v8, a1, v0.t 226; CHECK-NEXT: ret 227 %v = call <vscale x 3 x i8> @llvm.vp.usub.sat.nxv3i8(<vscale x 3 x i8> %va, <vscale x 3 x i8> splat (i8 -1), <vscale x 3 x i1> %m, i32 %evl) 228 ret <vscale x 3 x i8> %v 229} 230 231define <vscale x 3 x i8> @vssubu_vi_nxv3i8_unmasked(<vscale x 3 x i8> %va, i32 zeroext %evl) { 232; CHECK-LABEL: vssubu_vi_nxv3i8_unmasked: 233; CHECK: # %bb.0: 234; CHECK-NEXT: li a1, -1 235; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma 236; CHECK-NEXT: vssubu.vx v8, v8, a1 237; CHECK-NEXT: ret 238 %v = call <vscale x 3 x i8> @llvm.vp.usub.sat.nxv3i8(<vscale x 3 x i8> %va, <vscale x 3 x i8> splat (i8 -1), <vscale x 3 x i1> splat (i1 true), i32 %evl) 239 ret <vscale x 3 x i8> %v 240} 241 242declare <vscale x 4 x i8> @llvm.vp.usub.sat.nxv4i8(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i32) 243 244define <vscale x 4 x i8> @vssubu_vv_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %b, <vscale x 4 x i1> %m, i32 zeroext %evl) { 245; CHECK-LABEL: vssubu_vv_nxv4i8: 246; CHECK: # %bb.0: 247; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma 248; CHECK-NEXT: vssubu.vv v8, v8, v9, v0.t 249; CHECK-NEXT: ret 250 %v = call <vscale x 4 x i8> @llvm.vp.usub.sat.nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %b, <vscale x 4 x i1> %m, i32 %evl) 251 ret <vscale x 4 x i8> %v 252} 253 254define <vscale x 4 x i8> @vssubu_vv_nxv4i8_unmasked(<vscale x 4 x i8> %va, <vscale x 4 x i8> %b, i32 zeroext %evl) { 255; CHECK-LABEL: vssubu_vv_nxv4i8_unmasked: 256; CHECK: # %bb.0: 257; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma 258; CHECK-NEXT: vssubu.vv v8, v8, v9 259; CHECK-NEXT: ret 260 %v = call <vscale x 4 x i8> @llvm.vp.usub.sat.nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %b, <vscale x 4 x i1> splat (i1 true), i32 %evl) 261 ret <vscale x 4 x i8> %v 262} 263 264define <vscale x 4 x i8> @vssubu_vx_nxv4i8(<vscale x 4 x i8> %va, i8 %b, <vscale x 4 x i1> %m, i32 zeroext %evl) { 265; CHECK-LABEL: vssubu_vx_nxv4i8: 266; CHECK: # %bb.0: 267; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma 268; CHECK-NEXT: vssubu.vx v8, v8, a0, v0.t 269; CHECK-NEXT: ret 270 %elt.head = insertelement <vscale x 4 x i8> poison, i8 %b, i32 0 271 %vb = shufflevector <vscale x 4 x i8> %elt.head, <vscale x 4 x i8> poison, <vscale x 4 x i32> zeroinitializer 272 %v = call <vscale x 4 x i8> @llvm.vp.usub.sat.nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %vb, <vscale x 4 x i1> %m, i32 %evl) 273 ret <vscale x 4 x i8> %v 274} 275 276define <vscale x 4 x i8> @vssubu_vx_nxv4i8_unmasked(<vscale x 4 x i8> %va, i8 %b, i32 zeroext %evl) { 277; CHECK-LABEL: vssubu_vx_nxv4i8_unmasked: 278; CHECK: # %bb.0: 279; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma 280; CHECK-NEXT: vssubu.vx v8, v8, a0 281; CHECK-NEXT: ret 282 %elt.head = insertelement <vscale x 4 x i8> poison, i8 %b, i32 0 283 %vb = shufflevector <vscale x 4 x i8> %elt.head, <vscale x 4 x i8> poison, <vscale x 4 x i32> zeroinitializer 284 %v = call <vscale x 4 x i8> @llvm.vp.usub.sat.nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %vb, <vscale x 4 x i1> splat (i1 true), i32 %evl) 285 ret <vscale x 4 x i8> %v 286} 287 288define <vscale x 4 x i8> @vssubu_vi_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) { 289; CHECK-LABEL: vssubu_vi_nxv4i8: 290; CHECK: # %bb.0: 291; CHECK-NEXT: li a1, -1 292; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma 293; CHECK-NEXT: vssubu.vx v8, v8, a1, v0.t 294; CHECK-NEXT: ret 295 %v = call <vscale x 4 x i8> @llvm.vp.usub.sat.nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> splat (i8 -1), <vscale x 4 x i1> %m, i32 %evl) 296 ret <vscale x 4 x i8> %v 297} 298 299define <vscale x 4 x i8> @vssubu_vi_nxv4i8_unmasked(<vscale x 4 x i8> %va, i32 zeroext %evl) { 300; CHECK-LABEL: vssubu_vi_nxv4i8_unmasked: 301; CHECK: # %bb.0: 302; CHECK-NEXT: li a1, -1 303; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma 304; CHECK-NEXT: vssubu.vx v8, v8, a1 305; CHECK-NEXT: ret 306 %v = call <vscale x 4 x i8> @llvm.vp.usub.sat.nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> splat (i8 -1), <vscale x 4 x i1> splat (i1 true), i32 %evl) 307 ret <vscale x 4 x i8> %v 308} 309 310declare <vscale x 8 x i8> @llvm.vp.usub.sat.nxv8i8(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i1>, i32) 311 312define <vscale x 8 x i8> @vssubu_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %b, <vscale x 8 x i1> %m, i32 zeroext %evl) { 313; CHECK-LABEL: vssubu_vv_nxv8i8: 314; CHECK: # %bb.0: 315; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma 316; CHECK-NEXT: vssubu.vv v8, v8, v9, v0.t 317; CHECK-NEXT: ret 318 %v = call <vscale x 8 x i8> @llvm.vp.usub.sat.nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %b, <vscale x 8 x i1> %m, i32 %evl) 319 ret <vscale x 8 x i8> %v 320} 321 322define <vscale x 8 x i8> @vssubu_vv_nxv8i8_unmasked(<vscale x 8 x i8> %va, <vscale x 8 x i8> %b, i32 zeroext %evl) { 323; CHECK-LABEL: vssubu_vv_nxv8i8_unmasked: 324; CHECK: # %bb.0: 325; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma 326; CHECK-NEXT: vssubu.vv v8, v8, v9 327; CHECK-NEXT: ret 328 %v = call <vscale x 8 x i8> @llvm.vp.usub.sat.nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %b, <vscale x 8 x i1> splat (i1 true), i32 %evl) 329 ret <vscale x 8 x i8> %v 330} 331 332define <vscale x 8 x i8> @vssubu_vx_nxv8i8(<vscale x 8 x i8> %va, i8 %b, <vscale x 8 x i1> %m, i32 zeroext %evl) { 333; CHECK-LABEL: vssubu_vx_nxv8i8: 334; CHECK: # %bb.0: 335; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma 336; CHECK-NEXT: vssubu.vx v8, v8, a0, v0.t 337; CHECK-NEXT: ret 338 %elt.head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0 339 %vb = shufflevector <vscale x 8 x i8> %elt.head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer 340 %v = call <vscale x 8 x i8> @llvm.vp.usub.sat.nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb, <vscale x 8 x i1> %m, i32 %evl) 341 ret <vscale x 8 x i8> %v 342} 343 344define <vscale x 8 x i8> @vssubu_vx_nxv8i8_unmasked(<vscale x 8 x i8> %va, i8 %b, i32 zeroext %evl) { 345; CHECK-LABEL: vssubu_vx_nxv8i8_unmasked: 346; CHECK: # %bb.0: 347; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma 348; CHECK-NEXT: vssubu.vx v8, v8, a0 349; CHECK-NEXT: ret 350 %elt.head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0 351 %vb = shufflevector <vscale x 8 x i8> %elt.head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer 352 %v = call <vscale x 8 x i8> @llvm.vp.usub.sat.nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb, <vscale x 8 x i1> splat (i1 true), i32 %evl) 353 ret <vscale x 8 x i8> %v 354} 355 356define <vscale x 8 x i8> @vssubu_vi_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) { 357; CHECK-LABEL: vssubu_vi_nxv8i8: 358; CHECK: # %bb.0: 359; CHECK-NEXT: li a1, -1 360; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma 361; CHECK-NEXT: vssubu.vx v8, v8, a1, v0.t 362; CHECK-NEXT: ret 363 %v = call <vscale x 8 x i8> @llvm.vp.usub.sat.nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> splat (i8 -1), <vscale x 8 x i1> %m, i32 %evl) 364 ret <vscale x 8 x i8> %v 365} 366 367define <vscale x 8 x i8> @vssubu_vi_nxv8i8_unmasked(<vscale x 8 x i8> %va, i32 zeroext %evl) { 368; CHECK-LABEL: vssubu_vi_nxv8i8_unmasked: 369; CHECK: # %bb.0: 370; CHECK-NEXT: li a1, -1 371; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma 372; CHECK-NEXT: vssubu.vx v8, v8, a1 373; CHECK-NEXT: ret 374 %v = call <vscale x 8 x i8> @llvm.vp.usub.sat.nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> splat (i8 -1), <vscale x 8 x i1> splat (i1 true), i32 %evl) 375 ret <vscale x 8 x i8> %v 376} 377 378declare <vscale x 16 x i8> @llvm.vp.usub.sat.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i1>, i32) 379 380define <vscale x 16 x i8> @vssubu_vv_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %b, <vscale x 16 x i1> %m, i32 zeroext %evl) { 381; CHECK-LABEL: vssubu_vv_nxv16i8: 382; CHECK: # %bb.0: 383; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma 384; CHECK-NEXT: vssubu.vv v8, v8, v10, v0.t 385; CHECK-NEXT: ret 386 %v = call <vscale x 16 x i8> @llvm.vp.usub.sat.nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %b, <vscale x 16 x i1> %m, i32 %evl) 387 ret <vscale x 16 x i8> %v 388} 389 390define <vscale x 16 x i8> @vssubu_vv_nxv16i8_unmasked(<vscale x 16 x i8> %va, <vscale x 16 x i8> %b, i32 zeroext %evl) { 391; CHECK-LABEL: vssubu_vv_nxv16i8_unmasked: 392; CHECK: # %bb.0: 393; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma 394; CHECK-NEXT: vssubu.vv v8, v8, v10 395; CHECK-NEXT: ret 396 %v = call <vscale x 16 x i8> @llvm.vp.usub.sat.nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %b, <vscale x 16 x i1> splat (i1 true), i32 %evl) 397 ret <vscale x 16 x i8> %v 398} 399 400define <vscale x 16 x i8> @vssubu_vx_nxv16i8(<vscale x 16 x i8> %va, i8 %b, <vscale x 16 x i1> %m, i32 zeroext %evl) { 401; CHECK-LABEL: vssubu_vx_nxv16i8: 402; CHECK: # %bb.0: 403; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma 404; CHECK-NEXT: vssubu.vx v8, v8, a0, v0.t 405; CHECK-NEXT: ret 406 %elt.head = insertelement <vscale x 16 x i8> poison, i8 %b, i32 0 407 %vb = shufflevector <vscale x 16 x i8> %elt.head, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer 408 %v = call <vscale x 16 x i8> @llvm.vp.usub.sat.nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %vb, <vscale x 16 x i1> %m, i32 %evl) 409 ret <vscale x 16 x i8> %v 410} 411 412define <vscale x 16 x i8> @vssubu_vx_nxv16i8_unmasked(<vscale x 16 x i8> %va, i8 %b, i32 zeroext %evl) { 413; CHECK-LABEL: vssubu_vx_nxv16i8_unmasked: 414; CHECK: # %bb.0: 415; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma 416; CHECK-NEXT: vssubu.vx v8, v8, a0 417; CHECK-NEXT: ret 418 %elt.head = insertelement <vscale x 16 x i8> poison, i8 %b, i32 0 419 %vb = shufflevector <vscale x 16 x i8> %elt.head, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer 420 %v = call <vscale x 16 x i8> @llvm.vp.usub.sat.nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %vb, <vscale x 16 x i1> splat (i1 true), i32 %evl) 421 ret <vscale x 16 x i8> %v 422} 423 424define <vscale x 16 x i8> @vssubu_vi_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) { 425; CHECK-LABEL: vssubu_vi_nxv16i8: 426; CHECK: # %bb.0: 427; CHECK-NEXT: li a1, -1 428; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma 429; CHECK-NEXT: vssubu.vx v8, v8, a1, v0.t 430; CHECK-NEXT: ret 431 %v = call <vscale x 16 x i8> @llvm.vp.usub.sat.nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> splat (i8 -1), <vscale x 16 x i1> %m, i32 %evl) 432 ret <vscale x 16 x i8> %v 433} 434 435define <vscale x 16 x i8> @vssubu_vi_nxv16i8_unmasked(<vscale x 16 x i8> %va, i32 zeroext %evl) { 436; CHECK-LABEL: vssubu_vi_nxv16i8_unmasked: 437; CHECK: # %bb.0: 438; CHECK-NEXT: li a1, -1 439; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma 440; CHECK-NEXT: vssubu.vx v8, v8, a1 441; CHECK-NEXT: ret 442 %v = call <vscale x 16 x i8> @llvm.vp.usub.sat.nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> splat (i8 -1), <vscale x 16 x i1> splat (i1 true), i32 %evl) 443 ret <vscale x 16 x i8> %v 444} 445 446declare <vscale x 32 x i8> @llvm.vp.usub.sat.nxv32i8(<vscale x 32 x i8>, <vscale x 32 x i8>, <vscale x 32 x i1>, i32) 447 448define <vscale x 32 x i8> @vssubu_vv_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %b, <vscale x 32 x i1> %m, i32 zeroext %evl) { 449; CHECK-LABEL: vssubu_vv_nxv32i8: 450; CHECK: # %bb.0: 451; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma 452; CHECK-NEXT: vssubu.vv v8, v8, v12, v0.t 453; CHECK-NEXT: ret 454 %v = call <vscale x 32 x i8> @llvm.vp.usub.sat.nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %b, <vscale x 32 x i1> %m, i32 %evl) 455 ret <vscale x 32 x i8> %v 456} 457 458define <vscale x 32 x i8> @vssubu_vv_nxv32i8_unmasked(<vscale x 32 x i8> %va, <vscale x 32 x i8> %b, i32 zeroext %evl) { 459; CHECK-LABEL: vssubu_vv_nxv32i8_unmasked: 460; CHECK: # %bb.0: 461; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma 462; CHECK-NEXT: vssubu.vv v8, v8, v12 463; CHECK-NEXT: ret 464 %v = call <vscale x 32 x i8> @llvm.vp.usub.sat.nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %b, <vscale x 32 x i1> splat (i1 true), i32 %evl) 465 ret <vscale x 32 x i8> %v 466} 467 468define <vscale x 32 x i8> @vssubu_vx_nxv32i8(<vscale x 32 x i8> %va, i8 %b, <vscale x 32 x i1> %m, i32 zeroext %evl) { 469; CHECK-LABEL: vssubu_vx_nxv32i8: 470; CHECK: # %bb.0: 471; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma 472; CHECK-NEXT: vssubu.vx v8, v8, a0, v0.t 473; CHECK-NEXT: ret 474 %elt.head = insertelement <vscale x 32 x i8> poison, i8 %b, i32 0 475 %vb = shufflevector <vscale x 32 x i8> %elt.head, <vscale x 32 x i8> poison, <vscale x 32 x i32> zeroinitializer 476 %v = call <vscale x 32 x i8> @llvm.vp.usub.sat.nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %vb, <vscale x 32 x i1> %m, i32 %evl) 477 ret <vscale x 32 x i8> %v 478} 479 480define <vscale x 32 x i8> @vssubu_vx_nxv32i8_unmasked(<vscale x 32 x i8> %va, i8 %b, i32 zeroext %evl) { 481; CHECK-LABEL: vssubu_vx_nxv32i8_unmasked: 482; CHECK: # %bb.0: 483; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma 484; CHECK-NEXT: vssubu.vx v8, v8, a0 485; CHECK-NEXT: ret 486 %elt.head = insertelement <vscale x 32 x i8> poison, i8 %b, i32 0 487 %vb = shufflevector <vscale x 32 x i8> %elt.head, <vscale x 32 x i8> poison, <vscale x 32 x i32> zeroinitializer 488 %v = call <vscale x 32 x i8> @llvm.vp.usub.sat.nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %vb, <vscale x 32 x i1> splat (i1 true), i32 %evl) 489 ret <vscale x 32 x i8> %v 490} 491 492define <vscale x 32 x i8> @vssubu_vi_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) { 493; CHECK-LABEL: vssubu_vi_nxv32i8: 494; CHECK: # %bb.0: 495; CHECK-NEXT: li a1, -1 496; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma 497; CHECK-NEXT: vssubu.vx v8, v8, a1, v0.t 498; CHECK-NEXT: ret 499 %v = call <vscale x 32 x i8> @llvm.vp.usub.sat.nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> splat (i8 -1), <vscale x 32 x i1> %m, i32 %evl) 500 ret <vscale x 32 x i8> %v 501} 502 503define <vscale x 32 x i8> @vssubu_vi_nxv32i8_unmasked(<vscale x 32 x i8> %va, i32 zeroext %evl) { 504; CHECK-LABEL: vssubu_vi_nxv32i8_unmasked: 505; CHECK: # %bb.0: 506; CHECK-NEXT: li a1, -1 507; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma 508; CHECK-NEXT: vssubu.vx v8, v8, a1 509; CHECK-NEXT: ret 510 %v = call <vscale x 32 x i8> @llvm.vp.usub.sat.nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> splat (i8 -1), <vscale x 32 x i1> splat (i1 true), i32 %evl) 511 ret <vscale x 32 x i8> %v 512} 513 514declare <vscale x 64 x i8> @llvm.vp.usub.sat.nxv64i8(<vscale x 64 x i8>, <vscale x 64 x i8>, <vscale x 64 x i1>, i32) 515 516define <vscale x 64 x i8> @vssubu_vv_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %b, <vscale x 64 x i1> %m, i32 zeroext %evl) { 517; CHECK-LABEL: vssubu_vv_nxv64i8: 518; CHECK: # %bb.0: 519; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma 520; CHECK-NEXT: vssubu.vv v8, v8, v16, v0.t 521; CHECK-NEXT: ret 522 %v = call <vscale x 64 x i8> @llvm.vp.usub.sat.nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %b, <vscale x 64 x i1> %m, i32 %evl) 523 ret <vscale x 64 x i8> %v 524} 525 526define <vscale x 64 x i8> @vssubu_vv_nxv64i8_unmasked(<vscale x 64 x i8> %va, <vscale x 64 x i8> %b, i32 zeroext %evl) { 527; CHECK-LABEL: vssubu_vv_nxv64i8_unmasked: 528; CHECK: # %bb.0: 529; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma 530; CHECK-NEXT: vssubu.vv v8, v8, v16 531; CHECK-NEXT: ret 532 %v = call <vscale x 64 x i8> @llvm.vp.usub.sat.nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %b, <vscale x 64 x i1> splat (i1 true), i32 %evl) 533 ret <vscale x 64 x i8> %v 534} 535 536define <vscale x 64 x i8> @vssubu_vx_nxv64i8(<vscale x 64 x i8> %va, i8 %b, <vscale x 64 x i1> %m, i32 zeroext %evl) { 537; CHECK-LABEL: vssubu_vx_nxv64i8: 538; CHECK: # %bb.0: 539; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma 540; CHECK-NEXT: vssubu.vx v8, v8, a0, v0.t 541; CHECK-NEXT: ret 542 %elt.head = insertelement <vscale x 64 x i8> poison, i8 %b, i32 0 543 %vb = shufflevector <vscale x 64 x i8> %elt.head, <vscale x 64 x i8> poison, <vscale x 64 x i32> zeroinitializer 544 %v = call <vscale x 64 x i8> @llvm.vp.usub.sat.nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %vb, <vscale x 64 x i1> %m, i32 %evl) 545 ret <vscale x 64 x i8> %v 546} 547 548define <vscale x 64 x i8> @vssubu_vx_nxv64i8_unmasked(<vscale x 64 x i8> %va, i8 %b, i32 zeroext %evl) { 549; CHECK-LABEL: vssubu_vx_nxv64i8_unmasked: 550; CHECK: # %bb.0: 551; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma 552; CHECK-NEXT: vssubu.vx v8, v8, a0 553; CHECK-NEXT: ret 554 %elt.head = insertelement <vscale x 64 x i8> poison, i8 %b, i32 0 555 %vb = shufflevector <vscale x 64 x i8> %elt.head, <vscale x 64 x i8> poison, <vscale x 64 x i32> zeroinitializer 556 %v = call <vscale x 64 x i8> @llvm.vp.usub.sat.nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %vb, <vscale x 64 x i1> splat (i1 true), i32 %evl) 557 ret <vscale x 64 x i8> %v 558} 559 560define <vscale x 64 x i8> @vssubu_vi_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i1> %m, i32 zeroext %evl) { 561; CHECK-LABEL: vssubu_vi_nxv64i8: 562; CHECK: # %bb.0: 563; CHECK-NEXT: li a1, -1 564; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma 565; CHECK-NEXT: vssubu.vx v8, v8, a1, v0.t 566; CHECK-NEXT: ret 567 %v = call <vscale x 64 x i8> @llvm.vp.usub.sat.nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> splat (i8 -1), <vscale x 64 x i1> %m, i32 %evl) 568 ret <vscale x 64 x i8> %v 569} 570 571define <vscale x 64 x i8> @vssubu_vi_nxv64i8_unmasked(<vscale x 64 x i8> %va, i32 zeroext %evl) { 572; CHECK-LABEL: vssubu_vi_nxv64i8_unmasked: 573; CHECK: # %bb.0: 574; CHECK-NEXT: li a1, -1 575; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma 576; CHECK-NEXT: vssubu.vx v8, v8, a1 577; CHECK-NEXT: ret 578 %v = call <vscale x 64 x i8> @llvm.vp.usub.sat.nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> splat (i8 -1), <vscale x 64 x i1> splat (i1 true), i32 %evl) 579 ret <vscale x 64 x i8> %v 580} 581 582; Test that split-legalization works when the mask itself needs splitting. 583 584declare <vscale x 128 x i8> @llvm.vp.usub.sat.nxv128i8(<vscale x 128 x i8>, <vscale x 128 x i8>, <vscale x 128 x i1>, i32) 585 586define <vscale x 128 x i8> @vssubu_vi_nxv128i8(<vscale x 128 x i8> %va, <vscale x 128 x i1> %m, i32 zeroext %evl) { 587; CHECK-LABEL: vssubu_vi_nxv128i8: 588; CHECK: # %bb.0: 589; CHECK-NEXT: vsetvli a2, zero, e8, m8, ta, ma 590; CHECK-NEXT: vmv1r.v v24, v0 591; CHECK-NEXT: vlm.v v0, (a0) 592; CHECK-NEXT: csrr a0, vlenb 593; CHECK-NEXT: slli a0, a0, 3 594; CHECK-NEXT: sub a2, a1, a0 595; CHECK-NEXT: sltu a3, a1, a2 596; CHECK-NEXT: addi a3, a3, -1 597; CHECK-NEXT: and a3, a3, a2 598; CHECK-NEXT: li a2, -1 599; CHECK-NEXT: vsetvli zero, a3, e8, m8, ta, ma 600; CHECK-NEXT: vssubu.vx v16, v16, a2, v0.t 601; CHECK-NEXT: bltu a1, a0, .LBB50_2 602; CHECK-NEXT: # %bb.1: 603; CHECK-NEXT: mv a1, a0 604; CHECK-NEXT: .LBB50_2: 605; CHECK-NEXT: vmv1r.v v0, v24 606; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma 607; CHECK-NEXT: vssubu.vx v8, v8, a2, v0.t 608; CHECK-NEXT: ret 609 %v = call <vscale x 128 x i8> @llvm.vp.usub.sat.nxv128i8(<vscale x 128 x i8> %va, <vscale x 128 x i8> splat (i8 -1), <vscale x 128 x i1> %m, i32 %evl) 610 ret <vscale x 128 x i8> %v 611} 612 613define <vscale x 128 x i8> @vssubu_vi_nxv128i8_unmasked(<vscale x 128 x i8> %va, i32 zeroext %evl) { 614; CHECK-LABEL: vssubu_vi_nxv128i8_unmasked: 615; CHECK: # %bb.0: 616; CHECK-NEXT: csrr a1, vlenb 617; CHECK-NEXT: slli a1, a1, 3 618; CHECK-NEXT: sub a2, a0, a1 619; CHECK-NEXT: sltu a3, a0, a2 620; CHECK-NEXT: addi a3, a3, -1 621; CHECK-NEXT: and a3, a3, a2 622; CHECK-NEXT: li a2, -1 623; CHECK-NEXT: vsetvli zero, a3, e8, m8, ta, ma 624; CHECK-NEXT: vssubu.vx v16, v16, a2 625; CHECK-NEXT: bltu a0, a1, .LBB51_2 626; CHECK-NEXT: # %bb.1: 627; CHECK-NEXT: mv a0, a1 628; CHECK-NEXT: .LBB51_2: 629; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma 630; CHECK-NEXT: vssubu.vx v8, v8, a2 631; CHECK-NEXT: ret 632 %v = call <vscale x 128 x i8> @llvm.vp.usub.sat.nxv128i8(<vscale x 128 x i8> %va, <vscale x 128 x i8> splat (i8 -1), <vscale x 128 x i1> splat (i1 true), i32 %evl) 633 ret <vscale x 128 x i8> %v 634} 635 636declare <vscale x 1 x i16> @llvm.vp.usub.sat.nxv1i16(<vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i1>, i32) 637 638define <vscale x 1 x i16> @vssubu_vv_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %b, <vscale x 1 x i1> %m, i32 zeroext %evl) { 639; CHECK-LABEL: vssubu_vv_nxv1i16: 640; CHECK: # %bb.0: 641; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma 642; CHECK-NEXT: vssubu.vv v8, v8, v9, v0.t 643; CHECK-NEXT: ret 644 %v = call <vscale x 1 x i16> @llvm.vp.usub.sat.nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %b, <vscale x 1 x i1> %m, i32 %evl) 645 ret <vscale x 1 x i16> %v 646} 647 648define <vscale x 1 x i16> @vssubu_vv_nxv1i16_unmasked(<vscale x 1 x i16> %va, <vscale x 1 x i16> %b, i32 zeroext %evl) { 649; CHECK-LABEL: vssubu_vv_nxv1i16_unmasked: 650; CHECK: # %bb.0: 651; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma 652; CHECK-NEXT: vssubu.vv v8, v8, v9 653; CHECK-NEXT: ret 654 %v = call <vscale x 1 x i16> @llvm.vp.usub.sat.nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %b, <vscale x 1 x i1> splat (i1 true), i32 %evl) 655 ret <vscale x 1 x i16> %v 656} 657 658define <vscale x 1 x i16> @vssubu_vx_nxv1i16(<vscale x 1 x i16> %va, i16 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) { 659; CHECK-LABEL: vssubu_vx_nxv1i16: 660; CHECK: # %bb.0: 661; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma 662; CHECK-NEXT: vssubu.vx v8, v8, a0, v0.t 663; CHECK-NEXT: ret 664 %elt.head = insertelement <vscale x 1 x i16> poison, i16 %b, i32 0 665 %vb = shufflevector <vscale x 1 x i16> %elt.head, <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer 666 %v = call <vscale x 1 x i16> @llvm.vp.usub.sat.nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %vb, <vscale x 1 x i1> %m, i32 %evl) 667 ret <vscale x 1 x i16> %v 668} 669 670define <vscale x 1 x i16> @vssubu_vx_nxv1i16_unmasked(<vscale x 1 x i16> %va, i16 %b, i32 zeroext %evl) { 671; CHECK-LABEL: vssubu_vx_nxv1i16_unmasked: 672; CHECK: # %bb.0: 673; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma 674; CHECK-NEXT: vssubu.vx v8, v8, a0 675; CHECK-NEXT: ret 676 %elt.head = insertelement <vscale x 1 x i16> poison, i16 %b, i32 0 677 %vb = shufflevector <vscale x 1 x i16> %elt.head, <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer 678 %v = call <vscale x 1 x i16> @llvm.vp.usub.sat.nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %vb, <vscale x 1 x i1> splat (i1 true), i32 %evl) 679 ret <vscale x 1 x i16> %v 680} 681 682define <vscale x 1 x i16> @vssubu_vi_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) { 683; CHECK-LABEL: vssubu_vi_nxv1i16: 684; CHECK: # %bb.0: 685; CHECK-NEXT: li a1, -1 686; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma 687; CHECK-NEXT: vssubu.vx v8, v8, a1, v0.t 688; CHECK-NEXT: ret 689 %v = call <vscale x 1 x i16> @llvm.vp.usub.sat.nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> splat (i16 -1), <vscale x 1 x i1> %m, i32 %evl) 690 ret <vscale x 1 x i16> %v 691} 692 693define <vscale x 1 x i16> @vssubu_vi_nxv1i16_unmasked(<vscale x 1 x i16> %va, i32 zeroext %evl) { 694; CHECK-LABEL: vssubu_vi_nxv1i16_unmasked: 695; CHECK: # %bb.0: 696; CHECK-NEXT: li a1, -1 697; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma 698; CHECK-NEXT: vssubu.vx v8, v8, a1 699; CHECK-NEXT: ret 700 %v = call <vscale x 1 x i16> @llvm.vp.usub.sat.nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> splat (i16 -1), <vscale x 1 x i1> splat (i1 true), i32 %evl) 701 ret <vscale x 1 x i16> %v 702} 703 704declare <vscale x 2 x i16> @llvm.vp.usub.sat.nxv2i16(<vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i1>, i32) 705 706define <vscale x 2 x i16> @vssubu_vv_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %b, <vscale x 2 x i1> %m, i32 zeroext %evl) { 707; CHECK-LABEL: vssubu_vv_nxv2i16: 708; CHECK: # %bb.0: 709; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma 710; CHECK-NEXT: vssubu.vv v8, v8, v9, v0.t 711; CHECK-NEXT: ret 712 %v = call <vscale x 2 x i16> @llvm.vp.usub.sat.nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %b, <vscale x 2 x i1> %m, i32 %evl) 713 ret <vscale x 2 x i16> %v 714} 715 716define <vscale x 2 x i16> @vssubu_vv_nxv2i16_unmasked(<vscale x 2 x i16> %va, <vscale x 2 x i16> %b, i32 zeroext %evl) { 717; CHECK-LABEL: vssubu_vv_nxv2i16_unmasked: 718; CHECK: # %bb.0: 719; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma 720; CHECK-NEXT: vssubu.vv v8, v8, v9 721; CHECK-NEXT: ret 722 %v = call <vscale x 2 x i16> @llvm.vp.usub.sat.nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %b, <vscale x 2 x i1> splat (i1 true), i32 %evl) 723 ret <vscale x 2 x i16> %v 724} 725 726define <vscale x 2 x i16> @vssubu_vx_nxv2i16(<vscale x 2 x i16> %va, i16 %b, <vscale x 2 x i1> %m, i32 zeroext %evl) { 727; CHECK-LABEL: vssubu_vx_nxv2i16: 728; CHECK: # %bb.0: 729; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma 730; CHECK-NEXT: vssubu.vx v8, v8, a0, v0.t 731; CHECK-NEXT: ret 732 %elt.head = insertelement <vscale x 2 x i16> poison, i16 %b, i32 0 733 %vb = shufflevector <vscale x 2 x i16> %elt.head, <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer 734 %v = call <vscale x 2 x i16> @llvm.vp.usub.sat.nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %vb, <vscale x 2 x i1> %m, i32 %evl) 735 ret <vscale x 2 x i16> %v 736} 737 738define <vscale x 2 x i16> @vssubu_vx_nxv2i16_unmasked(<vscale x 2 x i16> %va, i16 %b, i32 zeroext %evl) { 739; CHECK-LABEL: vssubu_vx_nxv2i16_unmasked: 740; CHECK: # %bb.0: 741; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma 742; CHECK-NEXT: vssubu.vx v8, v8, a0 743; CHECK-NEXT: ret 744 %elt.head = insertelement <vscale x 2 x i16> poison, i16 %b, i32 0 745 %vb = shufflevector <vscale x 2 x i16> %elt.head, <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer 746 %v = call <vscale x 2 x i16> @llvm.vp.usub.sat.nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %vb, <vscale x 2 x i1> splat (i1 true), i32 %evl) 747 ret <vscale x 2 x i16> %v 748} 749 750define <vscale x 2 x i16> @vssubu_vi_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) { 751; CHECK-LABEL: vssubu_vi_nxv2i16: 752; CHECK: # %bb.0: 753; CHECK-NEXT: li a1, -1 754; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma 755; CHECK-NEXT: vssubu.vx v8, v8, a1, v0.t 756; CHECK-NEXT: ret 757 %v = call <vscale x 2 x i16> @llvm.vp.usub.sat.nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> splat (i16 -1), <vscale x 2 x i1> %m, i32 %evl) 758 ret <vscale x 2 x i16> %v 759} 760 761define <vscale x 2 x i16> @vssubu_vi_nxv2i16_unmasked(<vscale x 2 x i16> %va, i32 zeroext %evl) { 762; CHECK-LABEL: vssubu_vi_nxv2i16_unmasked: 763; CHECK: # %bb.0: 764; CHECK-NEXT: li a1, -1 765; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma 766; CHECK-NEXT: vssubu.vx v8, v8, a1 767; CHECK-NEXT: ret 768 %v = call <vscale x 2 x i16> @llvm.vp.usub.sat.nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> splat (i16 -1), <vscale x 2 x i1> splat (i1 true), i32 %evl) 769 ret <vscale x 2 x i16> %v 770} 771 772declare <vscale x 4 x i16> @llvm.vp.usub.sat.nxv4i16(<vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i1>, i32) 773 774define <vscale x 4 x i16> @vssubu_vv_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %b, <vscale x 4 x i1> %m, i32 zeroext %evl) { 775; CHECK-LABEL: vssubu_vv_nxv4i16: 776; CHECK: # %bb.0: 777; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma 778; CHECK-NEXT: vssubu.vv v8, v8, v9, v0.t 779; CHECK-NEXT: ret 780 %v = call <vscale x 4 x i16> @llvm.vp.usub.sat.nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %b, <vscale x 4 x i1> %m, i32 %evl) 781 ret <vscale x 4 x i16> %v 782} 783 784define <vscale x 4 x i16> @vssubu_vv_nxv4i16_unmasked(<vscale x 4 x i16> %va, <vscale x 4 x i16> %b, i32 zeroext %evl) { 785; CHECK-LABEL: vssubu_vv_nxv4i16_unmasked: 786; CHECK: # %bb.0: 787; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma 788; CHECK-NEXT: vssubu.vv v8, v8, v9 789; CHECK-NEXT: ret 790 %v = call <vscale x 4 x i16> @llvm.vp.usub.sat.nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %b, <vscale x 4 x i1> splat (i1 true), i32 %evl) 791 ret <vscale x 4 x i16> %v 792} 793 794define <vscale x 4 x i16> @vssubu_vx_nxv4i16(<vscale x 4 x i16> %va, i16 %b, <vscale x 4 x i1> %m, i32 zeroext %evl) { 795; CHECK-LABEL: vssubu_vx_nxv4i16: 796; CHECK: # %bb.0: 797; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma 798; CHECK-NEXT: vssubu.vx v8, v8, a0, v0.t 799; CHECK-NEXT: ret 800 %elt.head = insertelement <vscale x 4 x i16> poison, i16 %b, i32 0 801 %vb = shufflevector <vscale x 4 x i16> %elt.head, <vscale x 4 x i16> poison, <vscale x 4 x i32> zeroinitializer 802 %v = call <vscale x 4 x i16> @llvm.vp.usub.sat.nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %vb, <vscale x 4 x i1> %m, i32 %evl) 803 ret <vscale x 4 x i16> %v 804} 805 806define <vscale x 4 x i16> @vssubu_vx_nxv4i16_unmasked(<vscale x 4 x i16> %va, i16 %b, i32 zeroext %evl) { 807; CHECK-LABEL: vssubu_vx_nxv4i16_unmasked: 808; CHECK: # %bb.0: 809; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma 810; CHECK-NEXT: vssubu.vx v8, v8, a0 811; CHECK-NEXT: ret 812 %elt.head = insertelement <vscale x 4 x i16> poison, i16 %b, i32 0 813 %vb = shufflevector <vscale x 4 x i16> %elt.head, <vscale x 4 x i16> poison, <vscale x 4 x i32> zeroinitializer 814 %v = call <vscale x 4 x i16> @llvm.vp.usub.sat.nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %vb, <vscale x 4 x i1> splat (i1 true), i32 %evl) 815 ret <vscale x 4 x i16> %v 816} 817 818define <vscale x 4 x i16> @vssubu_vi_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) { 819; CHECK-LABEL: vssubu_vi_nxv4i16: 820; CHECK: # %bb.0: 821; CHECK-NEXT: li a1, -1 822; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma 823; CHECK-NEXT: vssubu.vx v8, v8, a1, v0.t 824; CHECK-NEXT: ret 825 %v = call <vscale x 4 x i16> @llvm.vp.usub.sat.nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> splat (i16 -1), <vscale x 4 x i1> %m, i32 %evl) 826 ret <vscale x 4 x i16> %v 827} 828 829define <vscale x 4 x i16> @vssubu_vi_nxv4i16_unmasked(<vscale x 4 x i16> %va, i32 zeroext %evl) { 830; CHECK-LABEL: vssubu_vi_nxv4i16_unmasked: 831; CHECK: # %bb.0: 832; CHECK-NEXT: li a1, -1 833; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma 834; CHECK-NEXT: vssubu.vx v8, v8, a1 835; CHECK-NEXT: ret 836 %v = call <vscale x 4 x i16> @llvm.vp.usub.sat.nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> splat (i16 -1), <vscale x 4 x i1> splat (i1 true), i32 %evl) 837 ret <vscale x 4 x i16> %v 838} 839 840declare <vscale x 8 x i16> @llvm.vp.usub.sat.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i1>, i32) 841 842define <vscale x 8 x i16> @vssubu_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %b, <vscale x 8 x i1> %m, i32 zeroext %evl) { 843; CHECK-LABEL: vssubu_vv_nxv8i16: 844; CHECK: # %bb.0: 845; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma 846; CHECK-NEXT: vssubu.vv v8, v8, v10, v0.t 847; CHECK-NEXT: ret 848 %v = call <vscale x 8 x i16> @llvm.vp.usub.sat.nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %b, <vscale x 8 x i1> %m, i32 %evl) 849 ret <vscale x 8 x i16> %v 850} 851 852define <vscale x 8 x i16> @vssubu_vv_nxv8i16_unmasked(<vscale x 8 x i16> %va, <vscale x 8 x i16> %b, i32 zeroext %evl) { 853; CHECK-LABEL: vssubu_vv_nxv8i16_unmasked: 854; CHECK: # %bb.0: 855; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma 856; CHECK-NEXT: vssubu.vv v8, v8, v10 857; CHECK-NEXT: ret 858 %v = call <vscale x 8 x i16> @llvm.vp.usub.sat.nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %b, <vscale x 8 x i1> splat (i1 true), i32 %evl) 859 ret <vscale x 8 x i16> %v 860} 861 862define <vscale x 8 x i16> @vssubu_vx_nxv8i16(<vscale x 8 x i16> %va, i16 %b, <vscale x 8 x i1> %m, i32 zeroext %evl) { 863; CHECK-LABEL: vssubu_vx_nxv8i16: 864; CHECK: # %bb.0: 865; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma 866; CHECK-NEXT: vssubu.vx v8, v8, a0, v0.t 867; CHECK-NEXT: ret 868 %elt.head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0 869 %vb = shufflevector <vscale x 8 x i16> %elt.head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer 870 %v = call <vscale x 8 x i16> @llvm.vp.usub.sat.nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb, <vscale x 8 x i1> %m, i32 %evl) 871 ret <vscale x 8 x i16> %v 872} 873 874define <vscale x 8 x i16> @vssubu_vx_nxv8i16_unmasked(<vscale x 8 x i16> %va, i16 %b, i32 zeroext %evl) { 875; CHECK-LABEL: vssubu_vx_nxv8i16_unmasked: 876; CHECK: # %bb.0: 877; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma 878; CHECK-NEXT: vssubu.vx v8, v8, a0 879; CHECK-NEXT: ret 880 %elt.head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0 881 %vb = shufflevector <vscale x 8 x i16> %elt.head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer 882 %v = call <vscale x 8 x i16> @llvm.vp.usub.sat.nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb, <vscale x 8 x i1> splat (i1 true), i32 %evl) 883 ret <vscale x 8 x i16> %v 884} 885 886define <vscale x 8 x i16> @vssubu_vi_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) { 887; CHECK-LABEL: vssubu_vi_nxv8i16: 888; CHECK: # %bb.0: 889; CHECK-NEXT: li a1, -1 890; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma 891; CHECK-NEXT: vssubu.vx v8, v8, a1, v0.t 892; CHECK-NEXT: ret 893 %v = call <vscale x 8 x i16> @llvm.vp.usub.sat.nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> splat (i16 -1), <vscale x 8 x i1> %m, i32 %evl) 894 ret <vscale x 8 x i16> %v 895} 896 897define <vscale x 8 x i16> @vssubu_vi_nxv8i16_unmasked(<vscale x 8 x i16> %va, i32 zeroext %evl) { 898; CHECK-LABEL: vssubu_vi_nxv8i16_unmasked: 899; CHECK: # %bb.0: 900; CHECK-NEXT: li a1, -1 901; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma 902; CHECK-NEXT: vssubu.vx v8, v8, a1 903; CHECK-NEXT: ret 904 %v = call <vscale x 8 x i16> @llvm.vp.usub.sat.nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> splat (i16 -1), <vscale x 8 x i1> splat (i1 true), i32 %evl) 905 ret <vscale x 8 x i16> %v 906} 907 908declare <vscale x 16 x i16> @llvm.vp.usub.sat.nxv16i16(<vscale x 16 x i16>, <vscale x 16 x i16>, <vscale x 16 x i1>, i32) 909 910define <vscale x 16 x i16> @vssubu_vv_nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %b, <vscale x 16 x i1> %m, i32 zeroext %evl) { 911; CHECK-LABEL: vssubu_vv_nxv16i16: 912; CHECK: # %bb.0: 913; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma 914; CHECK-NEXT: vssubu.vv v8, v8, v12, v0.t 915; CHECK-NEXT: ret 916 %v = call <vscale x 16 x i16> @llvm.vp.usub.sat.nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %b, <vscale x 16 x i1> %m, i32 %evl) 917 ret <vscale x 16 x i16> %v 918} 919 920define <vscale x 16 x i16> @vssubu_vv_nxv16i16_unmasked(<vscale x 16 x i16> %va, <vscale x 16 x i16> %b, i32 zeroext %evl) { 921; CHECK-LABEL: vssubu_vv_nxv16i16_unmasked: 922; CHECK: # %bb.0: 923; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma 924; CHECK-NEXT: vssubu.vv v8, v8, v12 925; CHECK-NEXT: ret 926 %v = call <vscale x 16 x i16> @llvm.vp.usub.sat.nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %b, <vscale x 16 x i1> splat (i1 true), i32 %evl) 927 ret <vscale x 16 x i16> %v 928} 929 930define <vscale x 16 x i16> @vssubu_vx_nxv16i16(<vscale x 16 x i16> %va, i16 %b, <vscale x 16 x i1> %m, i32 zeroext %evl) { 931; CHECK-LABEL: vssubu_vx_nxv16i16: 932; CHECK: # %bb.0: 933; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma 934; CHECK-NEXT: vssubu.vx v8, v8, a0, v0.t 935; CHECK-NEXT: ret 936 %elt.head = insertelement <vscale x 16 x i16> poison, i16 %b, i32 0 937 %vb = shufflevector <vscale x 16 x i16> %elt.head, <vscale x 16 x i16> poison, <vscale x 16 x i32> zeroinitializer 938 %v = call <vscale x 16 x i16> @llvm.vp.usub.sat.nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %vb, <vscale x 16 x i1> %m, i32 %evl) 939 ret <vscale x 16 x i16> %v 940} 941 942define <vscale x 16 x i16> @vssubu_vx_nxv16i16_unmasked(<vscale x 16 x i16> %va, i16 %b, i32 zeroext %evl) { 943; CHECK-LABEL: vssubu_vx_nxv16i16_unmasked: 944; CHECK: # %bb.0: 945; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma 946; CHECK-NEXT: vssubu.vx v8, v8, a0 947; CHECK-NEXT: ret 948 %elt.head = insertelement <vscale x 16 x i16> poison, i16 %b, i32 0 949 %vb = shufflevector <vscale x 16 x i16> %elt.head, <vscale x 16 x i16> poison, <vscale x 16 x i32> zeroinitializer 950 %v = call <vscale x 16 x i16> @llvm.vp.usub.sat.nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %vb, <vscale x 16 x i1> splat (i1 true), i32 %evl) 951 ret <vscale x 16 x i16> %v 952} 953 954define <vscale x 16 x i16> @vssubu_vi_nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) { 955; CHECK-LABEL: vssubu_vi_nxv16i16: 956; CHECK: # %bb.0: 957; CHECK-NEXT: li a1, -1 958; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma 959; CHECK-NEXT: vssubu.vx v8, v8, a1, v0.t 960; CHECK-NEXT: ret 961 %v = call <vscale x 16 x i16> @llvm.vp.usub.sat.nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> splat (i16 -1), <vscale x 16 x i1> %m, i32 %evl) 962 ret <vscale x 16 x i16> %v 963} 964 965define <vscale x 16 x i16> @vssubu_vi_nxv16i16_unmasked(<vscale x 16 x i16> %va, i32 zeroext %evl) { 966; CHECK-LABEL: vssubu_vi_nxv16i16_unmasked: 967; CHECK: # %bb.0: 968; CHECK-NEXT: li a1, -1 969; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma 970; CHECK-NEXT: vssubu.vx v8, v8, a1 971; CHECK-NEXT: ret 972 %v = call <vscale x 16 x i16> @llvm.vp.usub.sat.nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> splat (i16 -1), <vscale x 16 x i1> splat (i1 true), i32 %evl) 973 ret <vscale x 16 x i16> %v 974} 975 976declare <vscale x 32 x i16> @llvm.vp.usub.sat.nxv32i16(<vscale x 32 x i16>, <vscale x 32 x i16>, <vscale x 32 x i1>, i32) 977 978define <vscale x 32 x i16> @vssubu_vv_nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %b, <vscale x 32 x i1> %m, i32 zeroext %evl) { 979; CHECK-LABEL: vssubu_vv_nxv32i16: 980; CHECK: # %bb.0: 981; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma 982; CHECK-NEXT: vssubu.vv v8, v8, v16, v0.t 983; CHECK-NEXT: ret 984 %v = call <vscale x 32 x i16> @llvm.vp.usub.sat.nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %b, <vscale x 32 x i1> %m, i32 %evl) 985 ret <vscale x 32 x i16> %v 986} 987 988define <vscale x 32 x i16> @vssubu_vv_nxv32i16_unmasked(<vscale x 32 x i16> %va, <vscale x 32 x i16> %b, i32 zeroext %evl) { 989; CHECK-LABEL: vssubu_vv_nxv32i16_unmasked: 990; CHECK: # %bb.0: 991; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma 992; CHECK-NEXT: vssubu.vv v8, v8, v16 993; CHECK-NEXT: ret 994 %v = call <vscale x 32 x i16> @llvm.vp.usub.sat.nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %b, <vscale x 32 x i1> splat (i1 true), i32 %evl) 995 ret <vscale x 32 x i16> %v 996} 997 998define <vscale x 32 x i16> @vssubu_vx_nxv32i16(<vscale x 32 x i16> %va, i16 %b, <vscale x 32 x i1> %m, i32 zeroext %evl) { 999; CHECK-LABEL: vssubu_vx_nxv32i16: 1000; CHECK: # %bb.0: 1001; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma 1002; CHECK-NEXT: vssubu.vx v8, v8, a0, v0.t 1003; CHECK-NEXT: ret 1004 %elt.head = insertelement <vscale x 32 x i16> poison, i16 %b, i32 0 1005 %vb = shufflevector <vscale x 32 x i16> %elt.head, <vscale x 32 x i16> poison, <vscale x 32 x i32> zeroinitializer 1006 %v = call <vscale x 32 x i16> @llvm.vp.usub.sat.nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %vb, <vscale x 32 x i1> %m, i32 %evl) 1007 ret <vscale x 32 x i16> %v 1008} 1009 1010define <vscale x 32 x i16> @vssubu_vx_nxv32i16_unmasked(<vscale x 32 x i16> %va, i16 %b, i32 zeroext %evl) { 1011; CHECK-LABEL: vssubu_vx_nxv32i16_unmasked: 1012; CHECK: # %bb.0: 1013; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma 1014; CHECK-NEXT: vssubu.vx v8, v8, a0 1015; CHECK-NEXT: ret 1016 %elt.head = insertelement <vscale x 32 x i16> poison, i16 %b, i32 0 1017 %vb = shufflevector <vscale x 32 x i16> %elt.head, <vscale x 32 x i16> poison, <vscale x 32 x i32> zeroinitializer 1018 %v = call <vscale x 32 x i16> @llvm.vp.usub.sat.nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %vb, <vscale x 32 x i1> splat (i1 true), i32 %evl) 1019 ret <vscale x 32 x i16> %v 1020} 1021 1022define <vscale x 32 x i16> @vssubu_vi_nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) { 1023; CHECK-LABEL: vssubu_vi_nxv32i16: 1024; CHECK: # %bb.0: 1025; CHECK-NEXT: li a1, -1 1026; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma 1027; CHECK-NEXT: vssubu.vx v8, v8, a1, v0.t 1028; CHECK-NEXT: ret 1029 %v = call <vscale x 32 x i16> @llvm.vp.usub.sat.nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> splat (i16 -1), <vscale x 32 x i1> %m, i32 %evl) 1030 ret <vscale x 32 x i16> %v 1031} 1032 1033define <vscale x 32 x i16> @vssubu_vi_nxv32i16_unmasked(<vscale x 32 x i16> %va, i32 zeroext %evl) { 1034; CHECK-LABEL: vssubu_vi_nxv32i16_unmasked: 1035; CHECK: # %bb.0: 1036; CHECK-NEXT: li a1, -1 1037; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma 1038; CHECK-NEXT: vssubu.vx v8, v8, a1 1039; CHECK-NEXT: ret 1040 %v = call <vscale x 32 x i16> @llvm.vp.usub.sat.nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> splat (i16 -1), <vscale x 32 x i1> splat (i1 true), i32 %evl) 1041 ret <vscale x 32 x i16> %v 1042} 1043 1044declare <vscale x 1 x i32> @llvm.vp.usub.sat.nxv1i32(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i1>, i32) 1045 1046define <vscale x 1 x i32> @vssubu_vv_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %b, <vscale x 1 x i1> %m, i32 zeroext %evl) { 1047; CHECK-LABEL: vssubu_vv_nxv1i32: 1048; CHECK: # %bb.0: 1049; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma 1050; CHECK-NEXT: vssubu.vv v8, v8, v9, v0.t 1051; CHECK-NEXT: ret 1052 %v = call <vscale x 1 x i32> @llvm.vp.usub.sat.nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %b, <vscale x 1 x i1> %m, i32 %evl) 1053 ret <vscale x 1 x i32> %v 1054} 1055 1056define <vscale x 1 x i32> @vssubu_vv_nxv1i32_unmasked(<vscale x 1 x i32> %va, <vscale x 1 x i32> %b, i32 zeroext %evl) { 1057; CHECK-LABEL: vssubu_vv_nxv1i32_unmasked: 1058; CHECK: # %bb.0: 1059; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma 1060; CHECK-NEXT: vssubu.vv v8, v8, v9 1061; CHECK-NEXT: ret 1062 %v = call <vscale x 1 x i32> @llvm.vp.usub.sat.nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %b, <vscale x 1 x i1> splat (i1 true), i32 %evl) 1063 ret <vscale x 1 x i32> %v 1064} 1065 1066define <vscale x 1 x i32> @vssubu_vx_nxv1i32(<vscale x 1 x i32> %va, i32 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) { 1067; CHECK-LABEL: vssubu_vx_nxv1i32: 1068; CHECK: # %bb.0: 1069; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma 1070; CHECK-NEXT: vssubu.vx v8, v8, a0, v0.t 1071; CHECK-NEXT: ret 1072 %elt.head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 0 1073 %vb = shufflevector <vscale x 1 x i32> %elt.head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer 1074 %v = call <vscale x 1 x i32> @llvm.vp.usub.sat.nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb, <vscale x 1 x i1> %m, i32 %evl) 1075 ret <vscale x 1 x i32> %v 1076} 1077 1078define <vscale x 1 x i32> @vssubu_vx_nxv1i32_unmasked(<vscale x 1 x i32> %va, i32 %b, i32 zeroext %evl) { 1079; CHECK-LABEL: vssubu_vx_nxv1i32_unmasked: 1080; CHECK: # %bb.0: 1081; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma 1082; CHECK-NEXT: vssubu.vx v8, v8, a0 1083; CHECK-NEXT: ret 1084 %elt.head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 0 1085 %vb = shufflevector <vscale x 1 x i32> %elt.head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer 1086 %v = call <vscale x 1 x i32> @llvm.vp.usub.sat.nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb, <vscale x 1 x i1> splat (i1 true), i32 %evl) 1087 ret <vscale x 1 x i32> %v 1088} 1089 1090define <vscale x 1 x i32> @vssubu_vi_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) { 1091; CHECK-LABEL: vssubu_vi_nxv1i32: 1092; CHECK: # %bb.0: 1093; CHECK-NEXT: li a1, -1 1094; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma 1095; CHECK-NEXT: vssubu.vx v8, v8, a1, v0.t 1096; CHECK-NEXT: ret 1097 %v = call <vscale x 1 x i32> @llvm.vp.usub.sat.nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> splat (i32 -1), <vscale x 1 x i1> %m, i32 %evl) 1098 ret <vscale x 1 x i32> %v 1099} 1100 1101define <vscale x 1 x i32> @vssubu_vi_nxv1i32_unmasked(<vscale x 1 x i32> %va, i32 zeroext %evl) { 1102; CHECK-LABEL: vssubu_vi_nxv1i32_unmasked: 1103; CHECK: # %bb.0: 1104; CHECK-NEXT: li a1, -1 1105; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma 1106; CHECK-NEXT: vssubu.vx v8, v8, a1 1107; CHECK-NEXT: ret 1108 %v = call <vscale x 1 x i32> @llvm.vp.usub.sat.nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> splat (i32 -1), <vscale x 1 x i1> splat (i1 true), i32 %evl) 1109 ret <vscale x 1 x i32> %v 1110} 1111 1112declare <vscale x 2 x i32> @llvm.vp.usub.sat.nxv2i32(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i1>, i32) 1113 1114define <vscale x 2 x i32> @vssubu_vv_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %b, <vscale x 2 x i1> %m, i32 zeroext %evl) { 1115; CHECK-LABEL: vssubu_vv_nxv2i32: 1116; CHECK: # %bb.0: 1117; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma 1118; CHECK-NEXT: vssubu.vv v8, v8, v9, v0.t 1119; CHECK-NEXT: ret 1120 %v = call <vscale x 2 x i32> @llvm.vp.usub.sat.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %b, <vscale x 2 x i1> %m, i32 %evl) 1121 ret <vscale x 2 x i32> %v 1122} 1123 1124define <vscale x 2 x i32> @vssubu_vv_nxv2i32_unmasked(<vscale x 2 x i32> %va, <vscale x 2 x i32> %b, i32 zeroext %evl) { 1125; CHECK-LABEL: vssubu_vv_nxv2i32_unmasked: 1126; CHECK: # %bb.0: 1127; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma 1128; CHECK-NEXT: vssubu.vv v8, v8, v9 1129; CHECK-NEXT: ret 1130 %v = call <vscale x 2 x i32> @llvm.vp.usub.sat.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %b, <vscale x 2 x i1> splat (i1 true), i32 %evl) 1131 ret <vscale x 2 x i32> %v 1132} 1133 1134define <vscale x 2 x i32> @vssubu_vx_nxv2i32(<vscale x 2 x i32> %va, i32 %b, <vscale x 2 x i1> %m, i32 zeroext %evl) { 1135; CHECK-LABEL: vssubu_vx_nxv2i32: 1136; CHECK: # %bb.0: 1137; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma 1138; CHECK-NEXT: vssubu.vx v8, v8, a0, v0.t 1139; CHECK-NEXT: ret 1140 %elt.head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0 1141 %vb = shufflevector <vscale x 2 x i32> %elt.head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer 1142 %v = call <vscale x 2 x i32> @llvm.vp.usub.sat.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb, <vscale x 2 x i1> %m, i32 %evl) 1143 ret <vscale x 2 x i32> %v 1144} 1145 1146define <vscale x 2 x i32> @vssubu_vx_nxv2i32_unmasked(<vscale x 2 x i32> %va, i32 %b, i32 zeroext %evl) { 1147; CHECK-LABEL: vssubu_vx_nxv2i32_unmasked: 1148; CHECK: # %bb.0: 1149; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma 1150; CHECK-NEXT: vssubu.vx v8, v8, a0 1151; CHECK-NEXT: ret 1152 %elt.head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0 1153 %vb = shufflevector <vscale x 2 x i32> %elt.head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer 1154 %v = call <vscale x 2 x i32> @llvm.vp.usub.sat.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb, <vscale x 2 x i1> splat (i1 true), i32 %evl) 1155 ret <vscale x 2 x i32> %v 1156} 1157 1158define <vscale x 2 x i32> @vssubu_vi_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) { 1159; CHECK-LABEL: vssubu_vi_nxv2i32: 1160; CHECK: # %bb.0: 1161; CHECK-NEXT: li a1, -1 1162; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma 1163; CHECK-NEXT: vssubu.vx v8, v8, a1, v0.t 1164; CHECK-NEXT: ret 1165 %v = call <vscale x 2 x i32> @llvm.vp.usub.sat.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> splat (i32 -1), <vscale x 2 x i1> %m, i32 %evl) 1166 ret <vscale x 2 x i32> %v 1167} 1168 1169define <vscale x 2 x i32> @vssubu_vi_nxv2i32_unmasked(<vscale x 2 x i32> %va, i32 zeroext %evl) { 1170; CHECK-LABEL: vssubu_vi_nxv2i32_unmasked: 1171; CHECK: # %bb.0: 1172; CHECK-NEXT: li a1, -1 1173; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma 1174; CHECK-NEXT: vssubu.vx v8, v8, a1 1175; CHECK-NEXT: ret 1176 %v = call <vscale x 2 x i32> @llvm.vp.usub.sat.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> splat (i32 -1), <vscale x 2 x i1> splat (i1 true), i32 %evl) 1177 ret <vscale x 2 x i32> %v 1178} 1179 1180declare <vscale x 4 x i32> @llvm.vp.usub.sat.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i1>, i32) 1181 1182define <vscale x 4 x i32> @vssubu_vv_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %b, <vscale x 4 x i1> %m, i32 zeroext %evl) { 1183; CHECK-LABEL: vssubu_vv_nxv4i32: 1184; CHECK: # %bb.0: 1185; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma 1186; CHECK-NEXT: vssubu.vv v8, v8, v10, v0.t 1187; CHECK-NEXT: ret 1188 %v = call <vscale x 4 x i32> @llvm.vp.usub.sat.nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %b, <vscale x 4 x i1> %m, i32 %evl) 1189 ret <vscale x 4 x i32> %v 1190} 1191 1192define <vscale x 4 x i32> @vssubu_vv_nxv4i32_unmasked(<vscale x 4 x i32> %va, <vscale x 4 x i32> %b, i32 zeroext %evl) { 1193; CHECK-LABEL: vssubu_vv_nxv4i32_unmasked: 1194; CHECK: # %bb.0: 1195; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma 1196; CHECK-NEXT: vssubu.vv v8, v8, v10 1197; CHECK-NEXT: ret 1198 %v = call <vscale x 4 x i32> @llvm.vp.usub.sat.nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %b, <vscale x 4 x i1> splat (i1 true), i32 %evl) 1199 ret <vscale x 4 x i32> %v 1200} 1201 1202define <vscale x 4 x i32> @vssubu_vx_nxv4i32(<vscale x 4 x i32> %va, i32 %b, <vscale x 4 x i1> %m, i32 zeroext %evl) { 1203; CHECK-LABEL: vssubu_vx_nxv4i32: 1204; CHECK: # %bb.0: 1205; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma 1206; CHECK-NEXT: vssubu.vx v8, v8, a0, v0.t 1207; CHECK-NEXT: ret 1208 %elt.head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0 1209 %vb = shufflevector <vscale x 4 x i32> %elt.head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer 1210 %v = call <vscale x 4 x i32> @llvm.vp.usub.sat.nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb, <vscale x 4 x i1> %m, i32 %evl) 1211 ret <vscale x 4 x i32> %v 1212} 1213 1214define <vscale x 4 x i32> @vssubu_vx_nxv4i32_unmasked(<vscale x 4 x i32> %va, i32 %b, i32 zeroext %evl) { 1215; CHECK-LABEL: vssubu_vx_nxv4i32_unmasked: 1216; CHECK: # %bb.0: 1217; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma 1218; CHECK-NEXT: vssubu.vx v8, v8, a0 1219; CHECK-NEXT: ret 1220 %elt.head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0 1221 %vb = shufflevector <vscale x 4 x i32> %elt.head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer 1222 %v = call <vscale x 4 x i32> @llvm.vp.usub.sat.nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb, <vscale x 4 x i1> splat (i1 true), i32 %evl) 1223 ret <vscale x 4 x i32> %v 1224} 1225 1226define <vscale x 4 x i32> @vssubu_vi_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) { 1227; CHECK-LABEL: vssubu_vi_nxv4i32: 1228; CHECK: # %bb.0: 1229; CHECK-NEXT: li a1, -1 1230; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma 1231; CHECK-NEXT: vssubu.vx v8, v8, a1, v0.t 1232; CHECK-NEXT: ret 1233 %v = call <vscale x 4 x i32> @llvm.vp.usub.sat.nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> splat (i32 -1), <vscale x 4 x i1> %m, i32 %evl) 1234 ret <vscale x 4 x i32> %v 1235} 1236 1237define <vscale x 4 x i32> @vssubu_vi_nxv4i32_unmasked(<vscale x 4 x i32> %va, i32 zeroext %evl) { 1238; CHECK-LABEL: vssubu_vi_nxv4i32_unmasked: 1239; CHECK: # %bb.0: 1240; CHECK-NEXT: li a1, -1 1241; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma 1242; CHECK-NEXT: vssubu.vx v8, v8, a1 1243; CHECK-NEXT: ret 1244 %v = call <vscale x 4 x i32> @llvm.vp.usub.sat.nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> splat (i32 -1), <vscale x 4 x i1> splat (i1 true), i32 %evl) 1245 ret <vscale x 4 x i32> %v 1246} 1247 1248declare <vscale x 8 x i32> @llvm.vp.usub.sat.nxv8i32(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i1>, i32) 1249 1250define <vscale x 8 x i32> @vssubu_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %b, <vscale x 8 x i1> %m, i32 zeroext %evl) { 1251; CHECK-LABEL: vssubu_vv_nxv8i32: 1252; CHECK: # %bb.0: 1253; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma 1254; CHECK-NEXT: vssubu.vv v8, v8, v12, v0.t 1255; CHECK-NEXT: ret 1256 %v = call <vscale x 8 x i32> @llvm.vp.usub.sat.nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %b, <vscale x 8 x i1> %m, i32 %evl) 1257 ret <vscale x 8 x i32> %v 1258} 1259 1260define <vscale x 8 x i32> @vssubu_vv_nxv8i32_unmasked(<vscale x 8 x i32> %va, <vscale x 8 x i32> %b, i32 zeroext %evl) { 1261; CHECK-LABEL: vssubu_vv_nxv8i32_unmasked: 1262; CHECK: # %bb.0: 1263; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma 1264; CHECK-NEXT: vssubu.vv v8, v8, v12 1265; CHECK-NEXT: ret 1266 %v = call <vscale x 8 x i32> @llvm.vp.usub.sat.nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %b, <vscale x 8 x i1> splat (i1 true), i32 %evl) 1267 ret <vscale x 8 x i32> %v 1268} 1269 1270define <vscale x 8 x i32> @vssubu_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %b, <vscale x 8 x i1> %m, i32 zeroext %evl) { 1271; CHECK-LABEL: vssubu_vx_nxv8i32: 1272; CHECK: # %bb.0: 1273; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma 1274; CHECK-NEXT: vssubu.vx v8, v8, a0, v0.t 1275; CHECK-NEXT: ret 1276 %elt.head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0 1277 %vb = shufflevector <vscale x 8 x i32> %elt.head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer 1278 %v = call <vscale x 8 x i32> @llvm.vp.usub.sat.nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, <vscale x 8 x i1> %m, i32 %evl) 1279 ret <vscale x 8 x i32> %v 1280} 1281 1282define <vscale x 8 x i32> @vssubu_vx_nxv8i32_unmasked(<vscale x 8 x i32> %va, i32 %b, i32 zeroext %evl) { 1283; CHECK-LABEL: vssubu_vx_nxv8i32_unmasked: 1284; CHECK: # %bb.0: 1285; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma 1286; CHECK-NEXT: vssubu.vx v8, v8, a0 1287; CHECK-NEXT: ret 1288 %elt.head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0 1289 %vb = shufflevector <vscale x 8 x i32> %elt.head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer 1290 %v = call <vscale x 8 x i32> @llvm.vp.usub.sat.nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, <vscale x 8 x i1> splat (i1 true), i32 %evl) 1291 ret <vscale x 8 x i32> %v 1292} 1293 1294define <vscale x 8 x i32> @vssubu_vi_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) { 1295; CHECK-LABEL: vssubu_vi_nxv8i32: 1296; CHECK: # %bb.0: 1297; CHECK-NEXT: li a1, -1 1298; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma 1299; CHECK-NEXT: vssubu.vx v8, v8, a1, v0.t 1300; CHECK-NEXT: ret 1301 %v = call <vscale x 8 x i32> @llvm.vp.usub.sat.nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> splat (i32 -1), <vscale x 8 x i1> %m, i32 %evl) 1302 ret <vscale x 8 x i32> %v 1303} 1304 1305define <vscale x 8 x i32> @vssubu_vi_nxv8i32_unmasked(<vscale x 8 x i32> %va, i32 zeroext %evl) { 1306; CHECK-LABEL: vssubu_vi_nxv8i32_unmasked: 1307; CHECK: # %bb.0: 1308; CHECK-NEXT: li a1, -1 1309; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma 1310; CHECK-NEXT: vssubu.vx v8, v8, a1 1311; CHECK-NEXT: ret 1312 %v = call <vscale x 8 x i32> @llvm.vp.usub.sat.nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> splat (i32 -1), <vscale x 8 x i1> splat (i1 true), i32 %evl) 1313 ret <vscale x 8 x i32> %v 1314} 1315 1316declare <vscale x 16 x i32> @llvm.vp.usub.sat.nxv16i32(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i1>, i32) 1317 1318define <vscale x 16 x i32> @vssubu_vv_nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %b, <vscale x 16 x i1> %m, i32 zeroext %evl) { 1319; CHECK-LABEL: vssubu_vv_nxv16i32: 1320; CHECK: # %bb.0: 1321; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma 1322; CHECK-NEXT: vssubu.vv v8, v8, v16, v0.t 1323; CHECK-NEXT: ret 1324 %v = call <vscale x 16 x i32> @llvm.vp.usub.sat.nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %b, <vscale x 16 x i1> %m, i32 %evl) 1325 ret <vscale x 16 x i32> %v 1326} 1327 1328define <vscale x 16 x i32> @vssubu_vv_nxv16i32_unmasked(<vscale x 16 x i32> %va, <vscale x 16 x i32> %b, i32 zeroext %evl) { 1329; CHECK-LABEL: vssubu_vv_nxv16i32_unmasked: 1330; CHECK: # %bb.0: 1331; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma 1332; CHECK-NEXT: vssubu.vv v8, v8, v16 1333; CHECK-NEXT: ret 1334 %v = call <vscale x 16 x i32> @llvm.vp.usub.sat.nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %b, <vscale x 16 x i1> splat (i1 true), i32 %evl) 1335 ret <vscale x 16 x i32> %v 1336} 1337 1338define <vscale x 16 x i32> @vssubu_vx_nxv16i32(<vscale x 16 x i32> %va, i32 %b, <vscale x 16 x i1> %m, i32 zeroext %evl) { 1339; CHECK-LABEL: vssubu_vx_nxv16i32: 1340; CHECK: # %bb.0: 1341; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma 1342; CHECK-NEXT: vssubu.vx v8, v8, a0, v0.t 1343; CHECK-NEXT: ret 1344 %elt.head = insertelement <vscale x 16 x i32> poison, i32 %b, i32 0 1345 %vb = shufflevector <vscale x 16 x i32> %elt.head, <vscale x 16 x i32> poison, <vscale x 16 x i32> zeroinitializer 1346 %v = call <vscale x 16 x i32> @llvm.vp.usub.sat.nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %vb, <vscale x 16 x i1> %m, i32 %evl) 1347 ret <vscale x 16 x i32> %v 1348} 1349 1350define <vscale x 16 x i32> @vssubu_vx_nxv16i32_unmasked(<vscale x 16 x i32> %va, i32 %b, i32 zeroext %evl) { 1351; CHECK-LABEL: vssubu_vx_nxv16i32_unmasked: 1352; CHECK: # %bb.0: 1353; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma 1354; CHECK-NEXT: vssubu.vx v8, v8, a0 1355; CHECK-NEXT: ret 1356 %elt.head = insertelement <vscale x 16 x i32> poison, i32 %b, i32 0 1357 %vb = shufflevector <vscale x 16 x i32> %elt.head, <vscale x 16 x i32> poison, <vscale x 16 x i32> zeroinitializer 1358 %v = call <vscale x 16 x i32> @llvm.vp.usub.sat.nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %vb, <vscale x 16 x i1> splat (i1 true), i32 %evl) 1359 ret <vscale x 16 x i32> %v 1360} 1361 1362define <vscale x 16 x i32> @vssubu_vi_nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) { 1363; CHECK-LABEL: vssubu_vi_nxv16i32: 1364; CHECK: # %bb.0: 1365; CHECK-NEXT: li a1, -1 1366; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma 1367; CHECK-NEXT: vssubu.vx v8, v8, a1, v0.t 1368; CHECK-NEXT: ret 1369 %v = call <vscale x 16 x i32> @llvm.vp.usub.sat.nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> splat (i32 -1), <vscale x 16 x i1> %m, i32 %evl) 1370 ret <vscale x 16 x i32> %v 1371} 1372 1373define <vscale x 16 x i32> @vssubu_vi_nxv16i32_unmasked(<vscale x 16 x i32> %va, i32 zeroext %evl) { 1374; CHECK-LABEL: vssubu_vi_nxv16i32_unmasked: 1375; CHECK: # %bb.0: 1376; CHECK-NEXT: li a1, -1 1377; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma 1378; CHECK-NEXT: vssubu.vx v8, v8, a1 1379; CHECK-NEXT: ret 1380 %v = call <vscale x 16 x i32> @llvm.vp.usub.sat.nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> splat (i32 -1), <vscale x 16 x i1> splat (i1 true), i32 %evl) 1381 ret <vscale x 16 x i32> %v 1382} 1383 1384; Test that split-legalization works then the mask needs manual splitting. 1385 1386declare <vscale x 32 x i32> @llvm.vp.usub.sat.nxv32i32(<vscale x 32 x i32>, <vscale x 32 x i32>, <vscale x 32 x i1>, i32) 1387 1388define <vscale x 32 x i32> @vssubu_vi_nxv32i32(<vscale x 32 x i32> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) { 1389; CHECK-LABEL: vssubu_vi_nxv32i32: 1390; CHECK: # %bb.0: 1391; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma 1392; CHECK-NEXT: vmv1r.v v24, v0 1393; CHECK-NEXT: csrr a1, vlenb 1394; CHECK-NEXT: srli a2, a1, 2 1395; CHECK-NEXT: slli a1, a1, 1 1396; CHECK-NEXT: vslidedown.vx v0, v0, a2 1397; CHECK-NEXT: sub a2, a0, a1 1398; CHECK-NEXT: sltu a3, a0, a2 1399; CHECK-NEXT: addi a3, a3, -1 1400; CHECK-NEXT: and a3, a3, a2 1401; CHECK-NEXT: li a2, -1 1402; CHECK-NEXT: vsetvli zero, a3, e32, m8, ta, ma 1403; CHECK-NEXT: vssubu.vx v16, v16, a2, v0.t 1404; CHECK-NEXT: bltu a0, a1, .LBB118_2 1405; CHECK-NEXT: # %bb.1: 1406; CHECK-NEXT: mv a0, a1 1407; CHECK-NEXT: .LBB118_2: 1408; CHECK-NEXT: vmv1r.v v0, v24 1409; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma 1410; CHECK-NEXT: vssubu.vx v8, v8, a2, v0.t 1411; CHECK-NEXT: ret 1412 %v = call <vscale x 32 x i32> @llvm.vp.usub.sat.nxv32i32(<vscale x 32 x i32> %va, <vscale x 32 x i32> splat (i32 -1), <vscale x 32 x i1> %m, i32 %evl) 1413 ret <vscale x 32 x i32> %v 1414} 1415 1416define <vscale x 32 x i32> @vssubu_vi_nxv32i32_unmasked(<vscale x 32 x i32> %va, i32 zeroext %evl) { 1417; CHECK-LABEL: vssubu_vi_nxv32i32_unmasked: 1418; CHECK: # %bb.0: 1419; CHECK-NEXT: csrr a1, vlenb 1420; CHECK-NEXT: slli a1, a1, 1 1421; CHECK-NEXT: sub a2, a0, a1 1422; CHECK-NEXT: sltu a3, a0, a2 1423; CHECK-NEXT: addi a3, a3, -1 1424; CHECK-NEXT: and a3, a3, a2 1425; CHECK-NEXT: li a2, -1 1426; CHECK-NEXT: vsetvli zero, a3, e32, m8, ta, ma 1427; CHECK-NEXT: vssubu.vx v16, v16, a2 1428; CHECK-NEXT: bltu a0, a1, .LBB119_2 1429; CHECK-NEXT: # %bb.1: 1430; CHECK-NEXT: mv a0, a1 1431; CHECK-NEXT: .LBB119_2: 1432; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma 1433; CHECK-NEXT: vssubu.vx v8, v8, a2 1434; CHECK-NEXT: ret 1435 %v = call <vscale x 32 x i32> @llvm.vp.usub.sat.nxv32i32(<vscale x 32 x i32> %va, <vscale x 32 x i32> splat (i32 -1), <vscale x 32 x i1> splat (i1 true), i32 %evl) 1436 ret <vscale x 32 x i32> %v 1437} 1438 1439declare <vscale x 1 x i64> @llvm.vp.usub.sat.nxv1i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i1>, i32) 1440 1441define <vscale x 1 x i64> @vssubu_vv_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %b, <vscale x 1 x i1> %m, i32 zeroext %evl) { 1442; CHECK-LABEL: vssubu_vv_nxv1i64: 1443; CHECK: # %bb.0: 1444; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma 1445; CHECK-NEXT: vssubu.vv v8, v8, v9, v0.t 1446; CHECK-NEXT: ret 1447 %v = call <vscale x 1 x i64> @llvm.vp.usub.sat.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %b, <vscale x 1 x i1> %m, i32 %evl) 1448 ret <vscale x 1 x i64> %v 1449} 1450 1451define <vscale x 1 x i64> @vssubu_vv_nxv1i64_unmasked(<vscale x 1 x i64> %va, <vscale x 1 x i64> %b, i32 zeroext %evl) { 1452; CHECK-LABEL: vssubu_vv_nxv1i64_unmasked: 1453; CHECK: # %bb.0: 1454; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma 1455; CHECK-NEXT: vssubu.vv v8, v8, v9 1456; CHECK-NEXT: ret 1457 %v = call <vscale x 1 x i64> @llvm.vp.usub.sat.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %b, <vscale x 1 x i1> splat (i1 true), i32 %evl) 1458 ret <vscale x 1 x i64> %v 1459} 1460 1461define <vscale x 1 x i64> @vssubu_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) { 1462; RV32-LABEL: vssubu_vx_nxv1i64: 1463; RV32: # %bb.0: 1464; RV32-NEXT: addi sp, sp, -16 1465; RV32-NEXT: .cfi_def_cfa_offset 16 1466; RV32-NEXT: sw a0, 8(sp) 1467; RV32-NEXT: sw a1, 12(sp) 1468; RV32-NEXT: addi a0, sp, 8 1469; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma 1470; RV32-NEXT: vlse64.v v9, (a0), zero 1471; RV32-NEXT: vssubu.vv v8, v8, v9, v0.t 1472; RV32-NEXT: addi sp, sp, 16 1473; RV32-NEXT: .cfi_def_cfa_offset 0 1474; RV32-NEXT: ret 1475; 1476; RV64-LABEL: vssubu_vx_nxv1i64: 1477; RV64: # %bb.0: 1478; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, ma 1479; RV64-NEXT: vssubu.vx v8, v8, a0, v0.t 1480; RV64-NEXT: ret 1481 %elt.head = insertelement <vscale x 1 x i64> poison, i64 %b, i32 0 1482 %vb = shufflevector <vscale x 1 x i64> %elt.head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer 1483 %v = call <vscale x 1 x i64> @llvm.vp.usub.sat.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb, <vscale x 1 x i1> %m, i32 %evl) 1484 ret <vscale x 1 x i64> %v 1485} 1486 1487define <vscale x 1 x i64> @vssubu_vx_nxv1i64_unmasked(<vscale x 1 x i64> %va, i64 %b, i32 zeroext %evl) { 1488; RV32-LABEL: vssubu_vx_nxv1i64_unmasked: 1489; RV32: # %bb.0: 1490; RV32-NEXT: addi sp, sp, -16 1491; RV32-NEXT: .cfi_def_cfa_offset 16 1492; RV32-NEXT: sw a0, 8(sp) 1493; RV32-NEXT: sw a1, 12(sp) 1494; RV32-NEXT: addi a0, sp, 8 1495; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma 1496; RV32-NEXT: vlse64.v v9, (a0), zero 1497; RV32-NEXT: vssubu.vv v8, v8, v9 1498; RV32-NEXT: addi sp, sp, 16 1499; RV32-NEXT: .cfi_def_cfa_offset 0 1500; RV32-NEXT: ret 1501; 1502; RV64-LABEL: vssubu_vx_nxv1i64_unmasked: 1503; RV64: # %bb.0: 1504; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, ma 1505; RV64-NEXT: vssubu.vx v8, v8, a0 1506; RV64-NEXT: ret 1507 %elt.head = insertelement <vscale x 1 x i64> poison, i64 %b, i32 0 1508 %vb = shufflevector <vscale x 1 x i64> %elt.head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer 1509 %v = call <vscale x 1 x i64> @llvm.vp.usub.sat.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb, <vscale x 1 x i1> splat (i1 true), i32 %evl) 1510 ret <vscale x 1 x i64> %v 1511} 1512 1513define <vscale x 1 x i64> @vssubu_vi_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) { 1514; CHECK-LABEL: vssubu_vi_nxv1i64: 1515; CHECK: # %bb.0: 1516; CHECK-NEXT: li a1, -1 1517; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma 1518; CHECK-NEXT: vssubu.vx v8, v8, a1, v0.t 1519; CHECK-NEXT: ret 1520 %v = call <vscale x 1 x i64> @llvm.vp.usub.sat.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> splat (i64 -1), <vscale x 1 x i1> %m, i32 %evl) 1521 ret <vscale x 1 x i64> %v 1522} 1523 1524define <vscale x 1 x i64> @vssubu_vi_nxv1i64_unmasked(<vscale x 1 x i64> %va, i32 zeroext %evl) { 1525; CHECK-LABEL: vssubu_vi_nxv1i64_unmasked: 1526; CHECK: # %bb.0: 1527; CHECK-NEXT: li a1, -1 1528; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma 1529; CHECK-NEXT: vssubu.vx v8, v8, a1 1530; CHECK-NEXT: ret 1531 %v = call <vscale x 1 x i64> @llvm.vp.usub.sat.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> splat (i64 -1), <vscale x 1 x i1> splat (i1 true), i32 %evl) 1532 ret <vscale x 1 x i64> %v 1533} 1534 1535declare <vscale x 2 x i64> @llvm.vp.usub.sat.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i1>, i32) 1536 1537define <vscale x 2 x i64> @vssubu_vv_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %b, <vscale x 2 x i1> %m, i32 zeroext %evl) { 1538; CHECK-LABEL: vssubu_vv_nxv2i64: 1539; CHECK: # %bb.0: 1540; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma 1541; CHECK-NEXT: vssubu.vv v8, v8, v10, v0.t 1542; CHECK-NEXT: ret 1543 %v = call <vscale x 2 x i64> @llvm.vp.usub.sat.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %b, <vscale x 2 x i1> %m, i32 %evl) 1544 ret <vscale x 2 x i64> %v 1545} 1546 1547define <vscale x 2 x i64> @vssubu_vv_nxv2i64_unmasked(<vscale x 2 x i64> %va, <vscale x 2 x i64> %b, i32 zeroext %evl) { 1548; CHECK-LABEL: vssubu_vv_nxv2i64_unmasked: 1549; CHECK: # %bb.0: 1550; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma 1551; CHECK-NEXT: vssubu.vv v8, v8, v10 1552; CHECK-NEXT: ret 1553 %v = call <vscale x 2 x i64> @llvm.vp.usub.sat.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %b, <vscale x 2 x i1> splat (i1 true), i32 %evl) 1554 ret <vscale x 2 x i64> %v 1555} 1556 1557define <vscale x 2 x i64> @vssubu_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b, <vscale x 2 x i1> %m, i32 zeroext %evl) { 1558; RV32-LABEL: vssubu_vx_nxv2i64: 1559; RV32: # %bb.0: 1560; RV32-NEXT: addi sp, sp, -16 1561; RV32-NEXT: .cfi_def_cfa_offset 16 1562; RV32-NEXT: sw a0, 8(sp) 1563; RV32-NEXT: sw a1, 12(sp) 1564; RV32-NEXT: addi a0, sp, 8 1565; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma 1566; RV32-NEXT: vlse64.v v10, (a0), zero 1567; RV32-NEXT: vssubu.vv v8, v8, v10, v0.t 1568; RV32-NEXT: addi sp, sp, 16 1569; RV32-NEXT: .cfi_def_cfa_offset 0 1570; RV32-NEXT: ret 1571; 1572; RV64-LABEL: vssubu_vx_nxv2i64: 1573; RV64: # %bb.0: 1574; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, ma 1575; RV64-NEXT: vssubu.vx v8, v8, a0, v0.t 1576; RV64-NEXT: ret 1577 %elt.head = insertelement <vscale x 2 x i64> poison, i64 %b, i32 0 1578 %vb = shufflevector <vscale x 2 x i64> %elt.head, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer 1579 %v = call <vscale x 2 x i64> @llvm.vp.usub.sat.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb, <vscale x 2 x i1> %m, i32 %evl) 1580 ret <vscale x 2 x i64> %v 1581} 1582 1583define <vscale x 2 x i64> @vssubu_vx_nxv2i64_unmasked(<vscale x 2 x i64> %va, i64 %b, i32 zeroext %evl) { 1584; RV32-LABEL: vssubu_vx_nxv2i64_unmasked: 1585; RV32: # %bb.0: 1586; RV32-NEXT: addi sp, sp, -16 1587; RV32-NEXT: .cfi_def_cfa_offset 16 1588; RV32-NEXT: sw a0, 8(sp) 1589; RV32-NEXT: sw a1, 12(sp) 1590; RV32-NEXT: addi a0, sp, 8 1591; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma 1592; RV32-NEXT: vlse64.v v10, (a0), zero 1593; RV32-NEXT: vssubu.vv v8, v8, v10 1594; RV32-NEXT: addi sp, sp, 16 1595; RV32-NEXT: .cfi_def_cfa_offset 0 1596; RV32-NEXT: ret 1597; 1598; RV64-LABEL: vssubu_vx_nxv2i64_unmasked: 1599; RV64: # %bb.0: 1600; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, ma 1601; RV64-NEXT: vssubu.vx v8, v8, a0 1602; RV64-NEXT: ret 1603 %elt.head = insertelement <vscale x 2 x i64> poison, i64 %b, i32 0 1604 %vb = shufflevector <vscale x 2 x i64> %elt.head, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer 1605 %v = call <vscale x 2 x i64> @llvm.vp.usub.sat.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb, <vscale x 2 x i1> splat (i1 true), i32 %evl) 1606 ret <vscale x 2 x i64> %v 1607} 1608 1609define <vscale x 2 x i64> @vssubu_vi_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) { 1610; CHECK-LABEL: vssubu_vi_nxv2i64: 1611; CHECK: # %bb.0: 1612; CHECK-NEXT: li a1, -1 1613; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma 1614; CHECK-NEXT: vssubu.vx v8, v8, a1, v0.t 1615; CHECK-NEXT: ret 1616 %v = call <vscale x 2 x i64> @llvm.vp.usub.sat.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> splat (i64 -1), <vscale x 2 x i1> %m, i32 %evl) 1617 ret <vscale x 2 x i64> %v 1618} 1619 1620define <vscale x 2 x i64> @vssubu_vi_nxv2i64_unmasked(<vscale x 2 x i64> %va, i32 zeroext %evl) { 1621; CHECK-LABEL: vssubu_vi_nxv2i64_unmasked: 1622; CHECK: # %bb.0: 1623; CHECK-NEXT: li a1, -1 1624; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma 1625; CHECK-NEXT: vssubu.vx v8, v8, a1 1626; CHECK-NEXT: ret 1627 %v = call <vscale x 2 x i64> @llvm.vp.usub.sat.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> splat (i64 -1), <vscale x 2 x i1> splat (i1 true), i32 %evl) 1628 ret <vscale x 2 x i64> %v 1629} 1630 1631declare <vscale x 4 x i64> @llvm.vp.usub.sat.nxv4i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i1>, i32) 1632 1633define <vscale x 4 x i64> @vssubu_vv_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %b, <vscale x 4 x i1> %m, i32 zeroext %evl) { 1634; CHECK-LABEL: vssubu_vv_nxv4i64: 1635; CHECK: # %bb.0: 1636; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma 1637; CHECK-NEXT: vssubu.vv v8, v8, v12, v0.t 1638; CHECK-NEXT: ret 1639 %v = call <vscale x 4 x i64> @llvm.vp.usub.sat.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %b, <vscale x 4 x i1> %m, i32 %evl) 1640 ret <vscale x 4 x i64> %v 1641} 1642 1643define <vscale x 4 x i64> @vssubu_vv_nxv4i64_unmasked(<vscale x 4 x i64> %va, <vscale x 4 x i64> %b, i32 zeroext %evl) { 1644; CHECK-LABEL: vssubu_vv_nxv4i64_unmasked: 1645; CHECK: # %bb.0: 1646; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma 1647; CHECK-NEXT: vssubu.vv v8, v8, v12 1648; CHECK-NEXT: ret 1649 %v = call <vscale x 4 x i64> @llvm.vp.usub.sat.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %b, <vscale x 4 x i1> splat (i1 true), i32 %evl) 1650 ret <vscale x 4 x i64> %v 1651} 1652 1653define <vscale x 4 x i64> @vssubu_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b, <vscale x 4 x i1> %m, i32 zeroext %evl) { 1654; RV32-LABEL: vssubu_vx_nxv4i64: 1655; RV32: # %bb.0: 1656; RV32-NEXT: addi sp, sp, -16 1657; RV32-NEXT: .cfi_def_cfa_offset 16 1658; RV32-NEXT: sw a0, 8(sp) 1659; RV32-NEXT: sw a1, 12(sp) 1660; RV32-NEXT: addi a0, sp, 8 1661; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma 1662; RV32-NEXT: vlse64.v v12, (a0), zero 1663; RV32-NEXT: vssubu.vv v8, v8, v12, v0.t 1664; RV32-NEXT: addi sp, sp, 16 1665; RV32-NEXT: .cfi_def_cfa_offset 0 1666; RV32-NEXT: ret 1667; 1668; RV64-LABEL: vssubu_vx_nxv4i64: 1669; RV64: # %bb.0: 1670; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, ma 1671; RV64-NEXT: vssubu.vx v8, v8, a0, v0.t 1672; RV64-NEXT: ret 1673 %elt.head = insertelement <vscale x 4 x i64> poison, i64 %b, i32 0 1674 %vb = shufflevector <vscale x 4 x i64> %elt.head, <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer 1675 %v = call <vscale x 4 x i64> @llvm.vp.usub.sat.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb, <vscale x 4 x i1> %m, i32 %evl) 1676 ret <vscale x 4 x i64> %v 1677} 1678 1679define <vscale x 4 x i64> @vssubu_vx_nxv4i64_unmasked(<vscale x 4 x i64> %va, i64 %b, i32 zeroext %evl) { 1680; RV32-LABEL: vssubu_vx_nxv4i64_unmasked: 1681; RV32: # %bb.0: 1682; RV32-NEXT: addi sp, sp, -16 1683; RV32-NEXT: .cfi_def_cfa_offset 16 1684; RV32-NEXT: sw a0, 8(sp) 1685; RV32-NEXT: sw a1, 12(sp) 1686; RV32-NEXT: addi a0, sp, 8 1687; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma 1688; RV32-NEXT: vlse64.v v12, (a0), zero 1689; RV32-NEXT: vssubu.vv v8, v8, v12 1690; RV32-NEXT: addi sp, sp, 16 1691; RV32-NEXT: .cfi_def_cfa_offset 0 1692; RV32-NEXT: ret 1693; 1694; RV64-LABEL: vssubu_vx_nxv4i64_unmasked: 1695; RV64: # %bb.0: 1696; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, ma 1697; RV64-NEXT: vssubu.vx v8, v8, a0 1698; RV64-NEXT: ret 1699 %elt.head = insertelement <vscale x 4 x i64> poison, i64 %b, i32 0 1700 %vb = shufflevector <vscale x 4 x i64> %elt.head, <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer 1701 %v = call <vscale x 4 x i64> @llvm.vp.usub.sat.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb, <vscale x 4 x i1> splat (i1 true), i32 %evl) 1702 ret <vscale x 4 x i64> %v 1703} 1704 1705define <vscale x 4 x i64> @vssubu_vi_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) { 1706; CHECK-LABEL: vssubu_vi_nxv4i64: 1707; CHECK: # %bb.0: 1708; CHECK-NEXT: li a1, -1 1709; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma 1710; CHECK-NEXT: vssubu.vx v8, v8, a1, v0.t 1711; CHECK-NEXT: ret 1712 %v = call <vscale x 4 x i64> @llvm.vp.usub.sat.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> splat (i64 -1), <vscale x 4 x i1> %m, i32 %evl) 1713 ret <vscale x 4 x i64> %v 1714} 1715 1716define <vscale x 4 x i64> @vssubu_vi_nxv4i64_unmasked(<vscale x 4 x i64> %va, i32 zeroext %evl) { 1717; CHECK-LABEL: vssubu_vi_nxv4i64_unmasked: 1718; CHECK: # %bb.0: 1719; CHECK-NEXT: li a1, -1 1720; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma 1721; CHECK-NEXT: vssubu.vx v8, v8, a1 1722; CHECK-NEXT: ret 1723 %v = call <vscale x 4 x i64> @llvm.vp.usub.sat.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> splat (i64 -1), <vscale x 4 x i1> splat (i1 true), i32 %evl) 1724 ret <vscale x 4 x i64> %v 1725} 1726 1727declare <vscale x 8 x i64> @llvm.vp.usub.sat.nxv8i64(<vscale x 8 x i64>, <vscale x 8 x i64>, <vscale x 8 x i1>, i32) 1728 1729define <vscale x 8 x i64> @vssubu_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %b, <vscale x 8 x i1> %m, i32 zeroext %evl) { 1730; CHECK-LABEL: vssubu_vv_nxv8i64: 1731; CHECK: # %bb.0: 1732; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma 1733; CHECK-NEXT: vssubu.vv v8, v8, v16, v0.t 1734; CHECK-NEXT: ret 1735 %v = call <vscale x 8 x i64> @llvm.vp.usub.sat.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %b, <vscale x 8 x i1> %m, i32 %evl) 1736 ret <vscale x 8 x i64> %v 1737} 1738 1739define <vscale x 8 x i64> @vssubu_vv_nxv8i64_unmasked(<vscale x 8 x i64> %va, <vscale x 8 x i64> %b, i32 zeroext %evl) { 1740; CHECK-LABEL: vssubu_vv_nxv8i64_unmasked: 1741; CHECK: # %bb.0: 1742; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma 1743; CHECK-NEXT: vssubu.vv v8, v8, v16 1744; CHECK-NEXT: ret 1745 %v = call <vscale x 8 x i64> @llvm.vp.usub.sat.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %b, <vscale x 8 x i1> splat (i1 true), i32 %evl) 1746 ret <vscale x 8 x i64> %v 1747} 1748 1749define <vscale x 8 x i64> @vssubu_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <vscale x 8 x i1> %m, i32 zeroext %evl) { 1750; RV32-LABEL: vssubu_vx_nxv8i64: 1751; RV32: # %bb.0: 1752; RV32-NEXT: addi sp, sp, -16 1753; RV32-NEXT: .cfi_def_cfa_offset 16 1754; RV32-NEXT: sw a0, 8(sp) 1755; RV32-NEXT: sw a1, 12(sp) 1756; RV32-NEXT: addi a0, sp, 8 1757; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma 1758; RV32-NEXT: vlse64.v v16, (a0), zero 1759; RV32-NEXT: vssubu.vv v8, v8, v16, v0.t 1760; RV32-NEXT: addi sp, sp, 16 1761; RV32-NEXT: .cfi_def_cfa_offset 0 1762; RV32-NEXT: ret 1763; 1764; RV64-LABEL: vssubu_vx_nxv8i64: 1765; RV64: # %bb.0: 1766; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma 1767; RV64-NEXT: vssubu.vx v8, v8, a0, v0.t 1768; RV64-NEXT: ret 1769 %elt.head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0 1770 %vb = shufflevector <vscale x 8 x i64> %elt.head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer 1771 %v = call <vscale x 8 x i64> @llvm.vp.usub.sat.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb, <vscale x 8 x i1> %m, i32 %evl) 1772 ret <vscale x 8 x i64> %v 1773} 1774 1775define <vscale x 8 x i64> @vssubu_vx_nxv8i64_unmasked(<vscale x 8 x i64> %va, i64 %b, i32 zeroext %evl) { 1776; RV32-LABEL: vssubu_vx_nxv8i64_unmasked: 1777; RV32: # %bb.0: 1778; RV32-NEXT: addi sp, sp, -16 1779; RV32-NEXT: .cfi_def_cfa_offset 16 1780; RV32-NEXT: sw a0, 8(sp) 1781; RV32-NEXT: sw a1, 12(sp) 1782; RV32-NEXT: addi a0, sp, 8 1783; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma 1784; RV32-NEXT: vlse64.v v16, (a0), zero 1785; RV32-NEXT: vssubu.vv v8, v8, v16 1786; RV32-NEXT: addi sp, sp, 16 1787; RV32-NEXT: .cfi_def_cfa_offset 0 1788; RV32-NEXT: ret 1789; 1790; RV64-LABEL: vssubu_vx_nxv8i64_unmasked: 1791; RV64: # %bb.0: 1792; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma 1793; RV64-NEXT: vssubu.vx v8, v8, a0 1794; RV64-NEXT: ret 1795 %elt.head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0 1796 %vb = shufflevector <vscale x 8 x i64> %elt.head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer 1797 %v = call <vscale x 8 x i64> @llvm.vp.usub.sat.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb, <vscale x 8 x i1> splat (i1 true), i32 %evl) 1798 ret <vscale x 8 x i64> %v 1799} 1800 1801define <vscale x 8 x i64> @vssubu_vi_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) { 1802; CHECK-LABEL: vssubu_vi_nxv8i64: 1803; CHECK: # %bb.0: 1804; CHECK-NEXT: li a1, -1 1805; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma 1806; CHECK-NEXT: vssubu.vx v8, v8, a1, v0.t 1807; CHECK-NEXT: ret 1808 %v = call <vscale x 8 x i64> @llvm.vp.usub.sat.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> splat (i64 -1), <vscale x 8 x i1> %m, i32 %evl) 1809 ret <vscale x 8 x i64> %v 1810} 1811 1812define <vscale x 8 x i64> @vssubu_vi_nxv8i64_unmasked(<vscale x 8 x i64> %va, i32 zeroext %evl) { 1813; CHECK-LABEL: vssubu_vi_nxv8i64_unmasked: 1814; CHECK: # %bb.0: 1815; CHECK-NEXT: li a1, -1 1816; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma 1817; CHECK-NEXT: vssubu.vx v8, v8, a1 1818; CHECK-NEXT: ret 1819 %v = call <vscale x 8 x i64> @llvm.vp.usub.sat.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> splat (i64 -1), <vscale x 8 x i1> splat (i1 true), i32 %evl) 1820 ret <vscale x 8 x i64> %v 1821} 1822