xref: /llvm-project/llvm/test/CodeGen/RISCV/rvv/vssub-vp.ll (revision 36e4176f1d83d04cdebb4e1870561099b2478d80) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s \
3; RUN:   | FileCheck %s --check-prefixes=CHECK,RV32
4; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s \
5; RUN:   | FileCheck %s --check-prefixes=CHECK,RV64
6
7declare <vscale x 8 x i7> @llvm.vp.ssub.sat.nxv8i7(<vscale x 8 x i7>, <vscale x 8 x i7>, <vscale x 8 x i1>, i32)
8
9define <vscale x 8 x i7> @vssub_vx_nxv8i7(<vscale x 8 x i7> %a, i7 signext %b, <vscale x 8 x i1> %mask, i32 zeroext %evl) {
10; CHECK-LABEL: vssub_vx_nxv8i7:
11; CHECK:       # %bb.0:
12; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma
13; CHECK-NEXT:    vadd.vv v8, v8, v8
14; CHECK-NEXT:    vsra.vi v8, v8, 1
15; CHECK-NEXT:    vsub.vx v8, v8, a0, v0.t
16; CHECK-NEXT:    li a0, 63
17; CHECK-NEXT:    vmin.vx v8, v8, a0, v0.t
18; CHECK-NEXT:    li a0, 192
19; CHECK-NEXT:    vmax.vx v8, v8, a0, v0.t
20; CHECK-NEXT:    ret
21  %elt.head = insertelement <vscale x 8 x i7> poison, i7 %b, i32 0
22  %vb = shufflevector <vscale x 8 x i7> %elt.head, <vscale x 8 x i7> poison, <vscale x 8 x i32> zeroinitializer
23  %v = call <vscale x 8 x i7> @llvm.vp.ssub.sat.nxv8i7(<vscale x 8 x i7> %a, <vscale x 8 x i7> %vb, <vscale x 8 x i1> %mask, i32 %evl)
24  ret <vscale x 8 x i7> %v
25}
26
27declare <vscale x 1 x i8> @llvm.vp.ssub.sat.nxv1i8(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
28
29define <vscale x 1 x i8> @vssub_vv_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
30; CHECK-LABEL: vssub_vv_nxv1i8:
31; CHECK:       # %bb.0:
32; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, ma
33; CHECK-NEXT:    vssub.vv v8, v8, v9, v0.t
34; CHECK-NEXT:    ret
35  %v = call <vscale x 1 x i8> @llvm.vp.ssub.sat.nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %b, <vscale x 1 x i1> %m, i32 %evl)
36  ret <vscale x 1 x i8> %v
37}
38
39define <vscale x 1 x i8> @vssub_vv_nxv1i8_unmasked(<vscale x 1 x i8> %va, <vscale x 1 x i8> %b, i32 zeroext %evl) {
40; CHECK-LABEL: vssub_vv_nxv1i8_unmasked:
41; CHECK:       # %bb.0:
42; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, ma
43; CHECK-NEXT:    vssub.vv v8, v8, v9
44; CHECK-NEXT:    ret
45  %v = call <vscale x 1 x i8> @llvm.vp.ssub.sat.nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %b, <vscale x 1 x i1> splat (i1 true), i32 %evl)
46  ret <vscale x 1 x i8> %v
47}
48
49define <vscale x 1 x i8> @vssub_vx_nxv1i8(<vscale x 1 x i8> %va, i8 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
50; CHECK-LABEL: vssub_vx_nxv1i8:
51; CHECK:       # %bb.0:
52; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma
53; CHECK-NEXT:    vssub.vx v8, v8, a0, v0.t
54; CHECK-NEXT:    ret
55  %elt.head = insertelement <vscale x 1 x i8> poison, i8 %b, i32 0
56  %vb = shufflevector <vscale x 1 x i8> %elt.head, <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer
57  %v = call <vscale x 1 x i8> @llvm.vp.ssub.sat.nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %vb, <vscale x 1 x i1> %m, i32 %evl)
58  ret <vscale x 1 x i8> %v
59}
60
61define <vscale x 1 x i8> @vssub_vx_nxv1i8_commute(<vscale x 1 x i8> %va, i8 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
62; CHECK-LABEL: vssub_vx_nxv1i8_commute:
63; CHECK:       # %bb.0:
64; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma
65; CHECK-NEXT:    vmv.v.x v9, a0
66; CHECK-NEXT:    vssub.vv v8, v9, v8, v0.t
67; CHECK-NEXT:    ret
68  %elt.head = insertelement <vscale x 1 x i8> poison, i8 %b, i32 0
69  %vb = shufflevector <vscale x 1 x i8> %elt.head, <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer
70  %v = call <vscale x 1 x i8> @llvm.vp.ssub.sat.nxv1i8(<vscale x 1 x i8> %vb, <vscale x 1 x i8> %va, <vscale x 1 x i1> %m, i32 %evl)
71  ret <vscale x 1 x i8> %v
72}
73
74define <vscale x 1 x i8> @vssub_vx_nxv1i8_unmasked(<vscale x 1 x i8> %va, i8 %b, i32 zeroext %evl) {
75; CHECK-LABEL: vssub_vx_nxv1i8_unmasked:
76; CHECK:       # %bb.0:
77; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma
78; CHECK-NEXT:    vssub.vx v8, v8, a0
79; CHECK-NEXT:    ret
80  %elt.head = insertelement <vscale x 1 x i8> poison, i8 %b, i32 0
81  %vb = shufflevector <vscale x 1 x i8> %elt.head, <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer
82  %v = call <vscale x 1 x i8> @llvm.vp.ssub.sat.nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %vb, <vscale x 1 x i1> splat (i1 true), i32 %evl)
83  ret <vscale x 1 x i8> %v
84}
85
86define <vscale x 1 x i8> @vssub_vi_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
87; CHECK-LABEL: vssub_vi_nxv1i8:
88; CHECK:       # %bb.0:
89; CHECK-NEXT:    li a1, -1
90; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, ma
91; CHECK-NEXT:    vssub.vx v8, v8, a1, v0.t
92; CHECK-NEXT:    ret
93  %v = call <vscale x 1 x i8> @llvm.vp.ssub.sat.nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> splat (i8 -1), <vscale x 1 x i1> %m, i32 %evl)
94  ret <vscale x 1 x i8> %v
95}
96
97define <vscale x 1 x i8> @vssub_vi_nxv1i8_unmasked(<vscale x 1 x i8> %va, i32 zeroext %evl) {
98; CHECK-LABEL: vssub_vi_nxv1i8_unmasked:
99; CHECK:       # %bb.0:
100; CHECK-NEXT:    li a1, -1
101; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, ma
102; CHECK-NEXT:    vssub.vx v8, v8, a1
103; CHECK-NEXT:    ret
104  %v = call <vscale x 1 x i8> @llvm.vp.ssub.sat.nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> splat (i8 -1), <vscale x 1 x i1> splat (i1 true), i32 %evl)
105  ret <vscale x 1 x i8> %v
106}
107
108declare <vscale x 2 x i8> @llvm.vp.ssub.sat.nxv2i8(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i32)
109
110define <vscale x 2 x i8> @vssub_vv_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %b, <vscale x 2 x i1> %m, i32 zeroext %evl) {
111; CHECK-LABEL: vssub_vv_nxv2i8:
112; CHECK:       # %bb.0:
113; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, ma
114; CHECK-NEXT:    vssub.vv v8, v8, v9, v0.t
115; CHECK-NEXT:    ret
116  %v = call <vscale x 2 x i8> @llvm.vp.ssub.sat.nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %b, <vscale x 2 x i1> %m, i32 %evl)
117  ret <vscale x 2 x i8> %v
118}
119
120define <vscale x 2 x i8> @vssub_vv_nxv2i8_unmasked(<vscale x 2 x i8> %va, <vscale x 2 x i8> %b, i32 zeroext %evl) {
121; CHECK-LABEL: vssub_vv_nxv2i8_unmasked:
122; CHECK:       # %bb.0:
123; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, ma
124; CHECK-NEXT:    vssub.vv v8, v8, v9
125; CHECK-NEXT:    ret
126  %v = call <vscale x 2 x i8> @llvm.vp.ssub.sat.nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %b, <vscale x 2 x i1> splat (i1 true), i32 %evl)
127  ret <vscale x 2 x i8> %v
128}
129
130define <vscale x 2 x i8> @vssub_vx_nxv2i8(<vscale x 2 x i8> %va, i8 %b, <vscale x 2 x i1> %m, i32 zeroext %evl) {
131; CHECK-LABEL: vssub_vx_nxv2i8:
132; CHECK:       # %bb.0:
133; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma
134; CHECK-NEXT:    vssub.vx v8, v8, a0, v0.t
135; CHECK-NEXT:    ret
136  %elt.head = insertelement <vscale x 2 x i8> poison, i8 %b, i32 0
137  %vb = shufflevector <vscale x 2 x i8> %elt.head, <vscale x 2 x i8> poison, <vscale x 2 x i32> zeroinitializer
138  %v = call <vscale x 2 x i8> @llvm.vp.ssub.sat.nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %vb, <vscale x 2 x i1> %m, i32 %evl)
139  ret <vscale x 2 x i8> %v
140}
141
142define <vscale x 2 x i8> @vssub_vx_nxv2i8_unmasked(<vscale x 2 x i8> %va, i8 %b, i32 zeroext %evl) {
143; CHECK-LABEL: vssub_vx_nxv2i8_unmasked:
144; CHECK:       # %bb.0:
145; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma
146; CHECK-NEXT:    vssub.vx v8, v8, a0
147; CHECK-NEXT:    ret
148  %elt.head = insertelement <vscale x 2 x i8> poison, i8 %b, i32 0
149  %vb = shufflevector <vscale x 2 x i8> %elt.head, <vscale x 2 x i8> poison, <vscale x 2 x i32> zeroinitializer
150  %v = call <vscale x 2 x i8> @llvm.vp.ssub.sat.nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %vb, <vscale x 2 x i1> splat (i1 true), i32 %evl)
151  ret <vscale x 2 x i8> %v
152}
153
154define <vscale x 2 x i8> @vssub_vi_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
155; CHECK-LABEL: vssub_vi_nxv2i8:
156; CHECK:       # %bb.0:
157; CHECK-NEXT:    li a1, -1
158; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, ma
159; CHECK-NEXT:    vssub.vx v8, v8, a1, v0.t
160; CHECK-NEXT:    ret
161  %v = call <vscale x 2 x i8> @llvm.vp.ssub.sat.nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> splat (i8 -1), <vscale x 2 x i1> %m, i32 %evl)
162  ret <vscale x 2 x i8> %v
163}
164
165define <vscale x 2 x i8> @vssub_vi_nxv2i8_unmasked(<vscale x 2 x i8> %va, i32 zeroext %evl) {
166; CHECK-LABEL: vssub_vi_nxv2i8_unmasked:
167; CHECK:       # %bb.0:
168; CHECK-NEXT:    li a1, -1
169; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, ma
170; CHECK-NEXT:    vssub.vx v8, v8, a1
171; CHECK-NEXT:    ret
172  %v = call <vscale x 2 x i8> @llvm.vp.ssub.sat.nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> splat (i8 -1), <vscale x 2 x i1> splat (i1 true), i32 %evl)
173  ret <vscale x 2 x i8> %v
174}
175
176declare <vscale x 3 x i8> @llvm.vp.ssub.sat.nxv3i8(<vscale x 3 x i8>, <vscale x 3 x i8>, <vscale x 3 x i1>, i32)
177
178define <vscale x 3 x i8> @vssub_vv_nxv3i8(<vscale x 3 x i8> %va, <vscale x 3 x i8> %b, <vscale x 3 x i1> %m, i32 zeroext %evl) {
179; CHECK-LABEL: vssub_vv_nxv3i8:
180; CHECK:       # %bb.0:
181; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma
182; CHECK-NEXT:    vssub.vv v8, v8, v9, v0.t
183; CHECK-NEXT:    ret
184  %v = call <vscale x 3 x i8> @llvm.vp.ssub.sat.nxv3i8(<vscale x 3 x i8> %va, <vscale x 3 x i8> %b, <vscale x 3 x i1> %m, i32 %evl)
185  ret <vscale x 3 x i8> %v
186}
187
188define <vscale x 3 x i8> @vssub_vv_nxv3i8_unmasked(<vscale x 3 x i8> %va, <vscale x 3 x i8> %b, i32 zeroext %evl) {
189; CHECK-LABEL: vssub_vv_nxv3i8_unmasked:
190; CHECK:       # %bb.0:
191; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma
192; CHECK-NEXT:    vssub.vv v8, v8, v9
193; CHECK-NEXT:    ret
194  %v = call <vscale x 3 x i8> @llvm.vp.ssub.sat.nxv3i8(<vscale x 3 x i8> %va, <vscale x 3 x i8> %b, <vscale x 3 x i1> splat (i1 true), i32 %evl)
195  ret <vscale x 3 x i8> %v
196}
197
198define <vscale x 3 x i8> @vssub_vx_nxv3i8(<vscale x 3 x i8> %va, i8 %b, <vscale x 3 x i1> %m, i32 zeroext %evl) {
199; CHECK-LABEL: vssub_vx_nxv3i8:
200; CHECK:       # %bb.0:
201; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma
202; CHECK-NEXT:    vssub.vx v8, v8, a0, v0.t
203; CHECK-NEXT:    ret
204  %elt.head = insertelement <vscale x 3 x i8> poison, i8 %b, i32 0
205  %vb = shufflevector <vscale x 3 x i8> %elt.head, <vscale x 3 x i8> poison, <vscale x 3 x i32> zeroinitializer
206  %v = call <vscale x 3 x i8> @llvm.vp.ssub.sat.nxv3i8(<vscale x 3 x i8> %va, <vscale x 3 x i8> %vb, <vscale x 3 x i1> %m, i32 %evl)
207  ret <vscale x 3 x i8> %v
208}
209
210define <vscale x 3 x i8> @vssub_vx_nxv3i8_unmasked(<vscale x 3 x i8> %va, i8 %b, i32 zeroext %evl) {
211; CHECK-LABEL: vssub_vx_nxv3i8_unmasked:
212; CHECK:       # %bb.0:
213; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma
214; CHECK-NEXT:    vssub.vx v8, v8, a0
215; CHECK-NEXT:    ret
216  %elt.head = insertelement <vscale x 3 x i8> poison, i8 %b, i32 0
217  %vb = shufflevector <vscale x 3 x i8> %elt.head, <vscale x 3 x i8> poison, <vscale x 3 x i32> zeroinitializer
218  %v = call <vscale x 3 x i8> @llvm.vp.ssub.sat.nxv3i8(<vscale x 3 x i8> %va, <vscale x 3 x i8> %vb, <vscale x 3 x i1> splat (i1 true), i32 %evl)
219  ret <vscale x 3 x i8> %v
220}
221
222define <vscale x 3 x i8> @vssub_vi_nxv3i8(<vscale x 3 x i8> %va, <vscale x 3 x i1> %m, i32 zeroext %evl) {
223; CHECK-LABEL: vssub_vi_nxv3i8:
224; CHECK:       # %bb.0:
225; CHECK-NEXT:    li a1, -1
226; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma
227; CHECK-NEXT:    vssub.vx v8, v8, a1, v0.t
228; CHECK-NEXT:    ret
229  %v = call <vscale x 3 x i8> @llvm.vp.ssub.sat.nxv3i8(<vscale x 3 x i8> %va, <vscale x 3 x i8> splat (i8 -1), <vscale x 3 x i1> %m, i32 %evl)
230  ret <vscale x 3 x i8> %v
231}
232
233define <vscale x 3 x i8> @vssub_vi_nxv3i8_unmasked(<vscale x 3 x i8> %va, i32 zeroext %evl) {
234; CHECK-LABEL: vssub_vi_nxv3i8_unmasked:
235; CHECK:       # %bb.0:
236; CHECK-NEXT:    li a1, -1
237; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma
238; CHECK-NEXT:    vssub.vx v8, v8, a1
239; CHECK-NEXT:    ret
240  %v = call <vscale x 3 x i8> @llvm.vp.ssub.sat.nxv3i8(<vscale x 3 x i8> %va, <vscale x 3 x i8> splat (i8 -1), <vscale x 3 x i1> splat (i1 true), i32 %evl)
241  ret <vscale x 3 x i8> %v
242}
243
244declare <vscale x 4 x i8> @llvm.vp.ssub.sat.nxv4i8(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i32)
245
246define <vscale x 4 x i8> @vssub_vv_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %b, <vscale x 4 x i1> %m, i32 zeroext %evl) {
247; CHECK-LABEL: vssub_vv_nxv4i8:
248; CHECK:       # %bb.0:
249; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma
250; CHECK-NEXT:    vssub.vv v8, v8, v9, v0.t
251; CHECK-NEXT:    ret
252  %v = call <vscale x 4 x i8> @llvm.vp.ssub.sat.nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %b, <vscale x 4 x i1> %m, i32 %evl)
253  ret <vscale x 4 x i8> %v
254}
255
256define <vscale x 4 x i8> @vssub_vv_nxv4i8_unmasked(<vscale x 4 x i8> %va, <vscale x 4 x i8> %b, i32 zeroext %evl) {
257; CHECK-LABEL: vssub_vv_nxv4i8_unmasked:
258; CHECK:       # %bb.0:
259; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma
260; CHECK-NEXT:    vssub.vv v8, v8, v9
261; CHECK-NEXT:    ret
262  %v = call <vscale x 4 x i8> @llvm.vp.ssub.sat.nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %b, <vscale x 4 x i1> splat (i1 true), i32 %evl)
263  ret <vscale x 4 x i8> %v
264}
265
266define <vscale x 4 x i8> @vssub_vx_nxv4i8(<vscale x 4 x i8> %va, i8 %b, <vscale x 4 x i1> %m, i32 zeroext %evl) {
267; CHECK-LABEL: vssub_vx_nxv4i8:
268; CHECK:       # %bb.0:
269; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma
270; CHECK-NEXT:    vssub.vx v8, v8, a0, v0.t
271; CHECK-NEXT:    ret
272  %elt.head = insertelement <vscale x 4 x i8> poison, i8 %b, i32 0
273  %vb = shufflevector <vscale x 4 x i8> %elt.head, <vscale x 4 x i8> poison, <vscale x 4 x i32> zeroinitializer
274  %v = call <vscale x 4 x i8> @llvm.vp.ssub.sat.nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %vb, <vscale x 4 x i1> %m, i32 %evl)
275  ret <vscale x 4 x i8> %v
276}
277
278define <vscale x 4 x i8> @vssub_vx_nxv4i8_unmasked(<vscale x 4 x i8> %va, i8 %b, i32 zeroext %evl) {
279; CHECK-LABEL: vssub_vx_nxv4i8_unmasked:
280; CHECK:       # %bb.0:
281; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma
282; CHECK-NEXT:    vssub.vx v8, v8, a0
283; CHECK-NEXT:    ret
284  %elt.head = insertelement <vscale x 4 x i8> poison, i8 %b, i32 0
285  %vb = shufflevector <vscale x 4 x i8> %elt.head, <vscale x 4 x i8> poison, <vscale x 4 x i32> zeroinitializer
286  %v = call <vscale x 4 x i8> @llvm.vp.ssub.sat.nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %vb, <vscale x 4 x i1> splat (i1 true), i32 %evl)
287  ret <vscale x 4 x i8> %v
288}
289
290define <vscale x 4 x i8> @vssub_vi_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {
291; CHECK-LABEL: vssub_vi_nxv4i8:
292; CHECK:       # %bb.0:
293; CHECK-NEXT:    li a1, -1
294; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma
295; CHECK-NEXT:    vssub.vx v8, v8, a1, v0.t
296; CHECK-NEXT:    ret
297  %v = call <vscale x 4 x i8> @llvm.vp.ssub.sat.nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> splat (i8 -1), <vscale x 4 x i1> %m, i32 %evl)
298  ret <vscale x 4 x i8> %v
299}
300
301define <vscale x 4 x i8> @vssub_vi_nxv4i8_unmasked(<vscale x 4 x i8> %va, i32 zeroext %evl) {
302; CHECK-LABEL: vssub_vi_nxv4i8_unmasked:
303; CHECK:       # %bb.0:
304; CHECK-NEXT:    li a1, -1
305; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma
306; CHECK-NEXT:    vssub.vx v8, v8, a1
307; CHECK-NEXT:    ret
308  %v = call <vscale x 4 x i8> @llvm.vp.ssub.sat.nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> splat (i8 -1), <vscale x 4 x i1> splat (i1 true), i32 %evl)
309  ret <vscale x 4 x i8> %v
310}
311
312declare <vscale x 8 x i8> @llvm.vp.ssub.sat.nxv8i8(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i1>, i32)
313
314define <vscale x 8 x i8> @vssub_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
315; CHECK-LABEL: vssub_vv_nxv8i8:
316; CHECK:       # %bb.0:
317; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, ma
318; CHECK-NEXT:    vssub.vv v8, v8, v9, v0.t
319; CHECK-NEXT:    ret
320  %v = call <vscale x 8 x i8> @llvm.vp.ssub.sat.nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %b, <vscale x 8 x i1> %m, i32 %evl)
321  ret <vscale x 8 x i8> %v
322}
323
324define <vscale x 8 x i8> @vssub_vv_nxv8i8_unmasked(<vscale x 8 x i8> %va, <vscale x 8 x i8> %b, i32 zeroext %evl) {
325; CHECK-LABEL: vssub_vv_nxv8i8_unmasked:
326; CHECK:       # %bb.0:
327; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, ma
328; CHECK-NEXT:    vssub.vv v8, v8, v9
329; CHECK-NEXT:    ret
330  %v = call <vscale x 8 x i8> @llvm.vp.ssub.sat.nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %b, <vscale x 8 x i1> splat (i1 true), i32 %evl)
331  ret <vscale x 8 x i8> %v
332}
333
334define <vscale x 8 x i8> @vssub_vx_nxv8i8(<vscale x 8 x i8> %va, i8 %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
335; CHECK-LABEL: vssub_vx_nxv8i8:
336; CHECK:       # %bb.0:
337; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma
338; CHECK-NEXT:    vssub.vx v8, v8, a0, v0.t
339; CHECK-NEXT:    ret
340  %elt.head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0
341  %vb = shufflevector <vscale x 8 x i8> %elt.head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
342  %v = call <vscale x 8 x i8> @llvm.vp.ssub.sat.nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb, <vscale x 8 x i1> %m, i32 %evl)
343  ret <vscale x 8 x i8> %v
344}
345
346define <vscale x 8 x i8> @vssub_vx_nxv8i8_unmasked(<vscale x 8 x i8> %va, i8 %b, i32 zeroext %evl) {
347; CHECK-LABEL: vssub_vx_nxv8i8_unmasked:
348; CHECK:       # %bb.0:
349; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma
350; CHECK-NEXT:    vssub.vx v8, v8, a0
351; CHECK-NEXT:    ret
352  %elt.head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0
353  %vb = shufflevector <vscale x 8 x i8> %elt.head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
354  %v = call <vscale x 8 x i8> @llvm.vp.ssub.sat.nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb, <vscale x 8 x i1> splat (i1 true), i32 %evl)
355  ret <vscale x 8 x i8> %v
356}
357
358define <vscale x 8 x i8> @vssub_vi_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {
359; CHECK-LABEL: vssub_vi_nxv8i8:
360; CHECK:       # %bb.0:
361; CHECK-NEXT:    li a1, -1
362; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, ma
363; CHECK-NEXT:    vssub.vx v8, v8, a1, v0.t
364; CHECK-NEXT:    ret
365  %v = call <vscale x 8 x i8> @llvm.vp.ssub.sat.nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> splat (i8 -1), <vscale x 8 x i1> %m, i32 %evl)
366  ret <vscale x 8 x i8> %v
367}
368
369define <vscale x 8 x i8> @vssub_vi_nxv8i8_unmasked(<vscale x 8 x i8> %va, i32 zeroext %evl) {
370; CHECK-LABEL: vssub_vi_nxv8i8_unmasked:
371; CHECK:       # %bb.0:
372; CHECK-NEXT:    li a1, -1
373; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, ma
374; CHECK-NEXT:    vssub.vx v8, v8, a1
375; CHECK-NEXT:    ret
376  %v = call <vscale x 8 x i8> @llvm.vp.ssub.sat.nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> splat (i8 -1), <vscale x 8 x i1> splat (i1 true), i32 %evl)
377  ret <vscale x 8 x i8> %v
378}
379
380declare <vscale x 16 x i8> @llvm.vp.ssub.sat.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i1>, i32)
381
382define <vscale x 16 x i8> @vssub_vv_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %b, <vscale x 16 x i1> %m, i32 zeroext %evl) {
383; CHECK-LABEL: vssub_vv_nxv16i8:
384; CHECK:       # %bb.0:
385; CHECK-NEXT:    vsetvli zero, a0, e8, m2, ta, ma
386; CHECK-NEXT:    vssub.vv v8, v8, v10, v0.t
387; CHECK-NEXT:    ret
388  %v = call <vscale x 16 x i8> @llvm.vp.ssub.sat.nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %b, <vscale x 16 x i1> %m, i32 %evl)
389  ret <vscale x 16 x i8> %v
390}
391
392define <vscale x 16 x i8> @vssub_vv_nxv16i8_unmasked(<vscale x 16 x i8> %va, <vscale x 16 x i8> %b, i32 zeroext %evl) {
393; CHECK-LABEL: vssub_vv_nxv16i8_unmasked:
394; CHECK:       # %bb.0:
395; CHECK-NEXT:    vsetvli zero, a0, e8, m2, ta, ma
396; CHECK-NEXT:    vssub.vv v8, v8, v10
397; CHECK-NEXT:    ret
398  %v = call <vscale x 16 x i8> @llvm.vp.ssub.sat.nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %b, <vscale x 16 x i1> splat (i1 true), i32 %evl)
399  ret <vscale x 16 x i8> %v
400}
401
402define <vscale x 16 x i8> @vssub_vx_nxv16i8(<vscale x 16 x i8> %va, i8 %b, <vscale x 16 x i1> %m, i32 zeroext %evl) {
403; CHECK-LABEL: vssub_vx_nxv16i8:
404; CHECK:       # %bb.0:
405; CHECK-NEXT:    vsetvli zero, a1, e8, m2, ta, ma
406; CHECK-NEXT:    vssub.vx v8, v8, a0, v0.t
407; CHECK-NEXT:    ret
408  %elt.head = insertelement <vscale x 16 x i8> poison, i8 %b, i32 0
409  %vb = shufflevector <vscale x 16 x i8> %elt.head, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
410  %v = call <vscale x 16 x i8> @llvm.vp.ssub.sat.nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %vb, <vscale x 16 x i1> %m, i32 %evl)
411  ret <vscale x 16 x i8> %v
412}
413
414define <vscale x 16 x i8> @vssub_vx_nxv16i8_unmasked(<vscale x 16 x i8> %va, i8 %b, i32 zeroext %evl) {
415; CHECK-LABEL: vssub_vx_nxv16i8_unmasked:
416; CHECK:       # %bb.0:
417; CHECK-NEXT:    vsetvli zero, a1, e8, m2, ta, ma
418; CHECK-NEXT:    vssub.vx v8, v8, a0
419; CHECK-NEXT:    ret
420  %elt.head = insertelement <vscale x 16 x i8> poison, i8 %b, i32 0
421  %vb = shufflevector <vscale x 16 x i8> %elt.head, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
422  %v = call <vscale x 16 x i8> @llvm.vp.ssub.sat.nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %vb, <vscale x 16 x i1> splat (i1 true), i32 %evl)
423  ret <vscale x 16 x i8> %v
424}
425
426define <vscale x 16 x i8> @vssub_vi_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {
427; CHECK-LABEL: vssub_vi_nxv16i8:
428; CHECK:       # %bb.0:
429; CHECK-NEXT:    li a1, -1
430; CHECK-NEXT:    vsetvli zero, a0, e8, m2, ta, ma
431; CHECK-NEXT:    vssub.vx v8, v8, a1, v0.t
432; CHECK-NEXT:    ret
433  %v = call <vscale x 16 x i8> @llvm.vp.ssub.sat.nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> splat (i8 -1), <vscale x 16 x i1> %m, i32 %evl)
434  ret <vscale x 16 x i8> %v
435}
436
437define <vscale x 16 x i8> @vssub_vi_nxv16i8_unmasked(<vscale x 16 x i8> %va, i32 zeroext %evl) {
438; CHECK-LABEL: vssub_vi_nxv16i8_unmasked:
439; CHECK:       # %bb.0:
440; CHECK-NEXT:    li a1, -1
441; CHECK-NEXT:    vsetvli zero, a0, e8, m2, ta, ma
442; CHECK-NEXT:    vssub.vx v8, v8, a1
443; CHECK-NEXT:    ret
444  %v = call <vscale x 16 x i8> @llvm.vp.ssub.sat.nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> splat (i8 -1), <vscale x 16 x i1> splat (i1 true), i32 %evl)
445  ret <vscale x 16 x i8> %v
446}
447
448declare <vscale x 32 x i8> @llvm.vp.ssub.sat.nxv32i8(<vscale x 32 x i8>, <vscale x 32 x i8>, <vscale x 32 x i1>, i32)
449
450define <vscale x 32 x i8> @vssub_vv_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %b, <vscale x 32 x i1> %m, i32 zeroext %evl) {
451; CHECK-LABEL: vssub_vv_nxv32i8:
452; CHECK:       # %bb.0:
453; CHECK-NEXT:    vsetvli zero, a0, e8, m4, ta, ma
454; CHECK-NEXT:    vssub.vv v8, v8, v12, v0.t
455; CHECK-NEXT:    ret
456  %v = call <vscale x 32 x i8> @llvm.vp.ssub.sat.nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %b, <vscale x 32 x i1> %m, i32 %evl)
457  ret <vscale x 32 x i8> %v
458}
459
460define <vscale x 32 x i8> @vssub_vv_nxv32i8_unmasked(<vscale x 32 x i8> %va, <vscale x 32 x i8> %b, i32 zeroext %evl) {
461; CHECK-LABEL: vssub_vv_nxv32i8_unmasked:
462; CHECK:       # %bb.0:
463; CHECK-NEXT:    vsetvli zero, a0, e8, m4, ta, ma
464; CHECK-NEXT:    vssub.vv v8, v8, v12
465; CHECK-NEXT:    ret
466  %v = call <vscale x 32 x i8> @llvm.vp.ssub.sat.nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %b, <vscale x 32 x i1> splat (i1 true), i32 %evl)
467  ret <vscale x 32 x i8> %v
468}
469
470define <vscale x 32 x i8> @vssub_vx_nxv32i8(<vscale x 32 x i8> %va, i8 %b, <vscale x 32 x i1> %m, i32 zeroext %evl) {
471; CHECK-LABEL: vssub_vx_nxv32i8:
472; CHECK:       # %bb.0:
473; CHECK-NEXT:    vsetvli zero, a1, e8, m4, ta, ma
474; CHECK-NEXT:    vssub.vx v8, v8, a0, v0.t
475; CHECK-NEXT:    ret
476  %elt.head = insertelement <vscale x 32 x i8> poison, i8 %b, i32 0
477  %vb = shufflevector <vscale x 32 x i8> %elt.head, <vscale x 32 x i8> poison, <vscale x 32 x i32> zeroinitializer
478  %v = call <vscale x 32 x i8> @llvm.vp.ssub.sat.nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %vb, <vscale x 32 x i1> %m, i32 %evl)
479  ret <vscale x 32 x i8> %v
480}
481
482define <vscale x 32 x i8> @vssub_vx_nxv32i8_unmasked(<vscale x 32 x i8> %va, i8 %b, i32 zeroext %evl) {
483; CHECK-LABEL: vssub_vx_nxv32i8_unmasked:
484; CHECK:       # %bb.0:
485; CHECK-NEXT:    vsetvli zero, a1, e8, m4, ta, ma
486; CHECK-NEXT:    vssub.vx v8, v8, a0
487; CHECK-NEXT:    ret
488  %elt.head = insertelement <vscale x 32 x i8> poison, i8 %b, i32 0
489  %vb = shufflevector <vscale x 32 x i8> %elt.head, <vscale x 32 x i8> poison, <vscale x 32 x i32> zeroinitializer
490  %v = call <vscale x 32 x i8> @llvm.vp.ssub.sat.nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %vb, <vscale x 32 x i1> splat (i1 true), i32 %evl)
491  ret <vscale x 32 x i8> %v
492}
493
494define <vscale x 32 x i8> @vssub_vi_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {
495; CHECK-LABEL: vssub_vi_nxv32i8:
496; CHECK:       # %bb.0:
497; CHECK-NEXT:    li a1, -1
498; CHECK-NEXT:    vsetvli zero, a0, e8, m4, ta, ma
499; CHECK-NEXT:    vssub.vx v8, v8, a1, v0.t
500; CHECK-NEXT:    ret
501  %v = call <vscale x 32 x i8> @llvm.vp.ssub.sat.nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> splat (i8 -1), <vscale x 32 x i1> %m, i32 %evl)
502  ret <vscale x 32 x i8> %v
503}
504
505define <vscale x 32 x i8> @vssub_vi_nxv32i8_unmasked(<vscale x 32 x i8> %va, i32 zeroext %evl) {
506; CHECK-LABEL: vssub_vi_nxv32i8_unmasked:
507; CHECK:       # %bb.0:
508; CHECK-NEXT:    li a1, -1
509; CHECK-NEXT:    vsetvli zero, a0, e8, m4, ta, ma
510; CHECK-NEXT:    vssub.vx v8, v8, a1
511; CHECK-NEXT:    ret
512  %v = call <vscale x 32 x i8> @llvm.vp.ssub.sat.nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> splat (i8 -1), <vscale x 32 x i1> splat (i1 true), i32 %evl)
513  ret <vscale x 32 x i8> %v
514}
515
516declare <vscale x 64 x i8> @llvm.vp.ssub.sat.nxv64i8(<vscale x 64 x i8>, <vscale x 64 x i8>, <vscale x 64 x i1>, i32)
517
518define <vscale x 64 x i8> @vssub_vv_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %b, <vscale x 64 x i1> %m, i32 zeroext %evl) {
519; CHECK-LABEL: vssub_vv_nxv64i8:
520; CHECK:       # %bb.0:
521; CHECK-NEXT:    vsetvli zero, a0, e8, m8, ta, ma
522; CHECK-NEXT:    vssub.vv v8, v8, v16, v0.t
523; CHECK-NEXT:    ret
524  %v = call <vscale x 64 x i8> @llvm.vp.ssub.sat.nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %b, <vscale x 64 x i1> %m, i32 %evl)
525  ret <vscale x 64 x i8> %v
526}
527
528define <vscale x 64 x i8> @vssub_vv_nxv64i8_unmasked(<vscale x 64 x i8> %va, <vscale x 64 x i8> %b, i32 zeroext %evl) {
529; CHECK-LABEL: vssub_vv_nxv64i8_unmasked:
530; CHECK:       # %bb.0:
531; CHECK-NEXT:    vsetvli zero, a0, e8, m8, ta, ma
532; CHECK-NEXT:    vssub.vv v8, v8, v16
533; CHECK-NEXT:    ret
534  %v = call <vscale x 64 x i8> @llvm.vp.ssub.sat.nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %b, <vscale x 64 x i1> splat (i1 true), i32 %evl)
535  ret <vscale x 64 x i8> %v
536}
537
538define <vscale x 64 x i8> @vssub_vx_nxv64i8(<vscale x 64 x i8> %va, i8 %b, <vscale x 64 x i1> %m, i32 zeroext %evl) {
539; CHECK-LABEL: vssub_vx_nxv64i8:
540; CHECK:       # %bb.0:
541; CHECK-NEXT:    vsetvli zero, a1, e8, m8, ta, ma
542; CHECK-NEXT:    vssub.vx v8, v8, a0, v0.t
543; CHECK-NEXT:    ret
544  %elt.head = insertelement <vscale x 64 x i8> poison, i8 %b, i32 0
545  %vb = shufflevector <vscale x 64 x i8> %elt.head, <vscale x 64 x i8> poison, <vscale x 64 x i32> zeroinitializer
546  %v = call <vscale x 64 x i8> @llvm.vp.ssub.sat.nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %vb, <vscale x 64 x i1> %m, i32 %evl)
547  ret <vscale x 64 x i8> %v
548}
549
550define <vscale x 64 x i8> @vssub_vx_nxv64i8_unmasked(<vscale x 64 x i8> %va, i8 %b, i32 zeroext %evl) {
551; CHECK-LABEL: vssub_vx_nxv64i8_unmasked:
552; CHECK:       # %bb.0:
553; CHECK-NEXT:    vsetvli zero, a1, e8, m8, ta, ma
554; CHECK-NEXT:    vssub.vx v8, v8, a0
555; CHECK-NEXT:    ret
556  %elt.head = insertelement <vscale x 64 x i8> poison, i8 %b, i32 0
557  %vb = shufflevector <vscale x 64 x i8> %elt.head, <vscale x 64 x i8> poison, <vscale x 64 x i32> zeroinitializer
558  %v = call <vscale x 64 x i8> @llvm.vp.ssub.sat.nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %vb, <vscale x 64 x i1> splat (i1 true), i32 %evl)
559  ret <vscale x 64 x i8> %v
560}
561
562define <vscale x 64 x i8> @vssub_vi_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i1> %m, i32 zeroext %evl) {
563; CHECK-LABEL: vssub_vi_nxv64i8:
564; CHECK:       # %bb.0:
565; CHECK-NEXT:    li a1, -1
566; CHECK-NEXT:    vsetvli zero, a0, e8, m8, ta, ma
567; CHECK-NEXT:    vssub.vx v8, v8, a1, v0.t
568; CHECK-NEXT:    ret
569  %v = call <vscale x 64 x i8> @llvm.vp.ssub.sat.nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> splat (i8 -1), <vscale x 64 x i1> %m, i32 %evl)
570  ret <vscale x 64 x i8> %v
571}
572
573define <vscale x 64 x i8> @vssub_vi_nxv64i8_unmasked(<vscale x 64 x i8> %va, i32 zeroext %evl) {
574; CHECK-LABEL: vssub_vi_nxv64i8_unmasked:
575; CHECK:       # %bb.0:
576; CHECK-NEXT:    li a1, -1
577; CHECK-NEXT:    vsetvli zero, a0, e8, m8, ta, ma
578; CHECK-NEXT:    vssub.vx v8, v8, a1
579; CHECK-NEXT:    ret
580  %v = call <vscale x 64 x i8> @llvm.vp.ssub.sat.nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> splat (i8 -1), <vscale x 64 x i1> splat (i1 true), i32 %evl)
581  ret <vscale x 64 x i8> %v
582}
583
584; Test that split-legalization works when the mask itself needs splitting.
585
586declare <vscale x 128 x i8> @llvm.vp.ssub.sat.nxv128i8(<vscale x 128 x i8>, <vscale x 128 x i8>, <vscale x 128 x i1>, i32)
587
588define <vscale x 128 x i8> @vssub_vi_nxv128i8(<vscale x 128 x i8> %va, <vscale x 128 x i1> %m, i32 zeroext %evl) {
589; CHECK-LABEL: vssub_vi_nxv128i8:
590; CHECK:       # %bb.0:
591; CHECK-NEXT:    vsetvli a2, zero, e8, m8, ta, ma
592; CHECK-NEXT:    vmv1r.v v24, v0
593; CHECK-NEXT:    vlm.v v0, (a0)
594; CHECK-NEXT:    csrr a0, vlenb
595; CHECK-NEXT:    slli a0, a0, 3
596; CHECK-NEXT:    sub a2, a1, a0
597; CHECK-NEXT:    sltu a3, a1, a2
598; CHECK-NEXT:    addi a3, a3, -1
599; CHECK-NEXT:    and a3, a3, a2
600; CHECK-NEXT:    li a2, -1
601; CHECK-NEXT:    vsetvli zero, a3, e8, m8, ta, ma
602; CHECK-NEXT:    vssub.vx v16, v16, a2, v0.t
603; CHECK-NEXT:    bltu a1, a0, .LBB50_2
604; CHECK-NEXT:  # %bb.1:
605; CHECK-NEXT:    mv a1, a0
606; CHECK-NEXT:  .LBB50_2:
607; CHECK-NEXT:    vmv1r.v v0, v24
608; CHECK-NEXT:    vsetvli zero, a1, e8, m8, ta, ma
609; CHECK-NEXT:    vssub.vx v8, v8, a2, v0.t
610; CHECK-NEXT:    ret
611  %v = call <vscale x 128 x i8> @llvm.vp.ssub.sat.nxv128i8(<vscale x 128 x i8> %va, <vscale x 128 x i8> splat (i8 -1), <vscale x 128 x i1> %m, i32 %evl)
612  ret <vscale x 128 x i8> %v
613}
614
615define <vscale x 128 x i8> @vssub_vi_nxv128i8_unmasked(<vscale x 128 x i8> %va, i32 zeroext %evl) {
616; CHECK-LABEL: vssub_vi_nxv128i8_unmasked:
617; CHECK:       # %bb.0:
618; CHECK-NEXT:    csrr a1, vlenb
619; CHECK-NEXT:    slli a1, a1, 3
620; CHECK-NEXT:    sub a2, a0, a1
621; CHECK-NEXT:    sltu a3, a0, a2
622; CHECK-NEXT:    addi a3, a3, -1
623; CHECK-NEXT:    and a3, a3, a2
624; CHECK-NEXT:    li a2, -1
625; CHECK-NEXT:    vsetvli zero, a3, e8, m8, ta, ma
626; CHECK-NEXT:    vssub.vx v16, v16, a2
627; CHECK-NEXT:    bltu a0, a1, .LBB51_2
628; CHECK-NEXT:  # %bb.1:
629; CHECK-NEXT:    mv a0, a1
630; CHECK-NEXT:  .LBB51_2:
631; CHECK-NEXT:    vsetvli zero, a0, e8, m8, ta, ma
632; CHECK-NEXT:    vssub.vx v8, v8, a2
633; CHECK-NEXT:    ret
634  %v = call <vscale x 128 x i8> @llvm.vp.ssub.sat.nxv128i8(<vscale x 128 x i8> %va, <vscale x 128 x i8> splat (i8 -1), <vscale x 128 x i1> splat (i1 true), i32 %evl)
635  ret <vscale x 128 x i8> %v
636}
637
638declare <vscale x 1 x i16> @llvm.vp.ssub.sat.nxv1i16(<vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i1>, i32)
639
640define <vscale x 1 x i16> @vssub_vv_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
641; CHECK-LABEL: vssub_vv_nxv1i16:
642; CHECK:       # %bb.0:
643; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma
644; CHECK-NEXT:    vssub.vv v8, v8, v9, v0.t
645; CHECK-NEXT:    ret
646  %v = call <vscale x 1 x i16> @llvm.vp.ssub.sat.nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %b, <vscale x 1 x i1> %m, i32 %evl)
647  ret <vscale x 1 x i16> %v
648}
649
650define <vscale x 1 x i16> @vssub_vv_nxv1i16_unmasked(<vscale x 1 x i16> %va, <vscale x 1 x i16> %b, i32 zeroext %evl) {
651; CHECK-LABEL: vssub_vv_nxv1i16_unmasked:
652; CHECK:       # %bb.0:
653; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma
654; CHECK-NEXT:    vssub.vv v8, v8, v9
655; CHECK-NEXT:    ret
656  %v = call <vscale x 1 x i16> @llvm.vp.ssub.sat.nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %b, <vscale x 1 x i1> splat (i1 true), i32 %evl)
657  ret <vscale x 1 x i16> %v
658}
659
660define <vscale x 1 x i16> @vssub_vx_nxv1i16(<vscale x 1 x i16> %va, i16 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
661; CHECK-LABEL: vssub_vx_nxv1i16:
662; CHECK:       # %bb.0:
663; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
664; CHECK-NEXT:    vssub.vx v8, v8, a0, v0.t
665; CHECK-NEXT:    ret
666  %elt.head = insertelement <vscale x 1 x i16> poison, i16 %b, i32 0
667  %vb = shufflevector <vscale x 1 x i16> %elt.head, <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer
668  %v = call <vscale x 1 x i16> @llvm.vp.ssub.sat.nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %vb, <vscale x 1 x i1> %m, i32 %evl)
669  ret <vscale x 1 x i16> %v
670}
671
672define <vscale x 1 x i16> @vssub_vx_nxv1i16_unmasked(<vscale x 1 x i16> %va, i16 %b, i32 zeroext %evl) {
673; CHECK-LABEL: vssub_vx_nxv1i16_unmasked:
674; CHECK:       # %bb.0:
675; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
676; CHECK-NEXT:    vssub.vx v8, v8, a0
677; CHECK-NEXT:    ret
678  %elt.head = insertelement <vscale x 1 x i16> poison, i16 %b, i32 0
679  %vb = shufflevector <vscale x 1 x i16> %elt.head, <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer
680  %v = call <vscale x 1 x i16> @llvm.vp.ssub.sat.nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %vb, <vscale x 1 x i1> splat (i1 true), i32 %evl)
681  ret <vscale x 1 x i16> %v
682}
683
684define <vscale x 1 x i16> @vssub_vi_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
685; CHECK-LABEL: vssub_vi_nxv1i16:
686; CHECK:       # %bb.0:
687; CHECK-NEXT:    li a1, -1
688; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma
689; CHECK-NEXT:    vssub.vx v8, v8, a1, v0.t
690; CHECK-NEXT:    ret
691  %v = call <vscale x 1 x i16> @llvm.vp.ssub.sat.nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> splat (i16 -1), <vscale x 1 x i1> %m, i32 %evl)
692  ret <vscale x 1 x i16> %v
693}
694
695define <vscale x 1 x i16> @vssub_vi_nxv1i16_unmasked(<vscale x 1 x i16> %va, i32 zeroext %evl) {
696; CHECK-LABEL: vssub_vi_nxv1i16_unmasked:
697; CHECK:       # %bb.0:
698; CHECK-NEXT:    li a1, -1
699; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma
700; CHECK-NEXT:    vssub.vx v8, v8, a1
701; CHECK-NEXT:    ret
702  %v = call <vscale x 1 x i16> @llvm.vp.ssub.sat.nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> splat (i16 -1), <vscale x 1 x i1> splat (i1 true), i32 %evl)
703  ret <vscale x 1 x i16> %v
704}
705
706declare <vscale x 2 x i16> @llvm.vp.ssub.sat.nxv2i16(<vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i1>, i32)
707
708define <vscale x 2 x i16> @vssub_vv_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %b, <vscale x 2 x i1> %m, i32 zeroext %evl) {
709; CHECK-LABEL: vssub_vv_nxv2i16:
710; CHECK:       # %bb.0:
711; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma
712; CHECK-NEXT:    vssub.vv v8, v8, v9, v0.t
713; CHECK-NEXT:    ret
714  %v = call <vscale x 2 x i16> @llvm.vp.ssub.sat.nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %b, <vscale x 2 x i1> %m, i32 %evl)
715  ret <vscale x 2 x i16> %v
716}
717
718define <vscale x 2 x i16> @vssub_vv_nxv2i16_unmasked(<vscale x 2 x i16> %va, <vscale x 2 x i16> %b, i32 zeroext %evl) {
719; CHECK-LABEL: vssub_vv_nxv2i16_unmasked:
720; CHECK:       # %bb.0:
721; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma
722; CHECK-NEXT:    vssub.vv v8, v8, v9
723; CHECK-NEXT:    ret
724  %v = call <vscale x 2 x i16> @llvm.vp.ssub.sat.nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %b, <vscale x 2 x i1> splat (i1 true), i32 %evl)
725  ret <vscale x 2 x i16> %v
726}
727
728define <vscale x 2 x i16> @vssub_vx_nxv2i16(<vscale x 2 x i16> %va, i16 %b, <vscale x 2 x i1> %m, i32 zeroext %evl) {
729; CHECK-LABEL: vssub_vx_nxv2i16:
730; CHECK:       # %bb.0:
731; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
732; CHECK-NEXT:    vssub.vx v8, v8, a0, v0.t
733; CHECK-NEXT:    ret
734  %elt.head = insertelement <vscale x 2 x i16> poison, i16 %b, i32 0
735  %vb = shufflevector <vscale x 2 x i16> %elt.head, <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer
736  %v = call <vscale x 2 x i16> @llvm.vp.ssub.sat.nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %vb, <vscale x 2 x i1> %m, i32 %evl)
737  ret <vscale x 2 x i16> %v
738}
739
740define <vscale x 2 x i16> @vssub_vx_nxv2i16_unmasked(<vscale x 2 x i16> %va, i16 %b, i32 zeroext %evl) {
741; CHECK-LABEL: vssub_vx_nxv2i16_unmasked:
742; CHECK:       # %bb.0:
743; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
744; CHECK-NEXT:    vssub.vx v8, v8, a0
745; CHECK-NEXT:    ret
746  %elt.head = insertelement <vscale x 2 x i16> poison, i16 %b, i32 0
747  %vb = shufflevector <vscale x 2 x i16> %elt.head, <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer
748  %v = call <vscale x 2 x i16> @llvm.vp.ssub.sat.nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %vb, <vscale x 2 x i1> splat (i1 true), i32 %evl)
749  ret <vscale x 2 x i16> %v
750}
751
752define <vscale x 2 x i16> @vssub_vi_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
753; CHECK-LABEL: vssub_vi_nxv2i16:
754; CHECK:       # %bb.0:
755; CHECK-NEXT:    li a1, -1
756; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma
757; CHECK-NEXT:    vssub.vx v8, v8, a1, v0.t
758; CHECK-NEXT:    ret
759  %v = call <vscale x 2 x i16> @llvm.vp.ssub.sat.nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> splat (i16 -1), <vscale x 2 x i1> %m, i32 %evl)
760  ret <vscale x 2 x i16> %v
761}
762
763define <vscale x 2 x i16> @vssub_vi_nxv2i16_unmasked(<vscale x 2 x i16> %va, i32 zeroext %evl) {
764; CHECK-LABEL: vssub_vi_nxv2i16_unmasked:
765; CHECK:       # %bb.0:
766; CHECK-NEXT:    li a1, -1
767; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma
768; CHECK-NEXT:    vssub.vx v8, v8, a1
769; CHECK-NEXT:    ret
770  %v = call <vscale x 2 x i16> @llvm.vp.ssub.sat.nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> splat (i16 -1), <vscale x 2 x i1> splat (i1 true), i32 %evl)
771  ret <vscale x 2 x i16> %v
772}
773
774declare <vscale x 4 x i16> @llvm.vp.ssub.sat.nxv4i16(<vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i1>, i32)
775
776define <vscale x 4 x i16> @vssub_vv_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %b, <vscale x 4 x i1> %m, i32 zeroext %evl) {
777; CHECK-LABEL: vssub_vv_nxv4i16:
778; CHECK:       # %bb.0:
779; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, ma
780; CHECK-NEXT:    vssub.vv v8, v8, v9, v0.t
781; CHECK-NEXT:    ret
782  %v = call <vscale x 4 x i16> @llvm.vp.ssub.sat.nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %b, <vscale x 4 x i1> %m, i32 %evl)
783  ret <vscale x 4 x i16> %v
784}
785
786define <vscale x 4 x i16> @vssub_vv_nxv4i16_unmasked(<vscale x 4 x i16> %va, <vscale x 4 x i16> %b, i32 zeroext %evl) {
787; CHECK-LABEL: vssub_vv_nxv4i16_unmasked:
788; CHECK:       # %bb.0:
789; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, ma
790; CHECK-NEXT:    vssub.vv v8, v8, v9
791; CHECK-NEXT:    ret
792  %v = call <vscale x 4 x i16> @llvm.vp.ssub.sat.nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %b, <vscale x 4 x i1> splat (i1 true), i32 %evl)
793  ret <vscale x 4 x i16> %v
794}
795
796define <vscale x 4 x i16> @vssub_vx_nxv4i16(<vscale x 4 x i16> %va, i16 %b, <vscale x 4 x i1> %m, i32 zeroext %evl) {
797; CHECK-LABEL: vssub_vx_nxv4i16:
798; CHECK:       # %bb.0:
799; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
800; CHECK-NEXT:    vssub.vx v8, v8, a0, v0.t
801; CHECK-NEXT:    ret
802  %elt.head = insertelement <vscale x 4 x i16> poison, i16 %b, i32 0
803  %vb = shufflevector <vscale x 4 x i16> %elt.head, <vscale x 4 x i16> poison, <vscale x 4 x i32> zeroinitializer
804  %v = call <vscale x 4 x i16> @llvm.vp.ssub.sat.nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %vb, <vscale x 4 x i1> %m, i32 %evl)
805  ret <vscale x 4 x i16> %v
806}
807
808define <vscale x 4 x i16> @vssub_vx_nxv4i16_unmasked(<vscale x 4 x i16> %va, i16 %b, i32 zeroext %evl) {
809; CHECK-LABEL: vssub_vx_nxv4i16_unmasked:
810; CHECK:       # %bb.0:
811; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
812; CHECK-NEXT:    vssub.vx v8, v8, a0
813; CHECK-NEXT:    ret
814  %elt.head = insertelement <vscale x 4 x i16> poison, i16 %b, i32 0
815  %vb = shufflevector <vscale x 4 x i16> %elt.head, <vscale x 4 x i16> poison, <vscale x 4 x i32> zeroinitializer
816  %v = call <vscale x 4 x i16> @llvm.vp.ssub.sat.nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %vb, <vscale x 4 x i1> splat (i1 true), i32 %evl)
817  ret <vscale x 4 x i16> %v
818}
819
820define <vscale x 4 x i16> @vssub_vi_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {
821; CHECK-LABEL: vssub_vi_nxv4i16:
822; CHECK:       # %bb.0:
823; CHECK-NEXT:    li a1, -1
824; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, ma
825; CHECK-NEXT:    vssub.vx v8, v8, a1, v0.t
826; CHECK-NEXT:    ret
827  %v = call <vscale x 4 x i16> @llvm.vp.ssub.sat.nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> splat (i16 -1), <vscale x 4 x i1> %m, i32 %evl)
828  ret <vscale x 4 x i16> %v
829}
830
831define <vscale x 4 x i16> @vssub_vi_nxv4i16_unmasked(<vscale x 4 x i16> %va, i32 zeroext %evl) {
832; CHECK-LABEL: vssub_vi_nxv4i16_unmasked:
833; CHECK:       # %bb.0:
834; CHECK-NEXT:    li a1, -1
835; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, ma
836; CHECK-NEXT:    vssub.vx v8, v8, a1
837; CHECK-NEXT:    ret
838  %v = call <vscale x 4 x i16> @llvm.vp.ssub.sat.nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> splat (i16 -1), <vscale x 4 x i1> splat (i1 true), i32 %evl)
839  ret <vscale x 4 x i16> %v
840}
841
842declare <vscale x 8 x i16> @llvm.vp.ssub.sat.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i1>, i32)
843
844define <vscale x 8 x i16> @vssub_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
845; CHECK-LABEL: vssub_vv_nxv8i16:
846; CHECK:       # %bb.0:
847; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, ma
848; CHECK-NEXT:    vssub.vv v8, v8, v10, v0.t
849; CHECK-NEXT:    ret
850  %v = call <vscale x 8 x i16> @llvm.vp.ssub.sat.nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %b, <vscale x 8 x i1> %m, i32 %evl)
851  ret <vscale x 8 x i16> %v
852}
853
854define <vscale x 8 x i16> @vssub_vv_nxv8i16_unmasked(<vscale x 8 x i16> %va, <vscale x 8 x i16> %b, i32 zeroext %evl) {
855; CHECK-LABEL: vssub_vv_nxv8i16_unmasked:
856; CHECK:       # %bb.0:
857; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, ma
858; CHECK-NEXT:    vssub.vv v8, v8, v10
859; CHECK-NEXT:    ret
860  %v = call <vscale x 8 x i16> @llvm.vp.ssub.sat.nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %b, <vscale x 8 x i1> splat (i1 true), i32 %evl)
861  ret <vscale x 8 x i16> %v
862}
863
864define <vscale x 8 x i16> @vssub_vx_nxv8i16(<vscale x 8 x i16> %va, i16 %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
865; CHECK-LABEL: vssub_vx_nxv8i16:
866; CHECK:       # %bb.0:
867; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma
868; CHECK-NEXT:    vssub.vx v8, v8, a0, v0.t
869; CHECK-NEXT:    ret
870  %elt.head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0
871  %vb = shufflevector <vscale x 8 x i16> %elt.head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
872  %v = call <vscale x 8 x i16> @llvm.vp.ssub.sat.nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb, <vscale x 8 x i1> %m, i32 %evl)
873  ret <vscale x 8 x i16> %v
874}
875
876define <vscale x 8 x i16> @vssub_vx_nxv8i16_unmasked(<vscale x 8 x i16> %va, i16 %b, i32 zeroext %evl) {
877; CHECK-LABEL: vssub_vx_nxv8i16_unmasked:
878; CHECK:       # %bb.0:
879; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma
880; CHECK-NEXT:    vssub.vx v8, v8, a0
881; CHECK-NEXT:    ret
882  %elt.head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0
883  %vb = shufflevector <vscale x 8 x i16> %elt.head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
884  %v = call <vscale x 8 x i16> @llvm.vp.ssub.sat.nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb, <vscale x 8 x i1> splat (i1 true), i32 %evl)
885  ret <vscale x 8 x i16> %v
886}
887
888define <vscale x 8 x i16> @vssub_vi_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {
889; CHECK-LABEL: vssub_vi_nxv8i16:
890; CHECK:       # %bb.0:
891; CHECK-NEXT:    li a1, -1
892; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, ma
893; CHECK-NEXT:    vssub.vx v8, v8, a1, v0.t
894; CHECK-NEXT:    ret
895  %v = call <vscale x 8 x i16> @llvm.vp.ssub.sat.nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> splat (i16 -1), <vscale x 8 x i1> %m, i32 %evl)
896  ret <vscale x 8 x i16> %v
897}
898
899define <vscale x 8 x i16> @vssub_vi_nxv8i16_unmasked(<vscale x 8 x i16> %va, i32 zeroext %evl) {
900; CHECK-LABEL: vssub_vi_nxv8i16_unmasked:
901; CHECK:       # %bb.0:
902; CHECK-NEXT:    li a1, -1
903; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, ma
904; CHECK-NEXT:    vssub.vx v8, v8, a1
905; CHECK-NEXT:    ret
906  %v = call <vscale x 8 x i16> @llvm.vp.ssub.sat.nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> splat (i16 -1), <vscale x 8 x i1> splat (i1 true), i32 %evl)
907  ret <vscale x 8 x i16> %v
908}
909
910declare <vscale x 16 x i16> @llvm.vp.ssub.sat.nxv16i16(<vscale x 16 x i16>, <vscale x 16 x i16>, <vscale x 16 x i1>, i32)
911
912define <vscale x 16 x i16> @vssub_vv_nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %b, <vscale x 16 x i1> %m, i32 zeroext %evl) {
913; CHECK-LABEL: vssub_vv_nxv16i16:
914; CHECK:       # %bb.0:
915; CHECK-NEXT:    vsetvli zero, a0, e16, m4, ta, ma
916; CHECK-NEXT:    vssub.vv v8, v8, v12, v0.t
917; CHECK-NEXT:    ret
918  %v = call <vscale x 16 x i16> @llvm.vp.ssub.sat.nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %b, <vscale x 16 x i1> %m, i32 %evl)
919  ret <vscale x 16 x i16> %v
920}
921
922define <vscale x 16 x i16> @vssub_vv_nxv16i16_unmasked(<vscale x 16 x i16> %va, <vscale x 16 x i16> %b, i32 zeroext %evl) {
923; CHECK-LABEL: vssub_vv_nxv16i16_unmasked:
924; CHECK:       # %bb.0:
925; CHECK-NEXT:    vsetvli zero, a0, e16, m4, ta, ma
926; CHECK-NEXT:    vssub.vv v8, v8, v12
927; CHECK-NEXT:    ret
928  %v = call <vscale x 16 x i16> @llvm.vp.ssub.sat.nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %b, <vscale x 16 x i1> splat (i1 true), i32 %evl)
929  ret <vscale x 16 x i16> %v
930}
931
932define <vscale x 16 x i16> @vssub_vx_nxv16i16(<vscale x 16 x i16> %va, i16 %b, <vscale x 16 x i1> %m, i32 zeroext %evl) {
933; CHECK-LABEL: vssub_vx_nxv16i16:
934; CHECK:       # %bb.0:
935; CHECK-NEXT:    vsetvli zero, a1, e16, m4, ta, ma
936; CHECK-NEXT:    vssub.vx v8, v8, a0, v0.t
937; CHECK-NEXT:    ret
938  %elt.head = insertelement <vscale x 16 x i16> poison, i16 %b, i32 0
939  %vb = shufflevector <vscale x 16 x i16> %elt.head, <vscale x 16 x i16> poison, <vscale x 16 x i32> zeroinitializer
940  %v = call <vscale x 16 x i16> @llvm.vp.ssub.sat.nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %vb, <vscale x 16 x i1> %m, i32 %evl)
941  ret <vscale x 16 x i16> %v
942}
943
944define <vscale x 16 x i16> @vssub_vx_nxv16i16_unmasked(<vscale x 16 x i16> %va, i16 %b, i32 zeroext %evl) {
945; CHECK-LABEL: vssub_vx_nxv16i16_unmasked:
946; CHECK:       # %bb.0:
947; CHECK-NEXT:    vsetvli zero, a1, e16, m4, ta, ma
948; CHECK-NEXT:    vssub.vx v8, v8, a0
949; CHECK-NEXT:    ret
950  %elt.head = insertelement <vscale x 16 x i16> poison, i16 %b, i32 0
951  %vb = shufflevector <vscale x 16 x i16> %elt.head, <vscale x 16 x i16> poison, <vscale x 16 x i32> zeroinitializer
952  %v = call <vscale x 16 x i16> @llvm.vp.ssub.sat.nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %vb, <vscale x 16 x i1> splat (i1 true), i32 %evl)
953  ret <vscale x 16 x i16> %v
954}
955
956define <vscale x 16 x i16> @vssub_vi_nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {
957; CHECK-LABEL: vssub_vi_nxv16i16:
958; CHECK:       # %bb.0:
959; CHECK-NEXT:    li a1, -1
960; CHECK-NEXT:    vsetvli zero, a0, e16, m4, ta, ma
961; CHECK-NEXT:    vssub.vx v8, v8, a1, v0.t
962; CHECK-NEXT:    ret
963  %v = call <vscale x 16 x i16> @llvm.vp.ssub.sat.nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> splat (i16 -1), <vscale x 16 x i1> %m, i32 %evl)
964  ret <vscale x 16 x i16> %v
965}
966
967define <vscale x 16 x i16> @vssub_vi_nxv16i16_unmasked(<vscale x 16 x i16> %va, i32 zeroext %evl) {
968; CHECK-LABEL: vssub_vi_nxv16i16_unmasked:
969; CHECK:       # %bb.0:
970; CHECK-NEXT:    li a1, -1
971; CHECK-NEXT:    vsetvli zero, a0, e16, m4, ta, ma
972; CHECK-NEXT:    vssub.vx v8, v8, a1
973; CHECK-NEXT:    ret
974  %v = call <vscale x 16 x i16> @llvm.vp.ssub.sat.nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> splat (i16 -1), <vscale x 16 x i1> splat (i1 true), i32 %evl)
975  ret <vscale x 16 x i16> %v
976}
977
978declare <vscale x 32 x i16> @llvm.vp.ssub.sat.nxv32i16(<vscale x 32 x i16>, <vscale x 32 x i16>, <vscale x 32 x i1>, i32)
979
980define <vscale x 32 x i16> @vssub_vv_nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %b, <vscale x 32 x i1> %m, i32 zeroext %evl) {
981; CHECK-LABEL: vssub_vv_nxv32i16:
982; CHECK:       # %bb.0:
983; CHECK-NEXT:    vsetvli zero, a0, e16, m8, ta, ma
984; CHECK-NEXT:    vssub.vv v8, v8, v16, v0.t
985; CHECK-NEXT:    ret
986  %v = call <vscale x 32 x i16> @llvm.vp.ssub.sat.nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %b, <vscale x 32 x i1> %m, i32 %evl)
987  ret <vscale x 32 x i16> %v
988}
989
990define <vscale x 32 x i16> @vssub_vv_nxv32i16_unmasked(<vscale x 32 x i16> %va, <vscale x 32 x i16> %b, i32 zeroext %evl) {
991; CHECK-LABEL: vssub_vv_nxv32i16_unmasked:
992; CHECK:       # %bb.0:
993; CHECK-NEXT:    vsetvli zero, a0, e16, m8, ta, ma
994; CHECK-NEXT:    vssub.vv v8, v8, v16
995; CHECK-NEXT:    ret
996  %v = call <vscale x 32 x i16> @llvm.vp.ssub.sat.nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %b, <vscale x 32 x i1> splat (i1 true), i32 %evl)
997  ret <vscale x 32 x i16> %v
998}
999
1000define <vscale x 32 x i16> @vssub_vx_nxv32i16(<vscale x 32 x i16> %va, i16 %b, <vscale x 32 x i1> %m, i32 zeroext %evl) {
1001; CHECK-LABEL: vssub_vx_nxv32i16:
1002; CHECK:       # %bb.0:
1003; CHECK-NEXT:    vsetvli zero, a1, e16, m8, ta, ma
1004; CHECK-NEXT:    vssub.vx v8, v8, a0, v0.t
1005; CHECK-NEXT:    ret
1006  %elt.head = insertelement <vscale x 32 x i16> poison, i16 %b, i32 0
1007  %vb = shufflevector <vscale x 32 x i16> %elt.head, <vscale x 32 x i16> poison, <vscale x 32 x i32> zeroinitializer
1008  %v = call <vscale x 32 x i16> @llvm.vp.ssub.sat.nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %vb, <vscale x 32 x i1> %m, i32 %evl)
1009  ret <vscale x 32 x i16> %v
1010}
1011
1012define <vscale x 32 x i16> @vssub_vx_nxv32i16_unmasked(<vscale x 32 x i16> %va, i16 %b, i32 zeroext %evl) {
1013; CHECK-LABEL: vssub_vx_nxv32i16_unmasked:
1014; CHECK:       # %bb.0:
1015; CHECK-NEXT:    vsetvli zero, a1, e16, m8, ta, ma
1016; CHECK-NEXT:    vssub.vx v8, v8, a0
1017; CHECK-NEXT:    ret
1018  %elt.head = insertelement <vscale x 32 x i16> poison, i16 %b, i32 0
1019  %vb = shufflevector <vscale x 32 x i16> %elt.head, <vscale x 32 x i16> poison, <vscale x 32 x i32> zeroinitializer
1020  %v = call <vscale x 32 x i16> @llvm.vp.ssub.sat.nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %vb, <vscale x 32 x i1> splat (i1 true), i32 %evl)
1021  ret <vscale x 32 x i16> %v
1022}
1023
1024define <vscale x 32 x i16> @vssub_vi_nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {
1025; CHECK-LABEL: vssub_vi_nxv32i16:
1026; CHECK:       # %bb.0:
1027; CHECK-NEXT:    li a1, -1
1028; CHECK-NEXT:    vsetvli zero, a0, e16, m8, ta, ma
1029; CHECK-NEXT:    vssub.vx v8, v8, a1, v0.t
1030; CHECK-NEXT:    ret
1031  %v = call <vscale x 32 x i16> @llvm.vp.ssub.sat.nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> splat (i16 -1), <vscale x 32 x i1> %m, i32 %evl)
1032  ret <vscale x 32 x i16> %v
1033}
1034
1035define <vscale x 32 x i16> @vssub_vi_nxv32i16_unmasked(<vscale x 32 x i16> %va, i32 zeroext %evl) {
1036; CHECK-LABEL: vssub_vi_nxv32i16_unmasked:
1037; CHECK:       # %bb.0:
1038; CHECK-NEXT:    li a1, -1
1039; CHECK-NEXT:    vsetvli zero, a0, e16, m8, ta, ma
1040; CHECK-NEXT:    vssub.vx v8, v8, a1
1041; CHECK-NEXT:    ret
1042  %v = call <vscale x 32 x i16> @llvm.vp.ssub.sat.nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> splat (i16 -1), <vscale x 32 x i1> splat (i1 true), i32 %evl)
1043  ret <vscale x 32 x i16> %v
1044}
1045
1046declare <vscale x 1 x i32> @llvm.vp.ssub.sat.nxv1i32(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
1047
1048define <vscale x 1 x i32> @vssub_vv_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
1049; CHECK-LABEL: vssub_vv_nxv1i32:
1050; CHECK:       # %bb.0:
1051; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma
1052; CHECK-NEXT:    vssub.vv v8, v8, v9, v0.t
1053; CHECK-NEXT:    ret
1054  %v = call <vscale x 1 x i32> @llvm.vp.ssub.sat.nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %b, <vscale x 1 x i1> %m, i32 %evl)
1055  ret <vscale x 1 x i32> %v
1056}
1057
1058define <vscale x 1 x i32> @vssub_vv_nxv1i32_unmasked(<vscale x 1 x i32> %va, <vscale x 1 x i32> %b, i32 zeroext %evl) {
1059; CHECK-LABEL: vssub_vv_nxv1i32_unmasked:
1060; CHECK:       # %bb.0:
1061; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma
1062; CHECK-NEXT:    vssub.vv v8, v8, v9
1063; CHECK-NEXT:    ret
1064  %v = call <vscale x 1 x i32> @llvm.vp.ssub.sat.nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %b, <vscale x 1 x i1> splat (i1 true), i32 %evl)
1065  ret <vscale x 1 x i32> %v
1066}
1067
1068define <vscale x 1 x i32> @vssub_vx_nxv1i32(<vscale x 1 x i32> %va, i32 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
1069; CHECK-LABEL: vssub_vx_nxv1i32:
1070; CHECK:       # %bb.0:
1071; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma
1072; CHECK-NEXT:    vssub.vx v8, v8, a0, v0.t
1073; CHECK-NEXT:    ret
1074  %elt.head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 0
1075  %vb = shufflevector <vscale x 1 x i32> %elt.head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer
1076  %v = call <vscale x 1 x i32> @llvm.vp.ssub.sat.nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb, <vscale x 1 x i1> %m, i32 %evl)
1077  ret <vscale x 1 x i32> %v
1078}
1079
1080define <vscale x 1 x i32> @vssub_vx_nxv1i32_unmasked(<vscale x 1 x i32> %va, i32 %b, i32 zeroext %evl) {
1081; CHECK-LABEL: vssub_vx_nxv1i32_unmasked:
1082; CHECK:       # %bb.0:
1083; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma
1084; CHECK-NEXT:    vssub.vx v8, v8, a0
1085; CHECK-NEXT:    ret
1086  %elt.head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 0
1087  %vb = shufflevector <vscale x 1 x i32> %elt.head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer
1088  %v = call <vscale x 1 x i32> @llvm.vp.ssub.sat.nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb, <vscale x 1 x i1> splat (i1 true), i32 %evl)
1089  ret <vscale x 1 x i32> %v
1090}
1091
1092define <vscale x 1 x i32> @vssub_vi_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
1093; CHECK-LABEL: vssub_vi_nxv1i32:
1094; CHECK:       # %bb.0:
1095; CHECK-NEXT:    li a1, -1
1096; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma
1097; CHECK-NEXT:    vssub.vx v8, v8, a1, v0.t
1098; CHECK-NEXT:    ret
1099  %v = call <vscale x 1 x i32> @llvm.vp.ssub.sat.nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> splat (i32 -1), <vscale x 1 x i1> %m, i32 %evl)
1100  ret <vscale x 1 x i32> %v
1101}
1102
1103define <vscale x 1 x i32> @vssub_vi_nxv1i32_unmasked(<vscale x 1 x i32> %va, i32 zeroext %evl) {
1104; CHECK-LABEL: vssub_vi_nxv1i32_unmasked:
1105; CHECK:       # %bb.0:
1106; CHECK-NEXT:    li a1, -1
1107; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma
1108; CHECK-NEXT:    vssub.vx v8, v8, a1
1109; CHECK-NEXT:    ret
1110  %v = call <vscale x 1 x i32> @llvm.vp.ssub.sat.nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> splat (i32 -1), <vscale x 1 x i1> splat (i1 true), i32 %evl)
1111  ret <vscale x 1 x i32> %v
1112}
1113
1114declare <vscale x 2 x i32> @llvm.vp.ssub.sat.nxv2i32(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i1>, i32)
1115
1116define <vscale x 2 x i32> @vssub_vv_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %b, <vscale x 2 x i1> %m, i32 zeroext %evl) {
1117; CHECK-LABEL: vssub_vv_nxv2i32:
1118; CHECK:       # %bb.0:
1119; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma
1120; CHECK-NEXT:    vssub.vv v8, v8, v9, v0.t
1121; CHECK-NEXT:    ret
1122  %v = call <vscale x 2 x i32> @llvm.vp.ssub.sat.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %b, <vscale x 2 x i1> %m, i32 %evl)
1123  ret <vscale x 2 x i32> %v
1124}
1125
1126define <vscale x 2 x i32> @vssub_vv_nxv2i32_unmasked(<vscale x 2 x i32> %va, <vscale x 2 x i32> %b, i32 zeroext %evl) {
1127; CHECK-LABEL: vssub_vv_nxv2i32_unmasked:
1128; CHECK:       # %bb.0:
1129; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma
1130; CHECK-NEXT:    vssub.vv v8, v8, v9
1131; CHECK-NEXT:    ret
1132  %v = call <vscale x 2 x i32> @llvm.vp.ssub.sat.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %b, <vscale x 2 x i1> splat (i1 true), i32 %evl)
1133  ret <vscale x 2 x i32> %v
1134}
1135
1136define <vscale x 2 x i32> @vssub_vx_nxv2i32(<vscale x 2 x i32> %va, i32 %b, <vscale x 2 x i1> %m, i32 zeroext %evl) {
1137; CHECK-LABEL: vssub_vx_nxv2i32:
1138; CHECK:       # %bb.0:
1139; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma
1140; CHECK-NEXT:    vssub.vx v8, v8, a0, v0.t
1141; CHECK-NEXT:    ret
1142  %elt.head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0
1143  %vb = shufflevector <vscale x 2 x i32> %elt.head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer
1144  %v = call <vscale x 2 x i32> @llvm.vp.ssub.sat.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb, <vscale x 2 x i1> %m, i32 %evl)
1145  ret <vscale x 2 x i32> %v
1146}
1147
1148define <vscale x 2 x i32> @vssub_vx_nxv2i32_unmasked(<vscale x 2 x i32> %va, i32 %b, i32 zeroext %evl) {
1149; CHECK-LABEL: vssub_vx_nxv2i32_unmasked:
1150; CHECK:       # %bb.0:
1151; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma
1152; CHECK-NEXT:    vssub.vx v8, v8, a0
1153; CHECK-NEXT:    ret
1154  %elt.head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0
1155  %vb = shufflevector <vscale x 2 x i32> %elt.head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer
1156  %v = call <vscale x 2 x i32> @llvm.vp.ssub.sat.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb, <vscale x 2 x i1> splat (i1 true), i32 %evl)
1157  ret <vscale x 2 x i32> %v
1158}
1159
1160define <vscale x 2 x i32> @vssub_vi_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
1161; CHECK-LABEL: vssub_vi_nxv2i32:
1162; CHECK:       # %bb.0:
1163; CHECK-NEXT:    li a1, -1
1164; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma
1165; CHECK-NEXT:    vssub.vx v8, v8, a1, v0.t
1166; CHECK-NEXT:    ret
1167  %v = call <vscale x 2 x i32> @llvm.vp.ssub.sat.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> splat (i32 -1), <vscale x 2 x i1> %m, i32 %evl)
1168  ret <vscale x 2 x i32> %v
1169}
1170
1171define <vscale x 2 x i32> @vssub_vi_nxv2i32_unmasked(<vscale x 2 x i32> %va, i32 zeroext %evl) {
1172; CHECK-LABEL: vssub_vi_nxv2i32_unmasked:
1173; CHECK:       # %bb.0:
1174; CHECK-NEXT:    li a1, -1
1175; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma
1176; CHECK-NEXT:    vssub.vx v8, v8, a1
1177; CHECK-NEXT:    ret
1178  %v = call <vscale x 2 x i32> @llvm.vp.ssub.sat.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> splat (i32 -1), <vscale x 2 x i1> splat (i1 true), i32 %evl)
1179  ret <vscale x 2 x i32> %v
1180}
1181
1182declare <vscale x 4 x i32> @llvm.vp.ssub.sat.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i1>, i32)
1183
1184define <vscale x 4 x i32> @vssub_vv_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %b, <vscale x 4 x i1> %m, i32 zeroext %evl) {
1185; CHECK-LABEL: vssub_vv_nxv4i32:
1186; CHECK:       # %bb.0:
1187; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma
1188; CHECK-NEXT:    vssub.vv v8, v8, v10, v0.t
1189; CHECK-NEXT:    ret
1190  %v = call <vscale x 4 x i32> @llvm.vp.ssub.sat.nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %b, <vscale x 4 x i1> %m, i32 %evl)
1191  ret <vscale x 4 x i32> %v
1192}
1193
1194define <vscale x 4 x i32> @vssub_vv_nxv4i32_unmasked(<vscale x 4 x i32> %va, <vscale x 4 x i32> %b, i32 zeroext %evl) {
1195; CHECK-LABEL: vssub_vv_nxv4i32_unmasked:
1196; CHECK:       # %bb.0:
1197; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma
1198; CHECK-NEXT:    vssub.vv v8, v8, v10
1199; CHECK-NEXT:    ret
1200  %v = call <vscale x 4 x i32> @llvm.vp.ssub.sat.nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %b, <vscale x 4 x i1> splat (i1 true), i32 %evl)
1201  ret <vscale x 4 x i32> %v
1202}
1203
1204define <vscale x 4 x i32> @vssub_vx_nxv4i32(<vscale x 4 x i32> %va, i32 %b, <vscale x 4 x i1> %m, i32 zeroext %evl) {
1205; CHECK-LABEL: vssub_vx_nxv4i32:
1206; CHECK:       # %bb.0:
1207; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma
1208; CHECK-NEXT:    vssub.vx v8, v8, a0, v0.t
1209; CHECK-NEXT:    ret
1210  %elt.head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0
1211  %vb = shufflevector <vscale x 4 x i32> %elt.head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
1212  %v = call <vscale x 4 x i32> @llvm.vp.ssub.sat.nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb, <vscale x 4 x i1> %m, i32 %evl)
1213  ret <vscale x 4 x i32> %v
1214}
1215
1216define <vscale x 4 x i32> @vssub_vx_nxv4i32_unmasked(<vscale x 4 x i32> %va, i32 %b, i32 zeroext %evl) {
1217; CHECK-LABEL: vssub_vx_nxv4i32_unmasked:
1218; CHECK:       # %bb.0:
1219; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma
1220; CHECK-NEXT:    vssub.vx v8, v8, a0
1221; CHECK-NEXT:    ret
1222  %elt.head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0
1223  %vb = shufflevector <vscale x 4 x i32> %elt.head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
1224  %v = call <vscale x 4 x i32> @llvm.vp.ssub.sat.nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb, <vscale x 4 x i1> splat (i1 true), i32 %evl)
1225  ret <vscale x 4 x i32> %v
1226}
1227
1228define <vscale x 4 x i32> @vssub_vi_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {
1229; CHECK-LABEL: vssub_vi_nxv4i32:
1230; CHECK:       # %bb.0:
1231; CHECK-NEXT:    li a1, -1
1232; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma
1233; CHECK-NEXT:    vssub.vx v8, v8, a1, v0.t
1234; CHECK-NEXT:    ret
1235  %v = call <vscale x 4 x i32> @llvm.vp.ssub.sat.nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> splat (i32 -1), <vscale x 4 x i1> %m, i32 %evl)
1236  ret <vscale x 4 x i32> %v
1237}
1238
1239define <vscale x 4 x i32> @vssub_vi_nxv4i32_unmasked(<vscale x 4 x i32> %va, i32 zeroext %evl) {
1240; CHECK-LABEL: vssub_vi_nxv4i32_unmasked:
1241; CHECK:       # %bb.0:
1242; CHECK-NEXT:    li a1, -1
1243; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma
1244; CHECK-NEXT:    vssub.vx v8, v8, a1
1245; CHECK-NEXT:    ret
1246  %v = call <vscale x 4 x i32> @llvm.vp.ssub.sat.nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> splat (i32 -1), <vscale x 4 x i1> splat (i1 true), i32 %evl)
1247  ret <vscale x 4 x i32> %v
1248}
1249
1250declare <vscale x 8 x i32> @llvm.vp.ssub.sat.nxv8i32(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i1>, i32)
1251
1252define <vscale x 8 x i32> @vssub_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
1253; CHECK-LABEL: vssub_vv_nxv8i32:
1254; CHECK:       # %bb.0:
1255; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, ma
1256; CHECK-NEXT:    vssub.vv v8, v8, v12, v0.t
1257; CHECK-NEXT:    ret
1258  %v = call <vscale x 8 x i32> @llvm.vp.ssub.sat.nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %b, <vscale x 8 x i1> %m, i32 %evl)
1259  ret <vscale x 8 x i32> %v
1260}
1261
1262define <vscale x 8 x i32> @vssub_vv_nxv8i32_unmasked(<vscale x 8 x i32> %va, <vscale x 8 x i32> %b, i32 zeroext %evl) {
1263; CHECK-LABEL: vssub_vv_nxv8i32_unmasked:
1264; CHECK:       # %bb.0:
1265; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, ma
1266; CHECK-NEXT:    vssub.vv v8, v8, v12
1267; CHECK-NEXT:    ret
1268  %v = call <vscale x 8 x i32> @llvm.vp.ssub.sat.nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %b, <vscale x 8 x i1> splat (i1 true), i32 %evl)
1269  ret <vscale x 8 x i32> %v
1270}
1271
1272define <vscale x 8 x i32> @vssub_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
1273; CHECK-LABEL: vssub_vx_nxv8i32:
1274; CHECK:       # %bb.0:
1275; CHECK-NEXT:    vsetvli zero, a1, e32, m4, ta, ma
1276; CHECK-NEXT:    vssub.vx v8, v8, a0, v0.t
1277; CHECK-NEXT:    ret
1278  %elt.head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
1279  %vb = shufflevector <vscale x 8 x i32> %elt.head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
1280  %v = call <vscale x 8 x i32> @llvm.vp.ssub.sat.nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, <vscale x 8 x i1> %m, i32 %evl)
1281  ret <vscale x 8 x i32> %v
1282}
1283
1284define <vscale x 8 x i32> @vssub_vx_nxv8i32_unmasked(<vscale x 8 x i32> %va, i32 %b, i32 zeroext %evl) {
1285; CHECK-LABEL: vssub_vx_nxv8i32_unmasked:
1286; CHECK:       # %bb.0:
1287; CHECK-NEXT:    vsetvli zero, a1, e32, m4, ta, ma
1288; CHECK-NEXT:    vssub.vx v8, v8, a0
1289; CHECK-NEXT:    ret
1290  %elt.head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
1291  %vb = shufflevector <vscale x 8 x i32> %elt.head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
1292  %v = call <vscale x 8 x i32> @llvm.vp.ssub.sat.nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, <vscale x 8 x i1> splat (i1 true), i32 %evl)
1293  ret <vscale x 8 x i32> %v
1294}
1295
1296define <vscale x 8 x i32> @vssub_vi_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {
1297; CHECK-LABEL: vssub_vi_nxv8i32:
1298; CHECK:       # %bb.0:
1299; CHECK-NEXT:    li a1, -1
1300; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, ma
1301; CHECK-NEXT:    vssub.vx v8, v8, a1, v0.t
1302; CHECK-NEXT:    ret
1303  %v = call <vscale x 8 x i32> @llvm.vp.ssub.sat.nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> splat (i32 -1), <vscale x 8 x i1> %m, i32 %evl)
1304  ret <vscale x 8 x i32> %v
1305}
1306
1307define <vscale x 8 x i32> @vssub_vi_nxv8i32_unmasked(<vscale x 8 x i32> %va, i32 zeroext %evl) {
1308; CHECK-LABEL: vssub_vi_nxv8i32_unmasked:
1309; CHECK:       # %bb.0:
1310; CHECK-NEXT:    li a1, -1
1311; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, ma
1312; CHECK-NEXT:    vssub.vx v8, v8, a1
1313; CHECK-NEXT:    ret
1314  %v = call <vscale x 8 x i32> @llvm.vp.ssub.sat.nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> splat (i32 -1), <vscale x 8 x i1> splat (i1 true), i32 %evl)
1315  ret <vscale x 8 x i32> %v
1316}
1317
1318declare <vscale x 16 x i32> @llvm.vp.ssub.sat.nxv16i32(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i1>, i32)
1319
1320define <vscale x 16 x i32> @vssub_vv_nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %b, <vscale x 16 x i1> %m, i32 zeroext %evl) {
1321; CHECK-LABEL: vssub_vv_nxv16i32:
1322; CHECK:       # %bb.0:
1323; CHECK-NEXT:    vsetvli zero, a0, e32, m8, ta, ma
1324; CHECK-NEXT:    vssub.vv v8, v8, v16, v0.t
1325; CHECK-NEXT:    ret
1326  %v = call <vscale x 16 x i32> @llvm.vp.ssub.sat.nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %b, <vscale x 16 x i1> %m, i32 %evl)
1327  ret <vscale x 16 x i32> %v
1328}
1329
1330define <vscale x 16 x i32> @vssub_vv_nxv16i32_unmasked(<vscale x 16 x i32> %va, <vscale x 16 x i32> %b, i32 zeroext %evl) {
1331; CHECK-LABEL: vssub_vv_nxv16i32_unmasked:
1332; CHECK:       # %bb.0:
1333; CHECK-NEXT:    vsetvli zero, a0, e32, m8, ta, ma
1334; CHECK-NEXT:    vssub.vv v8, v8, v16
1335; CHECK-NEXT:    ret
1336  %v = call <vscale x 16 x i32> @llvm.vp.ssub.sat.nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %b, <vscale x 16 x i1> splat (i1 true), i32 %evl)
1337  ret <vscale x 16 x i32> %v
1338}
1339
1340define <vscale x 16 x i32> @vssub_vx_nxv16i32(<vscale x 16 x i32> %va, i32 %b, <vscale x 16 x i1> %m, i32 zeroext %evl) {
1341; CHECK-LABEL: vssub_vx_nxv16i32:
1342; CHECK:       # %bb.0:
1343; CHECK-NEXT:    vsetvli zero, a1, e32, m8, ta, ma
1344; CHECK-NEXT:    vssub.vx v8, v8, a0, v0.t
1345; CHECK-NEXT:    ret
1346  %elt.head = insertelement <vscale x 16 x i32> poison, i32 %b, i32 0
1347  %vb = shufflevector <vscale x 16 x i32> %elt.head, <vscale x 16 x i32> poison, <vscale x 16 x i32> zeroinitializer
1348  %v = call <vscale x 16 x i32> @llvm.vp.ssub.sat.nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %vb, <vscale x 16 x i1> %m, i32 %evl)
1349  ret <vscale x 16 x i32> %v
1350}
1351
1352define <vscale x 16 x i32> @vssub_vx_nxv16i32_unmasked(<vscale x 16 x i32> %va, i32 %b, i32 zeroext %evl) {
1353; CHECK-LABEL: vssub_vx_nxv16i32_unmasked:
1354; CHECK:       # %bb.0:
1355; CHECK-NEXT:    vsetvli zero, a1, e32, m8, ta, ma
1356; CHECK-NEXT:    vssub.vx v8, v8, a0
1357; CHECK-NEXT:    ret
1358  %elt.head = insertelement <vscale x 16 x i32> poison, i32 %b, i32 0
1359  %vb = shufflevector <vscale x 16 x i32> %elt.head, <vscale x 16 x i32> poison, <vscale x 16 x i32> zeroinitializer
1360  %v = call <vscale x 16 x i32> @llvm.vp.ssub.sat.nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %vb, <vscale x 16 x i1> splat (i1 true), i32 %evl)
1361  ret <vscale x 16 x i32> %v
1362}
1363
1364define <vscale x 16 x i32> @vssub_vi_nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {
1365; CHECK-LABEL: vssub_vi_nxv16i32:
1366; CHECK:       # %bb.0:
1367; CHECK-NEXT:    li a1, -1
1368; CHECK-NEXT:    vsetvli zero, a0, e32, m8, ta, ma
1369; CHECK-NEXT:    vssub.vx v8, v8, a1, v0.t
1370; CHECK-NEXT:    ret
1371  %v = call <vscale x 16 x i32> @llvm.vp.ssub.sat.nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> splat (i32 -1), <vscale x 16 x i1> %m, i32 %evl)
1372  ret <vscale x 16 x i32> %v
1373}
1374
1375define <vscale x 16 x i32> @vssub_vi_nxv16i32_unmasked(<vscale x 16 x i32> %va, i32 zeroext %evl) {
1376; CHECK-LABEL: vssub_vi_nxv16i32_unmasked:
1377; CHECK:       # %bb.0:
1378; CHECK-NEXT:    li a1, -1
1379; CHECK-NEXT:    vsetvli zero, a0, e32, m8, ta, ma
1380; CHECK-NEXT:    vssub.vx v8, v8, a1
1381; CHECK-NEXT:    ret
1382  %v = call <vscale x 16 x i32> @llvm.vp.ssub.sat.nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> splat (i32 -1), <vscale x 16 x i1> splat (i1 true), i32 %evl)
1383  ret <vscale x 16 x i32> %v
1384}
1385
1386; Test that split-legalization works then the mask needs manual splitting.
1387
1388declare <vscale x 32 x i32> @llvm.vp.ssub.sat.nxv32i32(<vscale x 32 x i32>, <vscale x 32 x i32>, <vscale x 32 x i1>, i32)
1389
1390define <vscale x 32 x i32> @vssub_vi_nxv32i32(<vscale x 32 x i32> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {
1391; CHECK-LABEL: vssub_vi_nxv32i32:
1392; CHECK:       # %bb.0:
1393; CHECK-NEXT:    vsetvli a1, zero, e8, mf2, ta, ma
1394; CHECK-NEXT:    vmv1r.v v24, v0
1395; CHECK-NEXT:    csrr a1, vlenb
1396; CHECK-NEXT:    srli a2, a1, 2
1397; CHECK-NEXT:    slli a1, a1, 1
1398; CHECK-NEXT:    vslidedown.vx v0, v0, a2
1399; CHECK-NEXT:    sub a2, a0, a1
1400; CHECK-NEXT:    sltu a3, a0, a2
1401; CHECK-NEXT:    addi a3, a3, -1
1402; CHECK-NEXT:    and a3, a3, a2
1403; CHECK-NEXT:    li a2, -1
1404; CHECK-NEXT:    vsetvli zero, a3, e32, m8, ta, ma
1405; CHECK-NEXT:    vssub.vx v16, v16, a2, v0.t
1406; CHECK-NEXT:    bltu a0, a1, .LBB118_2
1407; CHECK-NEXT:  # %bb.1:
1408; CHECK-NEXT:    mv a0, a1
1409; CHECK-NEXT:  .LBB118_2:
1410; CHECK-NEXT:    vmv1r.v v0, v24
1411; CHECK-NEXT:    vsetvli zero, a0, e32, m8, ta, ma
1412; CHECK-NEXT:    vssub.vx v8, v8, a2, v0.t
1413; CHECK-NEXT:    ret
1414  %v = call <vscale x 32 x i32> @llvm.vp.ssub.sat.nxv32i32(<vscale x 32 x i32> %va, <vscale x 32 x i32> splat (i32 -1), <vscale x 32 x i1> %m, i32 %evl)
1415  ret <vscale x 32 x i32> %v
1416}
1417
1418define <vscale x 32 x i32> @vssub_vi_nxv32i32_unmasked(<vscale x 32 x i32> %va, i32 zeroext %evl) {
1419; CHECK-LABEL: vssub_vi_nxv32i32_unmasked:
1420; CHECK:       # %bb.0:
1421; CHECK-NEXT:    csrr a1, vlenb
1422; CHECK-NEXT:    slli a1, a1, 1
1423; CHECK-NEXT:    sub a2, a0, a1
1424; CHECK-NEXT:    sltu a3, a0, a2
1425; CHECK-NEXT:    addi a3, a3, -1
1426; CHECK-NEXT:    and a3, a3, a2
1427; CHECK-NEXT:    li a2, -1
1428; CHECK-NEXT:    vsetvli zero, a3, e32, m8, ta, ma
1429; CHECK-NEXT:    vssub.vx v16, v16, a2
1430; CHECK-NEXT:    bltu a0, a1, .LBB119_2
1431; CHECK-NEXT:  # %bb.1:
1432; CHECK-NEXT:    mv a0, a1
1433; CHECK-NEXT:  .LBB119_2:
1434; CHECK-NEXT:    vsetvli zero, a0, e32, m8, ta, ma
1435; CHECK-NEXT:    vssub.vx v8, v8, a2
1436; CHECK-NEXT:    ret
1437  %v = call <vscale x 32 x i32> @llvm.vp.ssub.sat.nxv32i32(<vscale x 32 x i32> %va, <vscale x 32 x i32> splat (i32 -1), <vscale x 32 x i1> splat (i1 true), i32 %evl)
1438  ret <vscale x 32 x i32> %v
1439}
1440
1441declare <vscale x 1 x i64> @llvm.vp.ssub.sat.nxv1i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i1>, i32)
1442
1443define <vscale x 1 x i64> @vssub_vv_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
1444; CHECK-LABEL: vssub_vv_nxv1i64:
1445; CHECK:       # %bb.0:
1446; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, ma
1447; CHECK-NEXT:    vssub.vv v8, v8, v9, v0.t
1448; CHECK-NEXT:    ret
1449  %v = call <vscale x 1 x i64> @llvm.vp.ssub.sat.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %b, <vscale x 1 x i1> %m, i32 %evl)
1450  ret <vscale x 1 x i64> %v
1451}
1452
1453define <vscale x 1 x i64> @vssub_vv_nxv1i64_unmasked(<vscale x 1 x i64> %va, <vscale x 1 x i64> %b, i32 zeroext %evl) {
1454; CHECK-LABEL: vssub_vv_nxv1i64_unmasked:
1455; CHECK:       # %bb.0:
1456; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, ma
1457; CHECK-NEXT:    vssub.vv v8, v8, v9
1458; CHECK-NEXT:    ret
1459  %v = call <vscale x 1 x i64> @llvm.vp.ssub.sat.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %b, <vscale x 1 x i1> splat (i1 true), i32 %evl)
1460  ret <vscale x 1 x i64> %v
1461}
1462
1463define <vscale x 1 x i64> @vssub_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
1464; RV32-LABEL: vssub_vx_nxv1i64:
1465; RV32:       # %bb.0:
1466; RV32-NEXT:    addi sp, sp, -16
1467; RV32-NEXT:    .cfi_def_cfa_offset 16
1468; RV32-NEXT:    sw a0, 8(sp)
1469; RV32-NEXT:    sw a1, 12(sp)
1470; RV32-NEXT:    addi a0, sp, 8
1471; RV32-NEXT:    vsetvli zero, a2, e64, m1, ta, ma
1472; RV32-NEXT:    vlse64.v v9, (a0), zero
1473; RV32-NEXT:    vssub.vv v8, v8, v9, v0.t
1474; RV32-NEXT:    addi sp, sp, 16
1475; RV32-NEXT:    .cfi_def_cfa_offset 0
1476; RV32-NEXT:    ret
1477;
1478; RV64-LABEL: vssub_vx_nxv1i64:
1479; RV64:       # %bb.0:
1480; RV64-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
1481; RV64-NEXT:    vssub.vx v8, v8, a0, v0.t
1482; RV64-NEXT:    ret
1483  %elt.head = insertelement <vscale x 1 x i64> poison, i64 %b, i32 0
1484  %vb = shufflevector <vscale x 1 x i64> %elt.head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer
1485  %v = call <vscale x 1 x i64> @llvm.vp.ssub.sat.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb, <vscale x 1 x i1> %m, i32 %evl)
1486  ret <vscale x 1 x i64> %v
1487}
1488
1489define <vscale x 1 x i64> @vssub_vx_nxv1i64_unmasked(<vscale x 1 x i64> %va, i64 %b, i32 zeroext %evl) {
1490; RV32-LABEL: vssub_vx_nxv1i64_unmasked:
1491; RV32:       # %bb.0:
1492; RV32-NEXT:    addi sp, sp, -16
1493; RV32-NEXT:    .cfi_def_cfa_offset 16
1494; RV32-NEXT:    sw a0, 8(sp)
1495; RV32-NEXT:    sw a1, 12(sp)
1496; RV32-NEXT:    addi a0, sp, 8
1497; RV32-NEXT:    vsetvli zero, a2, e64, m1, ta, ma
1498; RV32-NEXT:    vlse64.v v9, (a0), zero
1499; RV32-NEXT:    vssub.vv v8, v8, v9
1500; RV32-NEXT:    addi sp, sp, 16
1501; RV32-NEXT:    .cfi_def_cfa_offset 0
1502; RV32-NEXT:    ret
1503;
1504; RV64-LABEL: vssub_vx_nxv1i64_unmasked:
1505; RV64:       # %bb.0:
1506; RV64-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
1507; RV64-NEXT:    vssub.vx v8, v8, a0
1508; RV64-NEXT:    ret
1509  %elt.head = insertelement <vscale x 1 x i64> poison, i64 %b, i32 0
1510  %vb = shufflevector <vscale x 1 x i64> %elt.head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer
1511  %v = call <vscale x 1 x i64> @llvm.vp.ssub.sat.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb, <vscale x 1 x i1> splat (i1 true), i32 %evl)
1512  ret <vscale x 1 x i64> %v
1513}
1514
1515define <vscale x 1 x i64> @vssub_vi_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
1516; CHECK-LABEL: vssub_vi_nxv1i64:
1517; CHECK:       # %bb.0:
1518; CHECK-NEXT:    li a1, -1
1519; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, ma
1520; CHECK-NEXT:    vssub.vx v8, v8, a1, v0.t
1521; CHECK-NEXT:    ret
1522  %v = call <vscale x 1 x i64> @llvm.vp.ssub.sat.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> splat (i64 -1), <vscale x 1 x i1> %m, i32 %evl)
1523  ret <vscale x 1 x i64> %v
1524}
1525
1526define <vscale x 1 x i64> @vssub_vi_nxv1i64_unmasked(<vscale x 1 x i64> %va, i32 zeroext %evl) {
1527; CHECK-LABEL: vssub_vi_nxv1i64_unmasked:
1528; CHECK:       # %bb.0:
1529; CHECK-NEXT:    li a1, -1
1530; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, ma
1531; CHECK-NEXT:    vssub.vx v8, v8, a1
1532; CHECK-NEXT:    ret
1533  %v = call <vscale x 1 x i64> @llvm.vp.ssub.sat.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> splat (i64 -1), <vscale x 1 x i1> splat (i1 true), i32 %evl)
1534  ret <vscale x 1 x i64> %v
1535}
1536
1537declare <vscale x 2 x i64> @llvm.vp.ssub.sat.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i1>, i32)
1538
1539define <vscale x 2 x i64> @vssub_vv_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %b, <vscale x 2 x i1> %m, i32 zeroext %evl) {
1540; CHECK-LABEL: vssub_vv_nxv2i64:
1541; CHECK:       # %bb.0:
1542; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, ma
1543; CHECK-NEXT:    vssub.vv v8, v8, v10, v0.t
1544; CHECK-NEXT:    ret
1545  %v = call <vscale x 2 x i64> @llvm.vp.ssub.sat.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %b, <vscale x 2 x i1> %m, i32 %evl)
1546  ret <vscale x 2 x i64> %v
1547}
1548
1549define <vscale x 2 x i64> @vssub_vv_nxv2i64_unmasked(<vscale x 2 x i64> %va, <vscale x 2 x i64> %b, i32 zeroext %evl) {
1550; CHECK-LABEL: vssub_vv_nxv2i64_unmasked:
1551; CHECK:       # %bb.0:
1552; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, ma
1553; CHECK-NEXT:    vssub.vv v8, v8, v10
1554; CHECK-NEXT:    ret
1555  %v = call <vscale x 2 x i64> @llvm.vp.ssub.sat.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %b, <vscale x 2 x i1> splat (i1 true), i32 %evl)
1556  ret <vscale x 2 x i64> %v
1557}
1558
1559define <vscale x 2 x i64> @vssub_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b, <vscale x 2 x i1> %m, i32 zeroext %evl) {
1560; RV32-LABEL: vssub_vx_nxv2i64:
1561; RV32:       # %bb.0:
1562; RV32-NEXT:    addi sp, sp, -16
1563; RV32-NEXT:    .cfi_def_cfa_offset 16
1564; RV32-NEXT:    sw a0, 8(sp)
1565; RV32-NEXT:    sw a1, 12(sp)
1566; RV32-NEXT:    addi a0, sp, 8
1567; RV32-NEXT:    vsetvli zero, a2, e64, m2, ta, ma
1568; RV32-NEXT:    vlse64.v v10, (a0), zero
1569; RV32-NEXT:    vssub.vv v8, v8, v10, v0.t
1570; RV32-NEXT:    addi sp, sp, 16
1571; RV32-NEXT:    .cfi_def_cfa_offset 0
1572; RV32-NEXT:    ret
1573;
1574; RV64-LABEL: vssub_vx_nxv2i64:
1575; RV64:       # %bb.0:
1576; RV64-NEXT:    vsetvli zero, a1, e64, m2, ta, ma
1577; RV64-NEXT:    vssub.vx v8, v8, a0, v0.t
1578; RV64-NEXT:    ret
1579  %elt.head = insertelement <vscale x 2 x i64> poison, i64 %b, i32 0
1580  %vb = shufflevector <vscale x 2 x i64> %elt.head, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
1581  %v = call <vscale x 2 x i64> @llvm.vp.ssub.sat.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb, <vscale x 2 x i1> %m, i32 %evl)
1582  ret <vscale x 2 x i64> %v
1583}
1584
1585define <vscale x 2 x i64> @vssub_vx_nxv2i64_unmasked(<vscale x 2 x i64> %va, i64 %b, i32 zeroext %evl) {
1586; RV32-LABEL: vssub_vx_nxv2i64_unmasked:
1587; RV32:       # %bb.0:
1588; RV32-NEXT:    addi sp, sp, -16
1589; RV32-NEXT:    .cfi_def_cfa_offset 16
1590; RV32-NEXT:    sw a0, 8(sp)
1591; RV32-NEXT:    sw a1, 12(sp)
1592; RV32-NEXT:    addi a0, sp, 8
1593; RV32-NEXT:    vsetvli zero, a2, e64, m2, ta, ma
1594; RV32-NEXT:    vlse64.v v10, (a0), zero
1595; RV32-NEXT:    vssub.vv v8, v8, v10
1596; RV32-NEXT:    addi sp, sp, 16
1597; RV32-NEXT:    .cfi_def_cfa_offset 0
1598; RV32-NEXT:    ret
1599;
1600; RV64-LABEL: vssub_vx_nxv2i64_unmasked:
1601; RV64:       # %bb.0:
1602; RV64-NEXT:    vsetvli zero, a1, e64, m2, ta, ma
1603; RV64-NEXT:    vssub.vx v8, v8, a0
1604; RV64-NEXT:    ret
1605  %elt.head = insertelement <vscale x 2 x i64> poison, i64 %b, i32 0
1606  %vb = shufflevector <vscale x 2 x i64> %elt.head, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
1607  %v = call <vscale x 2 x i64> @llvm.vp.ssub.sat.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb, <vscale x 2 x i1> splat (i1 true), i32 %evl)
1608  ret <vscale x 2 x i64> %v
1609}
1610
1611define <vscale x 2 x i64> @vssub_vi_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
1612; CHECK-LABEL: vssub_vi_nxv2i64:
1613; CHECK:       # %bb.0:
1614; CHECK-NEXT:    li a1, -1
1615; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, ma
1616; CHECK-NEXT:    vssub.vx v8, v8, a1, v0.t
1617; CHECK-NEXT:    ret
1618  %v = call <vscale x 2 x i64> @llvm.vp.ssub.sat.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> splat (i64 -1), <vscale x 2 x i1> %m, i32 %evl)
1619  ret <vscale x 2 x i64> %v
1620}
1621
1622define <vscale x 2 x i64> @vssub_vi_nxv2i64_unmasked(<vscale x 2 x i64> %va, i32 zeroext %evl) {
1623; CHECK-LABEL: vssub_vi_nxv2i64_unmasked:
1624; CHECK:       # %bb.0:
1625; CHECK-NEXT:    li a1, -1
1626; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, ma
1627; CHECK-NEXT:    vssub.vx v8, v8, a1
1628; CHECK-NEXT:    ret
1629  %v = call <vscale x 2 x i64> @llvm.vp.ssub.sat.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> splat (i64 -1), <vscale x 2 x i1> splat (i1 true), i32 %evl)
1630  ret <vscale x 2 x i64> %v
1631}
1632
1633declare <vscale x 4 x i64> @llvm.vp.ssub.sat.nxv4i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i1>, i32)
1634
1635define <vscale x 4 x i64> @vssub_vv_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %b, <vscale x 4 x i1> %m, i32 zeroext %evl) {
1636; CHECK-LABEL: vssub_vv_nxv4i64:
1637; CHECK:       # %bb.0:
1638; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, ma
1639; CHECK-NEXT:    vssub.vv v8, v8, v12, v0.t
1640; CHECK-NEXT:    ret
1641  %v = call <vscale x 4 x i64> @llvm.vp.ssub.sat.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %b, <vscale x 4 x i1> %m, i32 %evl)
1642  ret <vscale x 4 x i64> %v
1643}
1644
1645define <vscale x 4 x i64> @vssub_vv_nxv4i64_unmasked(<vscale x 4 x i64> %va, <vscale x 4 x i64> %b, i32 zeroext %evl) {
1646; CHECK-LABEL: vssub_vv_nxv4i64_unmasked:
1647; CHECK:       # %bb.0:
1648; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, ma
1649; CHECK-NEXT:    vssub.vv v8, v8, v12
1650; CHECK-NEXT:    ret
1651  %v = call <vscale x 4 x i64> @llvm.vp.ssub.sat.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %b, <vscale x 4 x i1> splat (i1 true), i32 %evl)
1652  ret <vscale x 4 x i64> %v
1653}
1654
1655define <vscale x 4 x i64> @vssub_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b, <vscale x 4 x i1> %m, i32 zeroext %evl) {
1656; RV32-LABEL: vssub_vx_nxv4i64:
1657; RV32:       # %bb.0:
1658; RV32-NEXT:    addi sp, sp, -16
1659; RV32-NEXT:    .cfi_def_cfa_offset 16
1660; RV32-NEXT:    sw a0, 8(sp)
1661; RV32-NEXT:    sw a1, 12(sp)
1662; RV32-NEXT:    addi a0, sp, 8
1663; RV32-NEXT:    vsetvli zero, a2, e64, m4, ta, ma
1664; RV32-NEXT:    vlse64.v v12, (a0), zero
1665; RV32-NEXT:    vssub.vv v8, v8, v12, v0.t
1666; RV32-NEXT:    addi sp, sp, 16
1667; RV32-NEXT:    .cfi_def_cfa_offset 0
1668; RV32-NEXT:    ret
1669;
1670; RV64-LABEL: vssub_vx_nxv4i64:
1671; RV64:       # %bb.0:
1672; RV64-NEXT:    vsetvli zero, a1, e64, m4, ta, ma
1673; RV64-NEXT:    vssub.vx v8, v8, a0, v0.t
1674; RV64-NEXT:    ret
1675  %elt.head = insertelement <vscale x 4 x i64> poison, i64 %b, i32 0
1676  %vb = shufflevector <vscale x 4 x i64> %elt.head, <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer
1677  %v = call <vscale x 4 x i64> @llvm.vp.ssub.sat.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb, <vscale x 4 x i1> %m, i32 %evl)
1678  ret <vscale x 4 x i64> %v
1679}
1680
1681define <vscale x 4 x i64> @vssub_vx_nxv4i64_unmasked(<vscale x 4 x i64> %va, i64 %b, i32 zeroext %evl) {
1682; RV32-LABEL: vssub_vx_nxv4i64_unmasked:
1683; RV32:       # %bb.0:
1684; RV32-NEXT:    addi sp, sp, -16
1685; RV32-NEXT:    .cfi_def_cfa_offset 16
1686; RV32-NEXT:    sw a0, 8(sp)
1687; RV32-NEXT:    sw a1, 12(sp)
1688; RV32-NEXT:    addi a0, sp, 8
1689; RV32-NEXT:    vsetvli zero, a2, e64, m4, ta, ma
1690; RV32-NEXT:    vlse64.v v12, (a0), zero
1691; RV32-NEXT:    vssub.vv v8, v8, v12
1692; RV32-NEXT:    addi sp, sp, 16
1693; RV32-NEXT:    .cfi_def_cfa_offset 0
1694; RV32-NEXT:    ret
1695;
1696; RV64-LABEL: vssub_vx_nxv4i64_unmasked:
1697; RV64:       # %bb.0:
1698; RV64-NEXT:    vsetvli zero, a1, e64, m4, ta, ma
1699; RV64-NEXT:    vssub.vx v8, v8, a0
1700; RV64-NEXT:    ret
1701  %elt.head = insertelement <vscale x 4 x i64> poison, i64 %b, i32 0
1702  %vb = shufflevector <vscale x 4 x i64> %elt.head, <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer
1703  %v = call <vscale x 4 x i64> @llvm.vp.ssub.sat.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb, <vscale x 4 x i1> splat (i1 true), i32 %evl)
1704  ret <vscale x 4 x i64> %v
1705}
1706
1707define <vscale x 4 x i64> @vssub_vi_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {
1708; CHECK-LABEL: vssub_vi_nxv4i64:
1709; CHECK:       # %bb.0:
1710; CHECK-NEXT:    li a1, -1
1711; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, ma
1712; CHECK-NEXT:    vssub.vx v8, v8, a1, v0.t
1713; CHECK-NEXT:    ret
1714  %v = call <vscale x 4 x i64> @llvm.vp.ssub.sat.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> splat (i64 -1), <vscale x 4 x i1> %m, i32 %evl)
1715  ret <vscale x 4 x i64> %v
1716}
1717
1718define <vscale x 4 x i64> @vssub_vi_nxv4i64_unmasked(<vscale x 4 x i64> %va, i32 zeroext %evl) {
1719; CHECK-LABEL: vssub_vi_nxv4i64_unmasked:
1720; CHECK:       # %bb.0:
1721; CHECK-NEXT:    li a1, -1
1722; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, ma
1723; CHECK-NEXT:    vssub.vx v8, v8, a1
1724; CHECK-NEXT:    ret
1725  %v = call <vscale x 4 x i64> @llvm.vp.ssub.sat.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> splat (i64 -1), <vscale x 4 x i1> splat (i1 true), i32 %evl)
1726  ret <vscale x 4 x i64> %v
1727}
1728
1729declare <vscale x 8 x i64> @llvm.vp.ssub.sat.nxv8i64(<vscale x 8 x i64>, <vscale x 8 x i64>, <vscale x 8 x i1>, i32)
1730
1731define <vscale x 8 x i64> @vssub_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
1732; CHECK-LABEL: vssub_vv_nxv8i64:
1733; CHECK:       # %bb.0:
1734; CHECK-NEXT:    vsetvli zero, a0, e64, m8, ta, ma
1735; CHECK-NEXT:    vssub.vv v8, v8, v16, v0.t
1736; CHECK-NEXT:    ret
1737  %v = call <vscale x 8 x i64> @llvm.vp.ssub.sat.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %b, <vscale x 8 x i1> %m, i32 %evl)
1738  ret <vscale x 8 x i64> %v
1739}
1740
1741define <vscale x 8 x i64> @vssub_vv_nxv8i64_unmasked(<vscale x 8 x i64> %va, <vscale x 8 x i64> %b, i32 zeroext %evl) {
1742; CHECK-LABEL: vssub_vv_nxv8i64_unmasked:
1743; CHECK:       # %bb.0:
1744; CHECK-NEXT:    vsetvli zero, a0, e64, m8, ta, ma
1745; CHECK-NEXT:    vssub.vv v8, v8, v16
1746; CHECK-NEXT:    ret
1747  %v = call <vscale x 8 x i64> @llvm.vp.ssub.sat.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %b, <vscale x 8 x i1> splat (i1 true), i32 %evl)
1748  ret <vscale x 8 x i64> %v
1749}
1750
1751define <vscale x 8 x i64> @vssub_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
1752; RV32-LABEL: vssub_vx_nxv8i64:
1753; RV32:       # %bb.0:
1754; RV32-NEXT:    addi sp, sp, -16
1755; RV32-NEXT:    .cfi_def_cfa_offset 16
1756; RV32-NEXT:    sw a0, 8(sp)
1757; RV32-NEXT:    sw a1, 12(sp)
1758; RV32-NEXT:    addi a0, sp, 8
1759; RV32-NEXT:    vsetvli zero, a2, e64, m8, ta, ma
1760; RV32-NEXT:    vlse64.v v16, (a0), zero
1761; RV32-NEXT:    vssub.vv v8, v8, v16, v0.t
1762; RV32-NEXT:    addi sp, sp, 16
1763; RV32-NEXT:    .cfi_def_cfa_offset 0
1764; RV32-NEXT:    ret
1765;
1766; RV64-LABEL: vssub_vx_nxv8i64:
1767; RV64:       # %bb.0:
1768; RV64-NEXT:    vsetvli zero, a1, e64, m8, ta, ma
1769; RV64-NEXT:    vssub.vx v8, v8, a0, v0.t
1770; RV64-NEXT:    ret
1771  %elt.head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
1772  %vb = shufflevector <vscale x 8 x i64> %elt.head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
1773  %v = call <vscale x 8 x i64> @llvm.vp.ssub.sat.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb, <vscale x 8 x i1> %m, i32 %evl)
1774  ret <vscale x 8 x i64> %v
1775}
1776
1777define <vscale x 8 x i64> @vssub_vx_nxv8i64_unmasked(<vscale x 8 x i64> %va, i64 %b, i32 zeroext %evl) {
1778; RV32-LABEL: vssub_vx_nxv8i64_unmasked:
1779; RV32:       # %bb.0:
1780; RV32-NEXT:    addi sp, sp, -16
1781; RV32-NEXT:    .cfi_def_cfa_offset 16
1782; RV32-NEXT:    sw a0, 8(sp)
1783; RV32-NEXT:    sw a1, 12(sp)
1784; RV32-NEXT:    addi a0, sp, 8
1785; RV32-NEXT:    vsetvli zero, a2, e64, m8, ta, ma
1786; RV32-NEXT:    vlse64.v v16, (a0), zero
1787; RV32-NEXT:    vssub.vv v8, v8, v16
1788; RV32-NEXT:    addi sp, sp, 16
1789; RV32-NEXT:    .cfi_def_cfa_offset 0
1790; RV32-NEXT:    ret
1791;
1792; RV64-LABEL: vssub_vx_nxv8i64_unmasked:
1793; RV64:       # %bb.0:
1794; RV64-NEXT:    vsetvli zero, a1, e64, m8, ta, ma
1795; RV64-NEXT:    vssub.vx v8, v8, a0
1796; RV64-NEXT:    ret
1797  %elt.head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
1798  %vb = shufflevector <vscale x 8 x i64> %elt.head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
1799  %v = call <vscale x 8 x i64> @llvm.vp.ssub.sat.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb, <vscale x 8 x i1> splat (i1 true), i32 %evl)
1800  ret <vscale x 8 x i64> %v
1801}
1802
1803define <vscale x 8 x i64> @vssub_vi_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {
1804; CHECK-LABEL: vssub_vi_nxv8i64:
1805; CHECK:       # %bb.0:
1806; CHECK-NEXT:    li a1, -1
1807; CHECK-NEXT:    vsetvli zero, a0, e64, m8, ta, ma
1808; CHECK-NEXT:    vssub.vx v8, v8, a1, v0.t
1809; CHECK-NEXT:    ret
1810  %v = call <vscale x 8 x i64> @llvm.vp.ssub.sat.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> splat (i64 -1), <vscale x 8 x i1> %m, i32 %evl)
1811  ret <vscale x 8 x i64> %v
1812}
1813
1814define <vscale x 8 x i64> @vssub_vi_nxv8i64_unmasked(<vscale x 8 x i64> %va, i32 zeroext %evl) {
1815; CHECK-LABEL: vssub_vi_nxv8i64_unmasked:
1816; CHECK:       # %bb.0:
1817; CHECK-NEXT:    li a1, -1
1818; CHECK-NEXT:    vsetvli zero, a0, e64, m8, ta, ma
1819; CHECK-NEXT:    vssub.vx v8, v8, a1
1820; CHECK-NEXT:    ret
1821  %v = call <vscale x 8 x i64> @llvm.vp.ssub.sat.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> splat (i64 -1), <vscale x 8 x i1> splat (i1 true), i32 %evl)
1822  ret <vscale x 8 x i64> %v
1823}
1824