xref: /llvm-project/llvm/test/CodeGen/RISCV/rvv/vssub-sdnode.ll (revision 97982a8c605fac7c86d02e641a6cd7898b3ca343) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s \
3; RUN:   | FileCheck %s --check-prefixes=CHECK,RV32
4; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s \
5; RUN:   | FileCheck %s --check-prefixes=CHECK,RV64
6
7declare <vscale x 1 x i8> @llvm.ssub.sat.nxv1i8(<vscale x 1 x i8>, <vscale x 1 x i8>)
8
9define <vscale x 1 x i8> @ssub_nxv1i8_vv(<vscale x 1 x i8> %va, <vscale x 1 x i8> %b) {
10; CHECK-LABEL: ssub_nxv1i8_vv:
11; CHECK:       # %bb.0:
12; CHECK-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
13; CHECK-NEXT:    vssub.vv v8, v8, v9
14; CHECK-NEXT:    ret
15  %v = call <vscale x 1 x i8> @llvm.ssub.sat.nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %b)
16  ret <vscale x 1 x i8> %v
17}
18
19define <vscale x 1 x i8> @ssub_nxv1i8_vx(<vscale x 1 x i8> %va, i8 %b) {
20; CHECK-LABEL: ssub_nxv1i8_vx:
21; CHECK:       # %bb.0:
22; CHECK-NEXT:    vsetvli a1, zero, e8, mf8, ta, ma
23; CHECK-NEXT:    vssub.vx v8, v8, a0
24; CHECK-NEXT:    ret
25  %elt.head = insertelement <vscale x 1 x i8> poison, i8 %b, i32 0
26  %vb = shufflevector <vscale x 1 x i8> %elt.head, <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer
27  %v = call <vscale x 1 x i8> @llvm.ssub.sat.nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %vb)
28  ret <vscale x 1 x i8> %v
29}
30
31define <vscale x 1 x i8> @ssub_nxv1i8_vi(<vscale x 1 x i8> %va) {
32; CHECK-LABEL: ssub_nxv1i8_vi:
33; CHECK:       # %bb.0:
34; CHECK-NEXT:    li a0, 1
35; CHECK-NEXT:    vsetvli a1, zero, e8, mf8, ta, ma
36; CHECK-NEXT:    vssub.vx v8, v8, a0
37; CHECK-NEXT:    ret
38  %v = call <vscale x 1 x i8> @llvm.ssub.sat.nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> splat (i8 1))
39  ret <vscale x 1 x i8> %v
40}
41
42declare <vscale x 2 x i8> @llvm.ssub.sat.nxv2i8(<vscale x 2 x i8>, <vscale x 2 x i8>)
43
44define <vscale x 2 x i8> @ssub_nxv2i8_vv(<vscale x 2 x i8> %va, <vscale x 2 x i8> %b) {
45; CHECK-LABEL: ssub_nxv2i8_vv:
46; CHECK:       # %bb.0:
47; CHECK-NEXT:    vsetvli a0, zero, e8, mf4, ta, ma
48; CHECK-NEXT:    vssub.vv v8, v8, v9
49; CHECK-NEXT:    ret
50  %v = call <vscale x 2 x i8> @llvm.ssub.sat.nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %b)
51  ret <vscale x 2 x i8> %v
52}
53
54define <vscale x 2 x i8> @ssub_nxv2i8_vx(<vscale x 2 x i8> %va, i8 %b) {
55; CHECK-LABEL: ssub_nxv2i8_vx:
56; CHECK:       # %bb.0:
57; CHECK-NEXT:    vsetvli a1, zero, e8, mf4, ta, ma
58; CHECK-NEXT:    vssub.vx v8, v8, a0
59; CHECK-NEXT:    ret
60  %elt.head = insertelement <vscale x 2 x i8> poison, i8 %b, i32 0
61  %vb = shufflevector <vscale x 2 x i8> %elt.head, <vscale x 2 x i8> poison, <vscale x 2 x i32> zeroinitializer
62  %v = call <vscale x 2 x i8> @llvm.ssub.sat.nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %vb)
63  ret <vscale x 2 x i8> %v
64}
65
66define <vscale x 2 x i8> @ssub_nxv2i8_vi(<vscale x 2 x i8> %va) {
67; CHECK-LABEL: ssub_nxv2i8_vi:
68; CHECK:       # %bb.0:
69; CHECK-NEXT:    li a0, 1
70; CHECK-NEXT:    vsetvli a1, zero, e8, mf4, ta, ma
71; CHECK-NEXT:    vssub.vx v8, v8, a0
72; CHECK-NEXT:    ret
73  %v = call <vscale x 2 x i8> @llvm.ssub.sat.nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> splat (i8 1))
74  ret <vscale x 2 x i8> %v
75}
76
77declare <vscale x 4 x i8> @llvm.ssub.sat.nxv4i8(<vscale x 4 x i8>, <vscale x 4 x i8>)
78
79define <vscale x 4 x i8> @ssub_nxv4i8_vv(<vscale x 4 x i8> %va, <vscale x 4 x i8> %b) {
80; CHECK-LABEL: ssub_nxv4i8_vv:
81; CHECK:       # %bb.0:
82; CHECK-NEXT:    vsetvli a0, zero, e8, mf2, ta, ma
83; CHECK-NEXT:    vssub.vv v8, v8, v9
84; CHECK-NEXT:    ret
85  %v = call <vscale x 4 x i8> @llvm.ssub.sat.nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %b)
86  ret <vscale x 4 x i8> %v
87}
88
89define <vscale x 4 x i8> @ssub_nxv4i8_vx(<vscale x 4 x i8> %va, i8 %b) {
90; CHECK-LABEL: ssub_nxv4i8_vx:
91; CHECK:       # %bb.0:
92; CHECK-NEXT:    vsetvli a1, zero, e8, mf2, ta, ma
93; CHECK-NEXT:    vssub.vx v8, v8, a0
94; CHECK-NEXT:    ret
95  %elt.head = insertelement <vscale x 4 x i8> poison, i8 %b, i32 0
96  %vb = shufflevector <vscale x 4 x i8> %elt.head, <vscale x 4 x i8> poison, <vscale x 4 x i32> zeroinitializer
97  %v = call <vscale x 4 x i8> @llvm.ssub.sat.nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %vb)
98  ret <vscale x 4 x i8> %v
99}
100
101define <vscale x 4 x i8> @ssub_nxv4i8_vi(<vscale x 4 x i8> %va) {
102; CHECK-LABEL: ssub_nxv4i8_vi:
103; CHECK:       # %bb.0:
104; CHECK-NEXT:    li a0, 1
105; CHECK-NEXT:    vsetvli a1, zero, e8, mf2, ta, ma
106; CHECK-NEXT:    vssub.vx v8, v8, a0
107; CHECK-NEXT:    ret
108  %v = call <vscale x 4 x i8> @llvm.ssub.sat.nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> splat (i8 1))
109  ret <vscale x 4 x i8> %v
110}
111
112declare <vscale x 8 x i8> @llvm.ssub.sat.nxv8i8(<vscale x 8 x i8>, <vscale x 8 x i8>)
113
114define <vscale x 8 x i8> @ssub_nxv8i8_vv(<vscale x 8 x i8> %va, <vscale x 8 x i8> %b) {
115; CHECK-LABEL: ssub_nxv8i8_vv:
116; CHECK:       # %bb.0:
117; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, ma
118; CHECK-NEXT:    vssub.vv v8, v8, v9
119; CHECK-NEXT:    ret
120  %v = call <vscale x 8 x i8> @llvm.ssub.sat.nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %b)
121  ret <vscale x 8 x i8> %v
122}
123
124define <vscale x 8 x i8> @ssub_nxv8i8_vx(<vscale x 8 x i8> %va, i8 %b) {
125; CHECK-LABEL: ssub_nxv8i8_vx:
126; CHECK:       # %bb.0:
127; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, ma
128; CHECK-NEXT:    vssub.vx v8, v8, a0
129; CHECK-NEXT:    ret
130  %elt.head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0
131  %vb = shufflevector <vscale x 8 x i8> %elt.head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
132  %v = call <vscale x 8 x i8> @llvm.ssub.sat.nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb)
133  ret <vscale x 8 x i8> %v
134}
135
136define <vscale x 8 x i8> @ssub_nxv8i8_vi(<vscale x 8 x i8> %va) {
137; CHECK-LABEL: ssub_nxv8i8_vi:
138; CHECK:       # %bb.0:
139; CHECK-NEXT:    li a0, 1
140; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, ma
141; CHECK-NEXT:    vssub.vx v8, v8, a0
142; CHECK-NEXT:    ret
143  %v = call <vscale x 8 x i8> @llvm.ssub.sat.nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> splat (i8 1))
144  ret <vscale x 8 x i8> %v
145}
146
147declare <vscale x 16 x i8> @llvm.ssub.sat.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>)
148
149define <vscale x 16 x i8> @ssub_nxv16i8_vv(<vscale x 16 x i8> %va, <vscale x 16 x i8> %b) {
150; CHECK-LABEL: ssub_nxv16i8_vv:
151; CHECK:       # %bb.0:
152; CHECK-NEXT:    vsetvli a0, zero, e8, m2, ta, ma
153; CHECK-NEXT:    vssub.vv v8, v8, v10
154; CHECK-NEXT:    ret
155  %v = call <vscale x 16 x i8> @llvm.ssub.sat.nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %b)
156  ret <vscale x 16 x i8> %v
157}
158
159define <vscale x 16 x i8> @ssub_nxv16i8_vx(<vscale x 16 x i8> %va, i8 %b) {
160; CHECK-LABEL: ssub_nxv16i8_vx:
161; CHECK:       # %bb.0:
162; CHECK-NEXT:    vsetvli a1, zero, e8, m2, ta, ma
163; CHECK-NEXT:    vssub.vx v8, v8, a0
164; CHECK-NEXT:    ret
165  %elt.head = insertelement <vscale x 16 x i8> poison, i8 %b, i32 0
166  %vb = shufflevector <vscale x 16 x i8> %elt.head, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
167  %v = call <vscale x 16 x i8> @llvm.ssub.sat.nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %vb)
168  ret <vscale x 16 x i8> %v
169}
170
171define <vscale x 16 x i8> @ssub_nxv16i8_vi(<vscale x 16 x i8> %va) {
172; CHECK-LABEL: ssub_nxv16i8_vi:
173; CHECK:       # %bb.0:
174; CHECK-NEXT:    li a0, 1
175; CHECK-NEXT:    vsetvli a1, zero, e8, m2, ta, ma
176; CHECK-NEXT:    vssub.vx v8, v8, a0
177; CHECK-NEXT:    ret
178  %v = call <vscale x 16 x i8> @llvm.ssub.sat.nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> splat (i8 1))
179  ret <vscale x 16 x i8> %v
180}
181
182declare <vscale x 32 x i8> @llvm.ssub.sat.nxv32i8(<vscale x 32 x i8>, <vscale x 32 x i8>)
183
184define <vscale x 32 x i8> @ssub_nxv32i8_vv(<vscale x 32 x i8> %va, <vscale x 32 x i8> %b) {
185; CHECK-LABEL: ssub_nxv32i8_vv:
186; CHECK:       # %bb.0:
187; CHECK-NEXT:    vsetvli a0, zero, e8, m4, ta, ma
188; CHECK-NEXT:    vssub.vv v8, v8, v12
189; CHECK-NEXT:    ret
190  %v = call <vscale x 32 x i8> @llvm.ssub.sat.nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %b)
191  ret <vscale x 32 x i8> %v
192}
193
194define <vscale x 32 x i8> @ssub_nxv32i8_vx(<vscale x 32 x i8> %va, i8 %b) {
195; CHECK-LABEL: ssub_nxv32i8_vx:
196; CHECK:       # %bb.0:
197; CHECK-NEXT:    vsetvli a1, zero, e8, m4, ta, ma
198; CHECK-NEXT:    vssub.vx v8, v8, a0
199; CHECK-NEXT:    ret
200  %elt.head = insertelement <vscale x 32 x i8> poison, i8 %b, i32 0
201  %vb = shufflevector <vscale x 32 x i8> %elt.head, <vscale x 32 x i8> poison, <vscale x 32 x i32> zeroinitializer
202  %v = call <vscale x 32 x i8> @llvm.ssub.sat.nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %vb)
203  ret <vscale x 32 x i8> %v
204}
205
206define <vscale x 32 x i8> @ssub_nxv32i8_vi(<vscale x 32 x i8> %va) {
207; CHECK-LABEL: ssub_nxv32i8_vi:
208; CHECK:       # %bb.0:
209; CHECK-NEXT:    li a0, 1
210; CHECK-NEXT:    vsetvli a1, zero, e8, m4, ta, ma
211; CHECK-NEXT:    vssub.vx v8, v8, a0
212; CHECK-NEXT:    ret
213  %v = call <vscale x 32 x i8> @llvm.ssub.sat.nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> splat (i8 1))
214  ret <vscale x 32 x i8> %v
215}
216
217declare <vscale x 64 x i8> @llvm.ssub.sat.nxv64i8(<vscale x 64 x i8>, <vscale x 64 x i8>)
218
219define <vscale x 64 x i8> @ssub_nxv64i8_vv(<vscale x 64 x i8> %va, <vscale x 64 x i8> %b) {
220; CHECK-LABEL: ssub_nxv64i8_vv:
221; CHECK:       # %bb.0:
222; CHECK-NEXT:    vsetvli a0, zero, e8, m8, ta, ma
223; CHECK-NEXT:    vssub.vv v8, v8, v16
224; CHECK-NEXT:    ret
225  %v = call <vscale x 64 x i8> @llvm.ssub.sat.nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %b)
226  ret <vscale x 64 x i8> %v
227}
228
229define <vscale x 64 x i8> @ssub_nxv64i8_vx(<vscale x 64 x i8> %va, i8 %b) {
230; CHECK-LABEL: ssub_nxv64i8_vx:
231; CHECK:       # %bb.0:
232; CHECK-NEXT:    vsetvli a1, zero, e8, m8, ta, ma
233; CHECK-NEXT:    vssub.vx v8, v8, a0
234; CHECK-NEXT:    ret
235  %elt.head = insertelement <vscale x 64 x i8> poison, i8 %b, i32 0
236  %vb = shufflevector <vscale x 64 x i8> %elt.head, <vscale x 64 x i8> poison, <vscale x 64 x i32> zeroinitializer
237  %v = call <vscale x 64 x i8> @llvm.ssub.sat.nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %vb)
238  ret <vscale x 64 x i8> %v
239}
240
241define <vscale x 64 x i8> @ssub_nxv64i8_vi(<vscale x 64 x i8> %va) {
242; CHECK-LABEL: ssub_nxv64i8_vi:
243; CHECK:       # %bb.0:
244; CHECK-NEXT:    li a0, 1
245; CHECK-NEXT:    vsetvli a1, zero, e8, m8, ta, ma
246; CHECK-NEXT:    vssub.vx v8, v8, a0
247; CHECK-NEXT:    ret
248  %v = call <vscale x 64 x i8> @llvm.ssub.sat.nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> splat (i8 1))
249  ret <vscale x 64 x i8> %v
250}
251
252declare <vscale x 1 x i16> @llvm.ssub.sat.nxv1i16(<vscale x 1 x i16>, <vscale x 1 x i16>)
253
254define <vscale x 1 x i16> @ssub_nxv1i16_vv(<vscale x 1 x i16> %va, <vscale x 1 x i16> %b) {
255; CHECK-LABEL: ssub_nxv1i16_vv:
256; CHECK:       # %bb.0:
257; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, ma
258; CHECK-NEXT:    vssub.vv v8, v8, v9
259; CHECK-NEXT:    ret
260  %v = call <vscale x 1 x i16> @llvm.ssub.sat.nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %b)
261  ret <vscale x 1 x i16> %v
262}
263
264define <vscale x 1 x i16> @ssub_nxv1i16_vx(<vscale x 1 x i16> %va, i16 %b) {
265; CHECK-LABEL: ssub_nxv1i16_vx:
266; CHECK:       # %bb.0:
267; CHECK-NEXT:    vsetvli a1, zero, e16, mf4, ta, ma
268; CHECK-NEXT:    vssub.vx v8, v8, a0
269; CHECK-NEXT:    ret
270  %elt.head = insertelement <vscale x 1 x i16> poison, i16 %b, i32 0
271  %vb = shufflevector <vscale x 1 x i16> %elt.head, <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer
272  %v = call <vscale x 1 x i16> @llvm.ssub.sat.nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %vb)
273  ret <vscale x 1 x i16> %v
274}
275
276define <vscale x 1 x i16> @ssub_nxv1i16_vi(<vscale x 1 x i16> %va) {
277; CHECK-LABEL: ssub_nxv1i16_vi:
278; CHECK:       # %bb.0:
279; CHECK-NEXT:    li a0, 1
280; CHECK-NEXT:    vsetvli a1, zero, e16, mf4, ta, ma
281; CHECK-NEXT:    vssub.vx v8, v8, a0
282; CHECK-NEXT:    ret
283  %v = call <vscale x 1 x i16> @llvm.ssub.sat.nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> splat (i16 1))
284  ret <vscale x 1 x i16> %v
285}
286
287declare <vscale x 2 x i16> @llvm.ssub.sat.nxv2i16(<vscale x 2 x i16>, <vscale x 2 x i16>)
288
289define <vscale x 2 x i16> @ssub_nxv2i16_vv(<vscale x 2 x i16> %va, <vscale x 2 x i16> %b) {
290; CHECK-LABEL: ssub_nxv2i16_vv:
291; CHECK:       # %bb.0:
292; CHECK-NEXT:    vsetvli a0, zero, e16, mf2, ta, ma
293; CHECK-NEXT:    vssub.vv v8, v8, v9
294; CHECK-NEXT:    ret
295  %v = call <vscale x 2 x i16> @llvm.ssub.sat.nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %b)
296  ret <vscale x 2 x i16> %v
297}
298
299define <vscale x 2 x i16> @ssub_nxv2i16_vx(<vscale x 2 x i16> %va, i16 %b) {
300; CHECK-LABEL: ssub_nxv2i16_vx:
301; CHECK:       # %bb.0:
302; CHECK-NEXT:    vsetvli a1, zero, e16, mf2, ta, ma
303; CHECK-NEXT:    vssub.vx v8, v8, a0
304; CHECK-NEXT:    ret
305  %elt.head = insertelement <vscale x 2 x i16> poison, i16 %b, i32 0
306  %vb = shufflevector <vscale x 2 x i16> %elt.head, <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer
307  %v = call <vscale x 2 x i16> @llvm.ssub.sat.nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %vb)
308  ret <vscale x 2 x i16> %v
309}
310
311define <vscale x 2 x i16> @ssub_nxv2i16_vi(<vscale x 2 x i16> %va) {
312; CHECK-LABEL: ssub_nxv2i16_vi:
313; CHECK:       # %bb.0:
314; CHECK-NEXT:    li a0, 1
315; CHECK-NEXT:    vsetvli a1, zero, e16, mf2, ta, ma
316; CHECK-NEXT:    vssub.vx v8, v8, a0
317; CHECK-NEXT:    ret
318  %v = call <vscale x 2 x i16> @llvm.ssub.sat.nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> splat (i16 1))
319  ret <vscale x 2 x i16> %v
320}
321
322declare <vscale x 4 x i16> @llvm.ssub.sat.nxv4i16(<vscale x 4 x i16>, <vscale x 4 x i16>)
323
324define <vscale x 4 x i16> @ssub_nxv4i16_vv(<vscale x 4 x i16> %va, <vscale x 4 x i16> %b) {
325; CHECK-LABEL: ssub_nxv4i16_vv:
326; CHECK:       # %bb.0:
327; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, ma
328; CHECK-NEXT:    vssub.vv v8, v8, v9
329; CHECK-NEXT:    ret
330  %v = call <vscale x 4 x i16> @llvm.ssub.sat.nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %b)
331  ret <vscale x 4 x i16> %v
332}
333
334define <vscale x 4 x i16> @ssub_nxv4i16_vx(<vscale x 4 x i16> %va, i16 %b) {
335; CHECK-LABEL: ssub_nxv4i16_vx:
336; CHECK:       # %bb.0:
337; CHECK-NEXT:    vsetvli a1, zero, e16, m1, ta, ma
338; CHECK-NEXT:    vssub.vx v8, v8, a0
339; CHECK-NEXT:    ret
340  %elt.head = insertelement <vscale x 4 x i16> poison, i16 %b, i32 0
341  %vb = shufflevector <vscale x 4 x i16> %elt.head, <vscale x 4 x i16> poison, <vscale x 4 x i32> zeroinitializer
342  %v = call <vscale x 4 x i16> @llvm.ssub.sat.nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %vb)
343  ret <vscale x 4 x i16> %v
344}
345
346define <vscale x 4 x i16> @ssub_nxv4i16_vi(<vscale x 4 x i16> %va) {
347; CHECK-LABEL: ssub_nxv4i16_vi:
348; CHECK:       # %bb.0:
349; CHECK-NEXT:    li a0, 1
350; CHECK-NEXT:    vsetvli a1, zero, e16, m1, ta, ma
351; CHECK-NEXT:    vssub.vx v8, v8, a0
352; CHECK-NEXT:    ret
353  %v = call <vscale x 4 x i16> @llvm.ssub.sat.nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> splat (i16 1))
354  ret <vscale x 4 x i16> %v
355}
356
357declare <vscale x 8 x i16> @llvm.ssub.sat.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>)
358
359define <vscale x 8 x i16> @ssub_nxv8i16_vv(<vscale x 8 x i16> %va, <vscale x 8 x i16> %b) {
360; CHECK-LABEL: ssub_nxv8i16_vv:
361; CHECK:       # %bb.0:
362; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, ma
363; CHECK-NEXT:    vssub.vv v8, v8, v10
364; CHECK-NEXT:    ret
365  %v = call <vscale x 8 x i16> @llvm.ssub.sat.nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %b)
366  ret <vscale x 8 x i16> %v
367}
368
369define <vscale x 8 x i16> @ssub_nxv8i16_vx(<vscale x 8 x i16> %va, i16 %b) {
370; CHECK-LABEL: ssub_nxv8i16_vx:
371; CHECK:       # %bb.0:
372; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, ma
373; CHECK-NEXT:    vssub.vx v8, v8, a0
374; CHECK-NEXT:    ret
375  %elt.head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0
376  %vb = shufflevector <vscale x 8 x i16> %elt.head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
377  %v = call <vscale x 8 x i16> @llvm.ssub.sat.nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb)
378  ret <vscale x 8 x i16> %v
379}
380
381define <vscale x 8 x i16> @ssub_nxv8i16_vi(<vscale x 8 x i16> %va) {
382; CHECK-LABEL: ssub_nxv8i16_vi:
383; CHECK:       # %bb.0:
384; CHECK-NEXT:    li a0, 1
385; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, ma
386; CHECK-NEXT:    vssub.vx v8, v8, a0
387; CHECK-NEXT:    ret
388  %v = call <vscale x 8 x i16> @llvm.ssub.sat.nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> splat (i16 1))
389  ret <vscale x 8 x i16> %v
390}
391
392declare <vscale x 16 x i16> @llvm.ssub.sat.nxv16i16(<vscale x 16 x i16>, <vscale x 16 x i16>)
393
394define <vscale x 16 x i16> @ssub_nxv16i16_vv(<vscale x 16 x i16> %va, <vscale x 16 x i16> %b) {
395; CHECK-LABEL: ssub_nxv16i16_vv:
396; CHECK:       # %bb.0:
397; CHECK-NEXT:    vsetvli a0, zero, e16, m4, ta, ma
398; CHECK-NEXT:    vssub.vv v8, v8, v12
399; CHECK-NEXT:    ret
400  %v = call <vscale x 16 x i16> @llvm.ssub.sat.nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %b)
401  ret <vscale x 16 x i16> %v
402}
403
404define <vscale x 16 x i16> @ssub_nxv16i16_vx(<vscale x 16 x i16> %va, i16 %b) {
405; CHECK-LABEL: ssub_nxv16i16_vx:
406; CHECK:       # %bb.0:
407; CHECK-NEXT:    vsetvli a1, zero, e16, m4, ta, ma
408; CHECK-NEXT:    vssub.vx v8, v8, a0
409; CHECK-NEXT:    ret
410  %elt.head = insertelement <vscale x 16 x i16> poison, i16 %b, i32 0
411  %vb = shufflevector <vscale x 16 x i16> %elt.head, <vscale x 16 x i16> poison, <vscale x 16 x i32> zeroinitializer
412  %v = call <vscale x 16 x i16> @llvm.ssub.sat.nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %vb)
413  ret <vscale x 16 x i16> %v
414}
415
416define <vscale x 16 x i16> @ssub_nxv16i16_vi(<vscale x 16 x i16> %va) {
417; CHECK-LABEL: ssub_nxv16i16_vi:
418; CHECK:       # %bb.0:
419; CHECK-NEXT:    li a0, 1
420; CHECK-NEXT:    vsetvli a1, zero, e16, m4, ta, ma
421; CHECK-NEXT:    vssub.vx v8, v8, a0
422; CHECK-NEXT:    ret
423  %v = call <vscale x 16 x i16> @llvm.ssub.sat.nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> splat (i16 1))
424  ret <vscale x 16 x i16> %v
425}
426
427declare <vscale x 32 x i16> @llvm.ssub.sat.nxv32i16(<vscale x 32 x i16>, <vscale x 32 x i16>)
428
429define <vscale x 32 x i16> @ssub_nxv32i16_vv(<vscale x 32 x i16> %va, <vscale x 32 x i16> %b) {
430; CHECK-LABEL: ssub_nxv32i16_vv:
431; CHECK:       # %bb.0:
432; CHECK-NEXT:    vsetvli a0, zero, e16, m8, ta, ma
433; CHECK-NEXT:    vssub.vv v8, v8, v16
434; CHECK-NEXT:    ret
435  %v = call <vscale x 32 x i16> @llvm.ssub.sat.nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %b)
436  ret <vscale x 32 x i16> %v
437}
438
439define <vscale x 32 x i16> @ssub_nxv32i16_vx(<vscale x 32 x i16> %va, i16 %b) {
440; CHECK-LABEL: ssub_nxv32i16_vx:
441; CHECK:       # %bb.0:
442; CHECK-NEXT:    vsetvli a1, zero, e16, m8, ta, ma
443; CHECK-NEXT:    vssub.vx v8, v8, a0
444; CHECK-NEXT:    ret
445  %elt.head = insertelement <vscale x 32 x i16> poison, i16 %b, i32 0
446  %vb = shufflevector <vscale x 32 x i16> %elt.head, <vscale x 32 x i16> poison, <vscale x 32 x i32> zeroinitializer
447  %v = call <vscale x 32 x i16> @llvm.ssub.sat.nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %vb)
448  ret <vscale x 32 x i16> %v
449}
450
451define <vscale x 32 x i16> @ssub_nxv32i16_vi(<vscale x 32 x i16> %va) {
452; CHECK-LABEL: ssub_nxv32i16_vi:
453; CHECK:       # %bb.0:
454; CHECK-NEXT:    li a0, 1
455; CHECK-NEXT:    vsetvli a1, zero, e16, m8, ta, ma
456; CHECK-NEXT:    vssub.vx v8, v8, a0
457; CHECK-NEXT:    ret
458  %v = call <vscale x 32 x i16> @llvm.ssub.sat.nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> splat (i16 1))
459  ret <vscale x 32 x i16> %v
460}
461
462declare <vscale x 1 x i32> @llvm.ssub.sat.nxv1i32(<vscale x 1 x i32>, <vscale x 1 x i32>)
463
464define <vscale x 1 x i32> @ssub_nxv1i32_vv(<vscale x 1 x i32> %va, <vscale x 1 x i32> %b) {
465; CHECK-LABEL: ssub_nxv1i32_vv:
466; CHECK:       # %bb.0:
467; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, ma
468; CHECK-NEXT:    vssub.vv v8, v8, v9
469; CHECK-NEXT:    ret
470  %v = call <vscale x 1 x i32> @llvm.ssub.sat.nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %b)
471  ret <vscale x 1 x i32> %v
472}
473
474define <vscale x 1 x i32> @ssub_nxv1i32_vx(<vscale x 1 x i32> %va, i32 %b) {
475; CHECK-LABEL: ssub_nxv1i32_vx:
476; CHECK:       # %bb.0:
477; CHECK-NEXT:    vsetvli a1, zero, e32, mf2, ta, ma
478; CHECK-NEXT:    vssub.vx v8, v8, a0
479; CHECK-NEXT:    ret
480  %elt.head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 0
481  %vb = shufflevector <vscale x 1 x i32> %elt.head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer
482  %v = call <vscale x 1 x i32> @llvm.ssub.sat.nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb)
483  ret <vscale x 1 x i32> %v
484}
485
486define <vscale x 1 x i32> @ssub_nxv1i32_vi(<vscale x 1 x i32> %va) {
487; CHECK-LABEL: ssub_nxv1i32_vi:
488; CHECK:       # %bb.0:
489; CHECK-NEXT:    li a0, 1
490; CHECK-NEXT:    vsetvli a1, zero, e32, mf2, ta, ma
491; CHECK-NEXT:    vssub.vx v8, v8, a0
492; CHECK-NEXT:    ret
493  %v = call <vscale x 1 x i32> @llvm.ssub.sat.nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> splat (i32 1))
494  ret <vscale x 1 x i32> %v
495}
496
497declare <vscale x 2 x i32> @llvm.ssub.sat.nxv2i32(<vscale x 2 x i32>, <vscale x 2 x i32>)
498
499define <vscale x 2 x i32> @ssub_nxv2i32_vv(<vscale x 2 x i32> %va, <vscale x 2 x i32> %b) {
500; CHECK-LABEL: ssub_nxv2i32_vv:
501; CHECK:       # %bb.0:
502; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, ma
503; CHECK-NEXT:    vssub.vv v8, v8, v9
504; CHECK-NEXT:    ret
505  %v = call <vscale x 2 x i32> @llvm.ssub.sat.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %b)
506  ret <vscale x 2 x i32> %v
507}
508
509define <vscale x 2 x i32> @ssub_nxv2i32_vx(<vscale x 2 x i32> %va, i32 %b) {
510; CHECK-LABEL: ssub_nxv2i32_vx:
511; CHECK:       # %bb.0:
512; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, ma
513; CHECK-NEXT:    vssub.vx v8, v8, a0
514; CHECK-NEXT:    ret
515  %elt.head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0
516  %vb = shufflevector <vscale x 2 x i32> %elt.head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer
517  %v = call <vscale x 2 x i32> @llvm.ssub.sat.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb)
518  ret <vscale x 2 x i32> %v
519}
520
521define <vscale x 2 x i32> @ssub_nxv2i32_vi(<vscale x 2 x i32> %va) {
522; CHECK-LABEL: ssub_nxv2i32_vi:
523; CHECK:       # %bb.0:
524; CHECK-NEXT:    li a0, 1
525; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, ma
526; CHECK-NEXT:    vssub.vx v8, v8, a0
527; CHECK-NEXT:    ret
528  %v = call <vscale x 2 x i32> @llvm.ssub.sat.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> splat (i32 1))
529  ret <vscale x 2 x i32> %v
530}
531
532declare <vscale x 4 x i32> @llvm.ssub.sat.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>)
533
534define <vscale x 4 x i32> @ssub_nxv4i32_vv(<vscale x 4 x i32> %va, <vscale x 4 x i32> %b) {
535; CHECK-LABEL: ssub_nxv4i32_vv:
536; CHECK:       # %bb.0:
537; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, ma
538; CHECK-NEXT:    vssub.vv v8, v8, v10
539; CHECK-NEXT:    ret
540  %v = call <vscale x 4 x i32> @llvm.ssub.sat.nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %b)
541  ret <vscale x 4 x i32> %v
542}
543
544define <vscale x 4 x i32> @ssub_nxv4i32_vx(<vscale x 4 x i32> %va, i32 %b) {
545; CHECK-LABEL: ssub_nxv4i32_vx:
546; CHECK:       # %bb.0:
547; CHECK-NEXT:    vsetvli a1, zero, e32, m2, ta, ma
548; CHECK-NEXT:    vssub.vx v8, v8, a0
549; CHECK-NEXT:    ret
550  %elt.head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0
551  %vb = shufflevector <vscale x 4 x i32> %elt.head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
552  %v = call <vscale x 4 x i32> @llvm.ssub.sat.nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb)
553  ret <vscale x 4 x i32> %v
554}
555
556define <vscale x 4 x i32> @ssub_nxv4i32_vi(<vscale x 4 x i32> %va) {
557; CHECK-LABEL: ssub_nxv4i32_vi:
558; CHECK:       # %bb.0:
559; CHECK-NEXT:    li a0, 1
560; CHECK-NEXT:    vsetvli a1, zero, e32, m2, ta, ma
561; CHECK-NEXT:    vssub.vx v8, v8, a0
562; CHECK-NEXT:    ret
563  %v = call <vscale x 4 x i32> @llvm.ssub.sat.nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> splat (i32 1))
564  ret <vscale x 4 x i32> %v
565}
566
567declare <vscale x 8 x i32> @llvm.ssub.sat.nxv8i32(<vscale x 8 x i32>, <vscale x 8 x i32>)
568
569define <vscale x 8 x i32> @ssub_nxv8i32_vv(<vscale x 8 x i32> %va, <vscale x 8 x i32> %b) {
570; CHECK-LABEL: ssub_nxv8i32_vv:
571; CHECK:       # %bb.0:
572; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, ma
573; CHECK-NEXT:    vssub.vv v8, v8, v12
574; CHECK-NEXT:    ret
575  %v = call <vscale x 8 x i32> @llvm.ssub.sat.nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %b)
576  ret <vscale x 8 x i32> %v
577}
578
579define <vscale x 8 x i32> @ssub_nxv8i32_vx(<vscale x 8 x i32> %va, i32 %b) {
580; CHECK-LABEL: ssub_nxv8i32_vx:
581; CHECK:       # %bb.0:
582; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, ma
583; CHECK-NEXT:    vssub.vx v8, v8, a0
584; CHECK-NEXT:    ret
585  %elt.head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
586  %vb = shufflevector <vscale x 8 x i32> %elt.head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
587  %v = call <vscale x 8 x i32> @llvm.ssub.sat.nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb)
588  ret <vscale x 8 x i32> %v
589}
590
591define <vscale x 8 x i32> @ssub_nxv8i32_vi(<vscale x 8 x i32> %va) {
592; CHECK-LABEL: ssub_nxv8i32_vi:
593; CHECK:       # %bb.0:
594; CHECK-NEXT:    li a0, 1
595; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, ma
596; CHECK-NEXT:    vssub.vx v8, v8, a0
597; CHECK-NEXT:    ret
598  %v = call <vscale x 8 x i32> @llvm.ssub.sat.nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> splat (i32 1))
599  ret <vscale x 8 x i32> %v
600}
601
602declare <vscale x 16 x i32> @llvm.ssub.sat.nxv16i32(<vscale x 16 x i32>, <vscale x 16 x i32>)
603
604define <vscale x 16 x i32> @ssub_nxv16i32_vv(<vscale x 16 x i32> %va, <vscale x 16 x i32> %b) {
605; CHECK-LABEL: ssub_nxv16i32_vv:
606; CHECK:       # %bb.0:
607; CHECK-NEXT:    vsetvli a0, zero, e32, m8, ta, ma
608; CHECK-NEXT:    vssub.vv v8, v8, v16
609; CHECK-NEXT:    ret
610  %v = call <vscale x 16 x i32> @llvm.ssub.sat.nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %b)
611  ret <vscale x 16 x i32> %v
612}
613
614define <vscale x 16 x i32> @ssub_nxv16i32_vx(<vscale x 16 x i32> %va, i32 %b) {
615; CHECK-LABEL: ssub_nxv16i32_vx:
616; CHECK:       # %bb.0:
617; CHECK-NEXT:    vsetvli a1, zero, e32, m8, ta, ma
618; CHECK-NEXT:    vssub.vx v8, v8, a0
619; CHECK-NEXT:    ret
620  %elt.head = insertelement <vscale x 16 x i32> poison, i32 %b, i32 0
621  %vb = shufflevector <vscale x 16 x i32> %elt.head, <vscale x 16 x i32> poison, <vscale x 16 x i32> zeroinitializer
622  %v = call <vscale x 16 x i32> @llvm.ssub.sat.nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %vb)
623  ret <vscale x 16 x i32> %v
624}
625
626define <vscale x 16 x i32> @ssub_nxv16i32_vi(<vscale x 16 x i32> %va) {
627; CHECK-LABEL: ssub_nxv16i32_vi:
628; CHECK:       # %bb.0:
629; CHECK-NEXT:    li a0, 1
630; CHECK-NEXT:    vsetvli a1, zero, e32, m8, ta, ma
631; CHECK-NEXT:    vssub.vx v8, v8, a0
632; CHECK-NEXT:    ret
633  %v = call <vscale x 16 x i32> @llvm.ssub.sat.nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> splat (i32 1))
634  ret <vscale x 16 x i32> %v
635}
636
637declare <vscale x 1 x i64> @llvm.ssub.sat.nxv1i64(<vscale x 1 x i64>, <vscale x 1 x i64>)
638
639define <vscale x 1 x i64> @ssub_nxv1i64_vv(<vscale x 1 x i64> %va, <vscale x 1 x i64> %b) {
640; CHECK-LABEL: ssub_nxv1i64_vv:
641; CHECK:       # %bb.0:
642; CHECK-NEXT:    vsetvli a0, zero, e64, m1, ta, ma
643; CHECK-NEXT:    vssub.vv v8, v8, v9
644; CHECK-NEXT:    ret
645  %v = call <vscale x 1 x i64> @llvm.ssub.sat.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %b)
646  ret <vscale x 1 x i64> %v
647}
648
649define <vscale x 1 x i64> @ssub_nxv1i64_vx(<vscale x 1 x i64> %va, i64 %b) {
650; RV32-LABEL: ssub_nxv1i64_vx:
651; RV32:       # %bb.0:
652; RV32-NEXT:    addi sp, sp, -16
653; RV32-NEXT:    .cfi_def_cfa_offset 16
654; RV32-NEXT:    sw a0, 8(sp)
655; RV32-NEXT:    sw a1, 12(sp)
656; RV32-NEXT:    addi a0, sp, 8
657; RV32-NEXT:    vsetvli a1, zero, e64, m1, ta, ma
658; RV32-NEXT:    vlse64.v v9, (a0), zero
659; RV32-NEXT:    vssub.vv v8, v8, v9
660; RV32-NEXT:    addi sp, sp, 16
661; RV32-NEXT:    .cfi_def_cfa_offset 0
662; RV32-NEXT:    ret
663;
664; RV64-LABEL: ssub_nxv1i64_vx:
665; RV64:       # %bb.0:
666; RV64-NEXT:    vsetvli a1, zero, e64, m1, ta, ma
667; RV64-NEXT:    vssub.vx v8, v8, a0
668; RV64-NEXT:    ret
669  %elt.head = insertelement <vscale x 1 x i64> poison, i64 %b, i32 0
670  %vb = shufflevector <vscale x 1 x i64> %elt.head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer
671  %v = call <vscale x 1 x i64> @llvm.ssub.sat.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb)
672  ret <vscale x 1 x i64> %v
673}
674
675define <vscale x 1 x i64> @ssub_nxv1i64_vi(<vscale x 1 x i64> %va) {
676; CHECK-LABEL: ssub_nxv1i64_vi:
677; CHECK:       # %bb.0:
678; CHECK-NEXT:    li a0, 1
679; CHECK-NEXT:    vsetvli a1, zero, e64, m1, ta, ma
680; CHECK-NEXT:    vssub.vx v8, v8, a0
681; CHECK-NEXT:    ret
682  %v = call <vscale x 1 x i64> @llvm.ssub.sat.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> splat (i64 1))
683  ret <vscale x 1 x i64> %v
684}
685
686declare <vscale x 2 x i64> @llvm.ssub.sat.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>)
687
688define <vscale x 2 x i64> @ssub_nxv2i64_vv(<vscale x 2 x i64> %va, <vscale x 2 x i64> %b) {
689; CHECK-LABEL: ssub_nxv2i64_vv:
690; CHECK:       # %bb.0:
691; CHECK-NEXT:    vsetvli a0, zero, e64, m2, ta, ma
692; CHECK-NEXT:    vssub.vv v8, v8, v10
693; CHECK-NEXT:    ret
694  %v = call <vscale x 2 x i64> @llvm.ssub.sat.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %b)
695  ret <vscale x 2 x i64> %v
696}
697
698define <vscale x 2 x i64> @ssub_nxv2i64_vx(<vscale x 2 x i64> %va, i64 %b) {
699; RV32-LABEL: ssub_nxv2i64_vx:
700; RV32:       # %bb.0:
701; RV32-NEXT:    addi sp, sp, -16
702; RV32-NEXT:    .cfi_def_cfa_offset 16
703; RV32-NEXT:    sw a0, 8(sp)
704; RV32-NEXT:    sw a1, 12(sp)
705; RV32-NEXT:    addi a0, sp, 8
706; RV32-NEXT:    vsetvli a1, zero, e64, m2, ta, ma
707; RV32-NEXT:    vlse64.v v10, (a0), zero
708; RV32-NEXT:    vssub.vv v8, v8, v10
709; RV32-NEXT:    addi sp, sp, 16
710; RV32-NEXT:    .cfi_def_cfa_offset 0
711; RV32-NEXT:    ret
712;
713; RV64-LABEL: ssub_nxv2i64_vx:
714; RV64:       # %bb.0:
715; RV64-NEXT:    vsetvli a1, zero, e64, m2, ta, ma
716; RV64-NEXT:    vssub.vx v8, v8, a0
717; RV64-NEXT:    ret
718  %elt.head = insertelement <vscale x 2 x i64> poison, i64 %b, i32 0
719  %vb = shufflevector <vscale x 2 x i64> %elt.head, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
720  %v = call <vscale x 2 x i64> @llvm.ssub.sat.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb)
721  ret <vscale x 2 x i64> %v
722}
723
724define <vscale x 2 x i64> @ssub_nxv2i64_vi(<vscale x 2 x i64> %va) {
725; CHECK-LABEL: ssub_nxv2i64_vi:
726; CHECK:       # %bb.0:
727; CHECK-NEXT:    li a0, 1
728; CHECK-NEXT:    vsetvli a1, zero, e64, m2, ta, ma
729; CHECK-NEXT:    vssub.vx v8, v8, a0
730; CHECK-NEXT:    ret
731  %v = call <vscale x 2 x i64> @llvm.ssub.sat.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> splat (i64 1))
732  ret <vscale x 2 x i64> %v
733}
734
735declare <vscale x 4 x i64> @llvm.ssub.sat.nxv4i64(<vscale x 4 x i64>, <vscale x 4 x i64>)
736
737define <vscale x 4 x i64> @ssub_nxv4i64_vv(<vscale x 4 x i64> %va, <vscale x 4 x i64> %b) {
738; CHECK-LABEL: ssub_nxv4i64_vv:
739; CHECK:       # %bb.0:
740; CHECK-NEXT:    vsetvli a0, zero, e64, m4, ta, ma
741; CHECK-NEXT:    vssub.vv v8, v8, v12
742; CHECK-NEXT:    ret
743  %v = call <vscale x 4 x i64> @llvm.ssub.sat.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %b)
744  ret <vscale x 4 x i64> %v
745}
746
747define <vscale x 4 x i64> @ssub_nxv4i64_vx(<vscale x 4 x i64> %va, i64 %b) {
748; RV32-LABEL: ssub_nxv4i64_vx:
749; RV32:       # %bb.0:
750; RV32-NEXT:    addi sp, sp, -16
751; RV32-NEXT:    .cfi_def_cfa_offset 16
752; RV32-NEXT:    sw a0, 8(sp)
753; RV32-NEXT:    sw a1, 12(sp)
754; RV32-NEXT:    addi a0, sp, 8
755; RV32-NEXT:    vsetvli a1, zero, e64, m4, ta, ma
756; RV32-NEXT:    vlse64.v v12, (a0), zero
757; RV32-NEXT:    vssub.vv v8, v8, v12
758; RV32-NEXT:    addi sp, sp, 16
759; RV32-NEXT:    .cfi_def_cfa_offset 0
760; RV32-NEXT:    ret
761;
762; RV64-LABEL: ssub_nxv4i64_vx:
763; RV64:       # %bb.0:
764; RV64-NEXT:    vsetvli a1, zero, e64, m4, ta, ma
765; RV64-NEXT:    vssub.vx v8, v8, a0
766; RV64-NEXT:    ret
767  %elt.head = insertelement <vscale x 4 x i64> poison, i64 %b, i32 0
768  %vb = shufflevector <vscale x 4 x i64> %elt.head, <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer
769  %v = call <vscale x 4 x i64> @llvm.ssub.sat.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb)
770  ret <vscale x 4 x i64> %v
771}
772
773define <vscale x 4 x i64> @ssub_nxv4i64_vi(<vscale x 4 x i64> %va) {
774; CHECK-LABEL: ssub_nxv4i64_vi:
775; CHECK:       # %bb.0:
776; CHECK-NEXT:    li a0, 1
777; CHECK-NEXT:    vsetvli a1, zero, e64, m4, ta, ma
778; CHECK-NEXT:    vssub.vx v8, v8, a0
779; CHECK-NEXT:    ret
780  %v = call <vscale x 4 x i64> @llvm.ssub.sat.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> splat (i64 1))
781  ret <vscale x 4 x i64> %v
782}
783
784declare <vscale x 8 x i64> @llvm.ssub.sat.nxv8i64(<vscale x 8 x i64>, <vscale x 8 x i64>)
785
786define <vscale x 8 x i64> @ssub_nxv8i64_vv(<vscale x 8 x i64> %va, <vscale x 8 x i64> %b) {
787; CHECK-LABEL: ssub_nxv8i64_vv:
788; CHECK:       # %bb.0:
789; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, ma
790; CHECK-NEXT:    vssub.vv v8, v8, v16
791; CHECK-NEXT:    ret
792  %v = call <vscale x 8 x i64> @llvm.ssub.sat.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %b)
793  ret <vscale x 8 x i64> %v
794}
795
796define <vscale x 8 x i64> @ssub_nxv8i64_vx(<vscale x 8 x i64> %va, i64 %b) {
797; RV32-LABEL: ssub_nxv8i64_vx:
798; RV32:       # %bb.0:
799; RV32-NEXT:    addi sp, sp, -16
800; RV32-NEXT:    .cfi_def_cfa_offset 16
801; RV32-NEXT:    sw a0, 8(sp)
802; RV32-NEXT:    sw a1, 12(sp)
803; RV32-NEXT:    addi a0, sp, 8
804; RV32-NEXT:    vsetvli a1, zero, e64, m8, ta, ma
805; RV32-NEXT:    vlse64.v v16, (a0), zero
806; RV32-NEXT:    vssub.vv v8, v8, v16
807; RV32-NEXT:    addi sp, sp, 16
808; RV32-NEXT:    .cfi_def_cfa_offset 0
809; RV32-NEXT:    ret
810;
811; RV64-LABEL: ssub_nxv8i64_vx:
812; RV64:       # %bb.0:
813; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, ma
814; RV64-NEXT:    vssub.vx v8, v8, a0
815; RV64-NEXT:    ret
816  %elt.head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
817  %vb = shufflevector <vscale x 8 x i64> %elt.head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
818  %v = call <vscale x 8 x i64> @llvm.ssub.sat.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb)
819  ret <vscale x 8 x i64> %v
820}
821
822define <vscale x 8 x i64> @ssub_nxv8i64_vi(<vscale x 8 x i64> %va) {
823; CHECK-LABEL: ssub_nxv8i64_vi:
824; CHECK:       # %bb.0:
825; CHECK-NEXT:    li a0, 1
826; CHECK-NEXT:    vsetvli a1, zero, e64, m8, ta, ma
827; CHECK-NEXT:    vssub.vx v8, v8, a0
828; CHECK-NEXT:    ret
829  %v = call <vscale x 8 x i64> @llvm.ssub.sat.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> splat (i64 1))
830  ret <vscale x 8 x i64> %v
831}
832