xref: /llvm-project/llvm/test/CodeGen/RISCV/rvv/vsrl-sdnode.ll (revision d8d131dfa99762ccdd2116661980b7d0493cd7b5) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s
3; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s
4
5define <vscale x 1 x i8> @vsrl_vx_nxv1i8(<vscale x 1 x i8> %va, i8 signext %b) {
6; CHECK-LABEL: vsrl_vx_nxv1i8:
7; CHECK:       # %bb.0:
8; CHECK-NEXT:    vsetvli a1, zero, e8, mf8, ta, ma
9; CHECK-NEXT:    vsrl.vx v8, v8, a0
10; CHECK-NEXT:    ret
11  %head = insertelement <vscale x 1 x i8> poison, i8 %b, i32 0
12  %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer
13  %vc = lshr <vscale x 1 x i8> %va, %splat
14  ret <vscale x 1 x i8> %vc
15}
16
17define <vscale x 1 x i8> @vsrl_vx_nxv1i8_0(<vscale x 1 x i8> %va) {
18; CHECK-LABEL: vsrl_vx_nxv1i8_0:
19; CHECK:       # %bb.0:
20; CHECK-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
21; CHECK-NEXT:    vsrl.vi v8, v8, 6
22; CHECK-NEXT:    ret
23  %vc = lshr <vscale x 1 x i8> %va, splat (i8 6)
24  ret <vscale x 1 x i8> %vc
25}
26
27define <vscale x 2 x i8> @vsrl_vx_nxv2i8(<vscale x 2 x i8> %va, i8 signext %b) {
28; CHECK-LABEL: vsrl_vx_nxv2i8:
29; CHECK:       # %bb.0:
30; CHECK-NEXT:    vsetvli a1, zero, e8, mf4, ta, ma
31; CHECK-NEXT:    vsrl.vx v8, v8, a0
32; CHECK-NEXT:    ret
33  %head = insertelement <vscale x 2 x i8> poison, i8 %b, i32 0
34  %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> poison, <vscale x 2 x i32> zeroinitializer
35  %vc = lshr <vscale x 2 x i8> %va, %splat
36  ret <vscale x 2 x i8> %vc
37}
38
39define <vscale x 2 x i8> @vsrl_vx_nxv2i8_0(<vscale x 2 x i8> %va) {
40; CHECK-LABEL: vsrl_vx_nxv2i8_0:
41; CHECK:       # %bb.0:
42; CHECK-NEXT:    vsetvli a0, zero, e8, mf4, ta, ma
43; CHECK-NEXT:    vsrl.vi v8, v8, 6
44; CHECK-NEXT:    ret
45  %vc = lshr <vscale x 2 x i8> %va, splat (i8 6)
46  ret <vscale x 2 x i8> %vc
47}
48
49define <vscale x 4 x i8> @vsrl_vx_nxv4i8(<vscale x 4 x i8> %va, i8 signext %b) {
50; CHECK-LABEL: vsrl_vx_nxv4i8:
51; CHECK:       # %bb.0:
52; CHECK-NEXT:    vsetvli a1, zero, e8, mf2, ta, ma
53; CHECK-NEXT:    vsrl.vx v8, v8, a0
54; CHECK-NEXT:    ret
55  %head = insertelement <vscale x 4 x i8> poison, i8 %b, i32 0
56  %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> poison, <vscale x 4 x i32> zeroinitializer
57  %vc = lshr <vscale x 4 x i8> %va, %splat
58  ret <vscale x 4 x i8> %vc
59}
60
61define <vscale x 4 x i8> @vsrl_vx_nxv4i8_0(<vscale x 4 x i8> %va) {
62; CHECK-LABEL: vsrl_vx_nxv4i8_0:
63; CHECK:       # %bb.0:
64; CHECK-NEXT:    vsetvli a0, zero, e8, mf2, ta, ma
65; CHECK-NEXT:    vsrl.vi v8, v8, 6
66; CHECK-NEXT:    ret
67  %vc = lshr <vscale x 4 x i8> %va, splat (i8 6)
68  ret <vscale x 4 x i8> %vc
69}
70
71define <vscale x 8 x i8> @vsrl_vx_nxv8i8(<vscale x 8 x i8> %va, i8 signext %b) {
72; CHECK-LABEL: vsrl_vx_nxv8i8:
73; CHECK:       # %bb.0:
74; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, ma
75; CHECK-NEXT:    vsrl.vx v8, v8, a0
76; CHECK-NEXT:    ret
77  %head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0
78  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
79  %vc = lshr <vscale x 8 x i8> %va, %splat
80  ret <vscale x 8 x i8> %vc
81}
82
83define <vscale x 8 x i8> @vsrl_vx_nxv8i8_0(<vscale x 8 x i8> %va) {
84; CHECK-LABEL: vsrl_vx_nxv8i8_0:
85; CHECK:       # %bb.0:
86; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, ma
87; CHECK-NEXT:    vsrl.vi v8, v8, 6
88; CHECK-NEXT:    ret
89  %vc = lshr <vscale x 8 x i8> %va, splat (i8 6)
90  ret <vscale x 8 x i8> %vc
91}
92
93define <vscale x 16 x i8> @vsrl_vx_nxv16i8(<vscale x 16 x i8> %va, i8 signext %b) {
94; CHECK-LABEL: vsrl_vx_nxv16i8:
95; CHECK:       # %bb.0:
96; CHECK-NEXT:    vsetvli a1, zero, e8, m2, ta, ma
97; CHECK-NEXT:    vsrl.vx v8, v8, a0
98; CHECK-NEXT:    ret
99  %head = insertelement <vscale x 16 x i8> poison, i8 %b, i32 0
100  %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
101  %vc = lshr <vscale x 16 x i8> %va, %splat
102  ret <vscale x 16 x i8> %vc
103}
104
105define <vscale x 16 x i8> @vsrl_vx_nxv16i8_0(<vscale x 16 x i8> %va) {
106; CHECK-LABEL: vsrl_vx_nxv16i8_0:
107; CHECK:       # %bb.0:
108; CHECK-NEXT:    vsetvli a0, zero, e8, m2, ta, ma
109; CHECK-NEXT:    vsrl.vi v8, v8, 6
110; CHECK-NEXT:    ret
111  %vc = lshr <vscale x 16 x i8> %va, splat (i8 6)
112  ret <vscale x 16 x i8> %vc
113}
114
115define <vscale x 32 x i8> @vsrl_vx_nxv32i8(<vscale x 32 x i8> %va, i8 signext %b) {
116; CHECK-LABEL: vsrl_vx_nxv32i8:
117; CHECK:       # %bb.0:
118; CHECK-NEXT:    vsetvli a1, zero, e8, m4, ta, ma
119; CHECK-NEXT:    vsrl.vx v8, v8, a0
120; CHECK-NEXT:    ret
121  %head = insertelement <vscale x 32 x i8> poison, i8 %b, i32 0
122  %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> poison, <vscale x 32 x i32> zeroinitializer
123  %vc = lshr <vscale x 32 x i8> %va, %splat
124  ret <vscale x 32 x i8> %vc
125}
126
127define <vscale x 32 x i8> @vsrl_vx_nxv32i8_0(<vscale x 32 x i8> %va) {
128; CHECK-LABEL: vsrl_vx_nxv32i8_0:
129; CHECK:       # %bb.0:
130; CHECK-NEXT:    vsetvli a0, zero, e8, m4, ta, ma
131; CHECK-NEXT:    vsrl.vi v8, v8, 6
132; CHECK-NEXT:    ret
133  %vc = lshr <vscale x 32 x i8> %va, splat (i8 6)
134  ret <vscale x 32 x i8> %vc
135}
136
137define <vscale x 64 x i8> @vsrl_vx_nxv64i8(<vscale x 64 x i8> %va, i8 signext %b) {
138; CHECK-LABEL: vsrl_vx_nxv64i8:
139; CHECK:       # %bb.0:
140; CHECK-NEXT:    vsetvli a1, zero, e8, m8, ta, ma
141; CHECK-NEXT:    vsrl.vx v8, v8, a0
142; CHECK-NEXT:    ret
143  %head = insertelement <vscale x 64 x i8> poison, i8 %b, i32 0
144  %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> poison, <vscale x 64 x i32> zeroinitializer
145  %vc = lshr <vscale x 64 x i8> %va, %splat
146  ret <vscale x 64 x i8> %vc
147}
148
149define <vscale x 64 x i8> @vsrl_vx_nxv64i8_0(<vscale x 64 x i8> %va) {
150; CHECK-LABEL: vsrl_vx_nxv64i8_0:
151; CHECK:       # %bb.0:
152; CHECK-NEXT:    vsetvli a0, zero, e8, m8, ta, ma
153; CHECK-NEXT:    vsrl.vi v8, v8, 6
154; CHECK-NEXT:    ret
155  %vc = lshr <vscale x 64 x i8> %va, splat (i8 6)
156  ret <vscale x 64 x i8> %vc
157}
158
159define <vscale x 1 x i16> @vsrl_vx_nxv1i16(<vscale x 1 x i16> %va, i16 signext %b) {
160; CHECK-LABEL: vsrl_vx_nxv1i16:
161; CHECK:       # %bb.0:
162; CHECK-NEXT:    vsetvli a1, zero, e16, mf4, ta, ma
163; CHECK-NEXT:    vsrl.vx v8, v8, a0
164; CHECK-NEXT:    ret
165  %head = insertelement <vscale x 1 x i16> poison, i16 %b, i32 0
166  %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer
167  %vc = lshr <vscale x 1 x i16> %va, %splat
168  ret <vscale x 1 x i16> %vc
169}
170
171define <vscale x 1 x i16> @vsrl_vx_nxv1i16_0(<vscale x 1 x i16> %va) {
172; CHECK-LABEL: vsrl_vx_nxv1i16_0:
173; CHECK:       # %bb.0:
174; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, ma
175; CHECK-NEXT:    vsrl.vi v8, v8, 6
176; CHECK-NEXT:    ret
177  %vc = lshr <vscale x 1 x i16> %va, splat (i16 6)
178  ret <vscale x 1 x i16> %vc
179}
180
181define <vscale x 2 x i16> @vsrl_vx_nxv2i16(<vscale x 2 x i16> %va, i16 signext %b) {
182; CHECK-LABEL: vsrl_vx_nxv2i16:
183; CHECK:       # %bb.0:
184; CHECK-NEXT:    vsetvli a1, zero, e16, mf2, ta, ma
185; CHECK-NEXT:    vsrl.vx v8, v8, a0
186; CHECK-NEXT:    ret
187  %head = insertelement <vscale x 2 x i16> poison, i16 %b, i32 0
188  %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer
189  %vc = lshr <vscale x 2 x i16> %va, %splat
190  ret <vscale x 2 x i16> %vc
191}
192
193define <vscale x 2 x i16> @vsrl_vx_nxv2i16_0(<vscale x 2 x i16> %va) {
194; CHECK-LABEL: vsrl_vx_nxv2i16_0:
195; CHECK:       # %bb.0:
196; CHECK-NEXT:    vsetvli a0, zero, e16, mf2, ta, ma
197; CHECK-NEXT:    vsrl.vi v8, v8, 6
198; CHECK-NEXT:    ret
199  %vc = lshr <vscale x 2 x i16> %va, splat (i16 6)
200  ret <vscale x 2 x i16> %vc
201}
202
203define <vscale x 4 x i16> @vsrl_vx_nxv4i16(<vscale x 4 x i16> %va, i16 signext %b) {
204; CHECK-LABEL: vsrl_vx_nxv4i16:
205; CHECK:       # %bb.0:
206; CHECK-NEXT:    vsetvli a1, zero, e16, m1, ta, ma
207; CHECK-NEXT:    vsrl.vx v8, v8, a0
208; CHECK-NEXT:    ret
209  %head = insertelement <vscale x 4 x i16> poison, i16 %b, i32 0
210  %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> poison, <vscale x 4 x i32> zeroinitializer
211  %vc = lshr <vscale x 4 x i16> %va, %splat
212  ret <vscale x 4 x i16> %vc
213}
214
215define <vscale x 4 x i16> @vsrl_vx_nxv4i16_0(<vscale x 4 x i16> %va) {
216; CHECK-LABEL: vsrl_vx_nxv4i16_0:
217; CHECK:       # %bb.0:
218; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, ma
219; CHECK-NEXT:    vsrl.vi v8, v8, 6
220; CHECK-NEXT:    ret
221  %vc = lshr <vscale x 4 x i16> %va, splat (i16 6)
222  ret <vscale x 4 x i16> %vc
223}
224
225define <vscale x 8 x i16> @vsrl_vx_nxv8i16(<vscale x 8 x i16> %va, i16 signext %b) {
226; CHECK-LABEL: vsrl_vx_nxv8i16:
227; CHECK:       # %bb.0:
228; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, ma
229; CHECK-NEXT:    vsrl.vx v8, v8, a0
230; CHECK-NEXT:    ret
231  %head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0
232  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
233  %vc = lshr <vscale x 8 x i16> %va, %splat
234  ret <vscale x 8 x i16> %vc
235}
236
237define <vscale x 8 x i16> @vsrl_vx_nxv8i16_0(<vscale x 8 x i16> %va) {
238; CHECK-LABEL: vsrl_vx_nxv8i16_0:
239; CHECK:       # %bb.0:
240; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, ma
241; CHECK-NEXT:    vsrl.vi v8, v8, 6
242; CHECK-NEXT:    ret
243  %vc = lshr <vscale x 8 x i16> %va, splat (i16 6)
244  ret <vscale x 8 x i16> %vc
245}
246
247define <vscale x 16 x i16> @vsrl_vx_nxv16i16(<vscale x 16 x i16> %va, i16 signext %b) {
248; CHECK-LABEL: vsrl_vx_nxv16i16:
249; CHECK:       # %bb.0:
250; CHECK-NEXT:    vsetvli a1, zero, e16, m4, ta, ma
251; CHECK-NEXT:    vsrl.vx v8, v8, a0
252; CHECK-NEXT:    ret
253  %head = insertelement <vscale x 16 x i16> poison, i16 %b, i32 0
254  %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> poison, <vscale x 16 x i32> zeroinitializer
255  %vc = lshr <vscale x 16 x i16> %va, %splat
256  ret <vscale x 16 x i16> %vc
257}
258
259define <vscale x 16 x i16> @vsrl_vx_nxv16i16_0(<vscale x 16 x i16> %va) {
260; CHECK-LABEL: vsrl_vx_nxv16i16_0:
261; CHECK:       # %bb.0:
262; CHECK-NEXT:    vsetvli a0, zero, e16, m4, ta, ma
263; CHECK-NEXT:    vsrl.vi v8, v8, 6
264; CHECK-NEXT:    ret
265  %vc = lshr <vscale x 16 x i16> %va, splat (i16 6)
266  ret <vscale x 16 x i16> %vc
267}
268
269define <vscale x 32 x i16> @vsrl_vx_nxv32i16(<vscale x 32 x i16> %va, i16 signext %b) {
270; CHECK-LABEL: vsrl_vx_nxv32i16:
271; CHECK:       # %bb.0:
272; CHECK-NEXT:    vsetvli a1, zero, e16, m8, ta, ma
273; CHECK-NEXT:    vsrl.vx v8, v8, a0
274; CHECK-NEXT:    ret
275  %head = insertelement <vscale x 32 x i16> poison, i16 %b, i32 0
276  %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> poison, <vscale x 32 x i32> zeroinitializer
277  %vc = lshr <vscale x 32 x i16> %va, %splat
278  ret <vscale x 32 x i16> %vc
279}
280
281define <vscale x 32 x i16> @vsrl_vx_nxv32i16_0(<vscale x 32 x i16> %va) {
282; CHECK-LABEL: vsrl_vx_nxv32i16_0:
283; CHECK:       # %bb.0:
284; CHECK-NEXT:    vsetvli a0, zero, e16, m8, ta, ma
285; CHECK-NEXT:    vsrl.vi v8, v8, 6
286; CHECK-NEXT:    ret
287  %vc = lshr <vscale x 32 x i16> %va, splat (i16 6)
288  ret <vscale x 32 x i16> %vc
289}
290
291define <vscale x 1 x i32> @vsrl_vx_nxv1i32(<vscale x 1 x i32> %va, i32 signext %b) {
292; CHECK-LABEL: vsrl_vx_nxv1i32:
293; CHECK:       # %bb.0:
294; CHECK-NEXT:    vsetvli a1, zero, e32, mf2, ta, ma
295; CHECK-NEXT:    vsrl.vx v8, v8, a0
296; CHECK-NEXT:    ret
297  %head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 0
298  %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer
299  %vc = lshr <vscale x 1 x i32> %va, %splat
300  ret <vscale x 1 x i32> %vc
301}
302
303define <vscale x 1 x i32> @vsrl_vx_nxv1i32_0(<vscale x 1 x i32> %va) {
304; CHECK-LABEL: vsrl_vx_nxv1i32_0:
305; CHECK:       # %bb.0:
306; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, ma
307; CHECK-NEXT:    vsrl.vi v8, v8, 31
308; CHECK-NEXT:    ret
309  %vc = lshr <vscale x 1 x i32> %va, splat (i32 31)
310  ret <vscale x 1 x i32> %vc
311}
312
313define <vscale x 2 x i32> @vsrl_vx_nxv2i32(<vscale x 2 x i32> %va, i32 signext %b) {
314; CHECK-LABEL: vsrl_vx_nxv2i32:
315; CHECK:       # %bb.0:
316; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, ma
317; CHECK-NEXT:    vsrl.vx v8, v8, a0
318; CHECK-NEXT:    ret
319  %head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0
320  %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer
321  %vc = lshr <vscale x 2 x i32> %va, %splat
322  ret <vscale x 2 x i32> %vc
323}
324
325define <vscale x 2 x i32> @vsrl_vx_nxv2i32_0(<vscale x 2 x i32> %va) {
326; CHECK-LABEL: vsrl_vx_nxv2i32_0:
327; CHECK:       # %bb.0:
328; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, ma
329; CHECK-NEXT:    vsrl.vi v8, v8, 31
330; CHECK-NEXT:    ret
331  %vc = lshr <vscale x 2 x i32> %va, splat (i32 31)
332  ret <vscale x 2 x i32> %vc
333}
334
335define <vscale x 4 x i32> @vsrl_vx_nxv4i32(<vscale x 4 x i32> %va, i32 signext %b) {
336; CHECK-LABEL: vsrl_vx_nxv4i32:
337; CHECK:       # %bb.0:
338; CHECK-NEXT:    vsetvli a1, zero, e32, m2, ta, ma
339; CHECK-NEXT:    vsrl.vx v8, v8, a0
340; CHECK-NEXT:    ret
341  %head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0
342  %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
343  %vc = lshr <vscale x 4 x i32> %va, %splat
344  ret <vscale x 4 x i32> %vc
345}
346
347define <vscale x 4 x i32> @vsrl_vx_nxv4i32_0(<vscale x 4 x i32> %va) {
348; CHECK-LABEL: vsrl_vx_nxv4i32_0:
349; CHECK:       # %bb.0:
350; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, ma
351; CHECK-NEXT:    vsrl.vi v8, v8, 31
352; CHECK-NEXT:    ret
353  %vc = lshr <vscale x 4 x i32> %va, splat (i32 31)
354  ret <vscale x 4 x i32> %vc
355}
356
357define <vscale x 8 x i32> @vsrl_vx_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b) {
358; CHECK-LABEL: vsrl_vx_nxv8i32:
359; CHECK:       # %bb.0:
360; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, ma
361; CHECK-NEXT:    vsrl.vx v8, v8, a0
362; CHECK-NEXT:    ret
363  %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
364  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
365  %vc = lshr <vscale x 8 x i32> %va, %splat
366  ret <vscale x 8 x i32> %vc
367}
368
369define <vscale x 8 x i32> @vsrl_vx_nxv8i32_0(<vscale x 8 x i32> %va) {
370; CHECK-LABEL: vsrl_vx_nxv8i32_0:
371; CHECK:       # %bb.0:
372; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, ma
373; CHECK-NEXT:    vsrl.vi v8, v8, 31
374; CHECK-NEXT:    ret
375  %vc = lshr <vscale x 8 x i32> %va, splat (i32 31)
376  ret <vscale x 8 x i32> %vc
377}
378
379define <vscale x 16 x i32> @vsrl_vx_nxv16i32(<vscale x 16 x i32> %va, i32 signext %b) {
380; CHECK-LABEL: vsrl_vx_nxv16i32:
381; CHECK:       # %bb.0:
382; CHECK-NEXT:    vsetvli a1, zero, e32, m8, ta, ma
383; CHECK-NEXT:    vsrl.vx v8, v8, a0
384; CHECK-NEXT:    ret
385  %head = insertelement <vscale x 16 x i32> poison, i32 %b, i32 0
386  %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> poison, <vscale x 16 x i32> zeroinitializer
387  %vc = lshr <vscale x 16 x i32> %va, %splat
388  ret <vscale x 16 x i32> %vc
389}
390
391define <vscale x 16 x i32> @vsrl_vx_nxv16i32_0(<vscale x 16 x i32> %va) {
392; CHECK-LABEL: vsrl_vx_nxv16i32_0:
393; CHECK:       # %bb.0:
394; CHECK-NEXT:    vsetvli a0, zero, e32, m8, ta, ma
395; CHECK-NEXT:    vsrl.vi v8, v8, 31
396; CHECK-NEXT:    ret
397  %vc = lshr <vscale x 16 x i32> %va, splat (i32 31)
398  ret <vscale x 16 x i32> %vc
399}
400
401define <vscale x 1 x i64> @vsrl_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b) {
402; CHECK-LABEL: vsrl_vx_nxv1i64:
403; CHECK:       # %bb.0:
404; CHECK-NEXT:    vsetvli a1, zero, e64, m1, ta, ma
405; CHECK-NEXT:    vsrl.vx v8, v8, a0
406; CHECK-NEXT:    ret
407  %head = insertelement <vscale x 1 x i64> poison, i64 %b, i32 0
408  %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer
409  %vc = lshr <vscale x 1 x i64> %va, %splat
410  ret <vscale x 1 x i64> %vc
411}
412
413define <vscale x 1 x i64> @vsrl_vx_nxv1i64_0(<vscale x 1 x i64> %va) {
414; CHECK-LABEL: vsrl_vx_nxv1i64_0:
415; CHECK:       # %bb.0:
416; CHECK-NEXT:    vsetvli a0, zero, e64, m1, ta, ma
417; CHECK-NEXT:    vsrl.vi v8, v8, 31
418; CHECK-NEXT:    ret
419  %vc = lshr <vscale x 1 x i64> %va, splat (i64 31)
420  ret <vscale x 1 x i64> %vc
421}
422
423define <vscale x 1 x i64> @vsrl_vx_nxv1i64_1(<vscale x 1 x i64> %va) {
424; CHECK-LABEL: vsrl_vx_nxv1i64_1:
425; CHECK:       # %bb.0:
426; CHECK-NEXT:    li a0, 32
427; CHECK-NEXT:    vsetvli a1, zero, e64, m1, ta, ma
428; CHECK-NEXT:    vsrl.vx v8, v8, a0
429; CHECK-NEXT:    ret
430  %vc = lshr <vscale x 1 x i64> %va, splat (i64 32)
431  ret <vscale x 1 x i64> %vc
432}
433
434define <vscale x 2 x i64> @vsrl_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b) {
435; CHECK-LABEL: vsrl_vx_nxv2i64:
436; CHECK:       # %bb.0:
437; CHECK-NEXT:    vsetvli a1, zero, e64, m2, ta, ma
438; CHECK-NEXT:    vsrl.vx v8, v8, a0
439; CHECK-NEXT:    ret
440  %head = insertelement <vscale x 2 x i64> poison, i64 %b, i32 0
441  %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
442  %vc = lshr <vscale x 2 x i64> %va, %splat
443  ret <vscale x 2 x i64> %vc
444}
445
446define <vscale x 2 x i64> @vsrl_vx_nxv2i64_0(<vscale x 2 x i64> %va) {
447; CHECK-LABEL: vsrl_vx_nxv2i64_0:
448; CHECK:       # %bb.0:
449; CHECK-NEXT:    vsetvli a0, zero, e64, m2, ta, ma
450; CHECK-NEXT:    vsrl.vi v8, v8, 31
451; CHECK-NEXT:    ret
452  %vc = lshr <vscale x 2 x i64> %va, splat (i64 31)
453  ret <vscale x 2 x i64> %vc
454}
455
456define <vscale x 2 x i64> @vsrl_vx_nxv2i64_1(<vscale x 2 x i64> %va) {
457; CHECK-LABEL: vsrl_vx_nxv2i64_1:
458; CHECK:       # %bb.0:
459; CHECK-NEXT:    li a0, 32
460; CHECK-NEXT:    vsetvli a1, zero, e64, m2, ta, ma
461; CHECK-NEXT:    vsrl.vx v8, v8, a0
462; CHECK-NEXT:    ret
463  %vc = lshr <vscale x 2 x i64> %va, splat (i64 32)
464  ret <vscale x 2 x i64> %vc
465}
466
467define <vscale x 4 x i64> @vsrl_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b) {
468; CHECK-LABEL: vsrl_vx_nxv4i64:
469; CHECK:       # %bb.0:
470; CHECK-NEXT:    vsetvli a1, zero, e64, m4, ta, ma
471; CHECK-NEXT:    vsrl.vx v8, v8, a0
472; CHECK-NEXT:    ret
473  %head = insertelement <vscale x 4 x i64> poison, i64 %b, i32 0
474  %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer
475  %vc = lshr <vscale x 4 x i64> %va, %splat
476  ret <vscale x 4 x i64> %vc
477}
478
479define <vscale x 4 x i64> @vsrl_vx_nxv4i64_0(<vscale x 4 x i64> %va) {
480; CHECK-LABEL: vsrl_vx_nxv4i64_0:
481; CHECK:       # %bb.0:
482; CHECK-NEXT:    vsetvli a0, zero, e64, m4, ta, ma
483; CHECK-NEXT:    vsrl.vi v8, v8, 31
484; CHECK-NEXT:    ret
485  %vc = lshr <vscale x 4 x i64> %va, splat (i64 31)
486  ret <vscale x 4 x i64> %vc
487}
488
489define <vscale x 4 x i64> @vsrl_vx_nxv4i64_1(<vscale x 4 x i64> %va) {
490; CHECK-LABEL: vsrl_vx_nxv4i64_1:
491; CHECK:       # %bb.0:
492; CHECK-NEXT:    li a0, 32
493; CHECK-NEXT:    vsetvli a1, zero, e64, m4, ta, ma
494; CHECK-NEXT:    vsrl.vx v8, v8, a0
495; CHECK-NEXT:    ret
496  %vc = lshr <vscale x 4 x i64> %va, splat (i64 32)
497  ret <vscale x 4 x i64> %vc
498}
499
500define <vscale x 8 x i64> @vsrl_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
501; CHECK-LABEL: vsrl_vx_nxv8i64:
502; CHECK:       # %bb.0:
503; CHECK-NEXT:    vsetvli a1, zero, e64, m8, ta, ma
504; CHECK-NEXT:    vsrl.vx v8, v8, a0
505; CHECK-NEXT:    ret
506  %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
507  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
508  %vc = lshr <vscale x 8 x i64> %va, %splat
509  ret <vscale x 8 x i64> %vc
510}
511
512define <vscale x 8 x i64> @vsrl_vx_nxv8i64_0(<vscale x 8 x i64> %va) {
513; CHECK-LABEL: vsrl_vx_nxv8i64_0:
514; CHECK:       # %bb.0:
515; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, ma
516; CHECK-NEXT:    vsrl.vi v8, v8, 31
517; CHECK-NEXT:    ret
518  %vc = lshr <vscale x 8 x i64> %va, splat (i64 31)
519  ret <vscale x 8 x i64> %vc
520}
521
522define <vscale x 8 x i64> @vsrl_vx_nxv8i64_1(<vscale x 8 x i64> %va) {
523; CHECK-LABEL: vsrl_vx_nxv8i64_1:
524; CHECK:       # %bb.0:
525; CHECK-NEXT:    li a0, 32
526; CHECK-NEXT:    vsetvli a1, zero, e64, m8, ta, ma
527; CHECK-NEXT:    vsrl.vx v8, v8, a0
528; CHECK-NEXT:    ret
529  %vc = lshr <vscale x 8 x i64> %va, splat (i64 32)
530  ret <vscale x 8 x i64> %vc
531}
532
533define <vscale x 8 x i32> @vsrl_vv_mask_nxv4i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, <vscale x 8 x i1> %mask) {
534; CHECK-LABEL: vsrl_vv_mask_nxv4i32:
535; CHECK:       # %bb.0:
536; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
537; CHECK-NEXT:    vsrl.vv v8, v8, v12, v0.t
538; CHECK-NEXT:    ret
539  %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %vb, <vscale x 8 x i32> zeroinitializer
540  %vc = lshr <vscale x 8 x i32> %va, %vs
541  ret <vscale x 8 x i32> %vc
542}
543
544define <vscale x 8 x i32> @vsrl_vx_mask_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b, <vscale x 8 x i1> %mask) {
545; CHECK-LABEL: vsrl_vx_mask_nxv8i32:
546; CHECK:       # %bb.0:
547; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
548; CHECK-NEXT:    vsrl.vx v8, v8, a0, v0.t
549; CHECK-NEXT:    ret
550  %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
551  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
552  %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat, <vscale x 8 x i32> zeroinitializer
553  %vc = lshr <vscale x 8 x i32> %va, %vs
554  ret <vscale x 8 x i32> %vc
555}
556
557define <vscale x 8 x i32> @vsrl_vi_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %mask) {
558; CHECK-LABEL: vsrl_vi_mask_nxv8i32:
559; CHECK:       # %bb.0:
560; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
561; CHECK-NEXT:    vsrl.vi v8, v8, 31, v0.t
562; CHECK-NEXT:    ret
563  %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> splat (i32 31), <vscale x 8 x i32> zeroinitializer
564  %vc = lshr <vscale x 8 x i32> %va, %vs
565  ret <vscale x 8 x i32> %vc
566}
567