xref: /llvm-project/llvm/test/CodeGen/RISCV/rvv/vsplats-i64.ll (revision 97982a8c605fac7c86d02e641a6cd7898b3ca343) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s \
3; RUN:   | FileCheck %s --check-prefixes=CHECK,RV32V
4; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s \
5; RUN:   | FileCheck %s --check-prefixes=CHECK,RV64V
6
7define <vscale x 8 x i64> @vsplat_nxv8i64_1() {
8; CHECK-LABEL: vsplat_nxv8i64_1:
9; CHECK:       # %bb.0:
10; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, ma
11; CHECK-NEXT:    vmv.v.i v8, -1
12; CHECK-NEXT:    ret
13  ret <vscale x 8 x i64> splat (i64 -1)
14}
15
16define <vscale x 8 x i64> @vsplat_nxv8i64_2() {
17; CHECK-LABEL: vsplat_nxv8i64_2:
18; CHECK:       # %bb.0:
19; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, ma
20; CHECK-NEXT:    vmv.v.i v8, 4
21; CHECK-NEXT:    ret
22  ret <vscale x 8 x i64> splat (i64 4)
23}
24
25define <vscale x 8 x i64> @vsplat_nxv8i64_3() {
26; CHECK-LABEL: vsplat_nxv8i64_3:
27; CHECK:       # %bb.0:
28; CHECK-NEXT:    li a0, 255
29; CHECK-NEXT:    vsetvli a1, zero, e64, m8, ta, ma
30; CHECK-NEXT:    vmv.v.x v8, a0
31; CHECK-NEXT:    ret
32  ret <vscale x 8 x i64> splat (i64 255)
33}
34
35define <vscale x 8 x i64> @vsplat_nxv8i64_4() {
36; RV32V-LABEL: vsplat_nxv8i64_4:
37; RV32V:       # %bb.0:
38; RV32V-NEXT:    addi sp, sp, -16
39; RV32V-NEXT:    .cfi_def_cfa_offset 16
40; RV32V-NEXT:    lui a0, 1028096
41; RV32V-NEXT:    addi a0, a0, -1281
42; RV32V-NEXT:    sw a0, 8(sp)
43; RV32V-NEXT:    sw zero, 12(sp)
44; RV32V-NEXT:    addi a0, sp, 8
45; RV32V-NEXT:    vsetvli a1, zero, e64, m8, ta, ma
46; RV32V-NEXT:    vlse64.v v8, (a0), zero
47; RV32V-NEXT:    addi sp, sp, 16
48; RV32V-NEXT:    .cfi_def_cfa_offset 0
49; RV32V-NEXT:    ret
50;
51; RV64V-LABEL: vsplat_nxv8i64_4:
52; RV64V:       # %bb.0:
53; RV64V-NEXT:    li a0, 251
54; RV64V-NEXT:    slli a0, a0, 24
55; RV64V-NEXT:    addi a0, a0, -1281
56; RV64V-NEXT:    vsetvli a1, zero, e64, m8, ta, ma
57; RV64V-NEXT:    vmv.v.x v8, a0
58; RV64V-NEXT:    ret
59  ret <vscale x 8 x i64> splat (i64 4211079935)
60}
61
62define <vscale x 8 x i64> @vsplat_nxv8i64_5(i64 %a) {
63; RV32V-LABEL: vsplat_nxv8i64_5:
64; RV32V:       # %bb.0:
65; RV32V-NEXT:    addi sp, sp, -16
66; RV32V-NEXT:    .cfi_def_cfa_offset 16
67; RV32V-NEXT:    sw a0, 8(sp)
68; RV32V-NEXT:    sw a1, 12(sp)
69; RV32V-NEXT:    addi a0, sp, 8
70; RV32V-NEXT:    vsetvli a1, zero, e64, m8, ta, ma
71; RV32V-NEXT:    vlse64.v v8, (a0), zero
72; RV32V-NEXT:    addi sp, sp, 16
73; RV32V-NEXT:    .cfi_def_cfa_offset 0
74; RV32V-NEXT:    ret
75;
76; RV64V-LABEL: vsplat_nxv8i64_5:
77; RV64V:       # %bb.0:
78; RV64V-NEXT:    vsetvli a1, zero, e64, m8, ta, ma
79; RV64V-NEXT:    vmv.v.x v8, a0
80; RV64V-NEXT:    ret
81  %head = insertelement <vscale x 8 x i64> poison, i64 %a, i32 0
82  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
83  ret <vscale x 8 x i64> %splat
84}
85
86define <vscale x 8 x i64> @vadd_vx_nxv8i64_6(<vscale x 8 x i64> %v) {
87; CHECK-LABEL: vadd_vx_nxv8i64_6:
88; CHECK:       # %bb.0:
89; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, ma
90; CHECK-NEXT:    vadd.vi v8, v8, 2
91; CHECK-NEXT:    ret
92  %vret = add <vscale x 8 x i64> %v, splat (i64 2)
93  ret <vscale x 8 x i64> %vret
94}
95
96define <vscale x 8 x i64> @vadd_vx_nxv8i64_7(<vscale x 8 x i64> %v) {
97; CHECK-LABEL: vadd_vx_nxv8i64_7:
98; CHECK:       # %bb.0:
99; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, ma
100; CHECK-NEXT:    vadd.vi v8, v8, -1
101; CHECK-NEXT:    ret
102  %vret = add <vscale x 8 x i64> %v, splat (i64 -1)
103  ret <vscale x 8 x i64> %vret
104}
105
106define <vscale x 8 x i64> @vadd_vx_nxv8i64_8(<vscale x 8 x i64> %v) {
107; CHECK-LABEL: vadd_vx_nxv8i64_8:
108; CHECK:       # %bb.0:
109; CHECK-NEXT:    li a0, 255
110; CHECK-NEXT:    vsetvli a1, zero, e64, m8, ta, ma
111; CHECK-NEXT:    vadd.vx v8, v8, a0
112; CHECK-NEXT:    ret
113  %vret = add <vscale x 8 x i64> %v, splat (i64 255)
114  ret <vscale x 8 x i64> %vret
115}
116
117define <vscale x 8 x i64> @vadd_vx_nxv8i64_9(<vscale x 8 x i64> %v) {
118; RV32V-LABEL: vadd_vx_nxv8i64_9:
119; RV32V:       # %bb.0:
120; RV32V-NEXT:    lui a0, 503808
121; RV32V-NEXT:    addi a0, a0, -1281
122; RV32V-NEXT:    vsetvli a1, zero, e64, m8, ta, ma
123; RV32V-NEXT:    vadd.vx v8, v8, a0
124; RV32V-NEXT:    ret
125;
126; RV64V-LABEL: vadd_vx_nxv8i64_9:
127; RV64V:       # %bb.0:
128; RV64V-NEXT:    lui a0, 503808
129; RV64V-NEXT:    addiw a0, a0, -1281
130; RV64V-NEXT:    vsetvli a1, zero, e64, m8, ta, ma
131; RV64V-NEXT:    vadd.vx v8, v8, a0
132; RV64V-NEXT:    ret
133  %vret = add <vscale x 8 x i64> %v, splat (i64 2063596287)
134  ret <vscale x 8 x i64> %vret
135}
136
137define <vscale x 8 x i64> @vadd_vx_nxv8i64_10(<vscale x 8 x i64> %v) {
138; RV32V-LABEL: vadd_vx_nxv8i64_10:
139; RV32V:       # %bb.0:
140; RV32V-NEXT:    addi sp, sp, -16
141; RV32V-NEXT:    .cfi_def_cfa_offset 16
142; RV32V-NEXT:    lui a0, 1028096
143; RV32V-NEXT:    addi a0, a0, -1281
144; RV32V-NEXT:    sw a0, 8(sp)
145; RV32V-NEXT:    sw zero, 12(sp)
146; RV32V-NEXT:    addi a0, sp, 8
147; RV32V-NEXT:    vsetvli a1, zero, e64, m8, ta, ma
148; RV32V-NEXT:    vlse64.v v16, (a0), zero
149; RV32V-NEXT:    vadd.vv v8, v8, v16
150; RV32V-NEXT:    addi sp, sp, 16
151; RV32V-NEXT:    .cfi_def_cfa_offset 0
152; RV32V-NEXT:    ret
153;
154; RV64V-LABEL: vadd_vx_nxv8i64_10:
155; RV64V:       # %bb.0:
156; RV64V-NEXT:    li a0, 251
157; RV64V-NEXT:    slli a0, a0, 24
158; RV64V-NEXT:    addi a0, a0, -1281
159; RV64V-NEXT:    vsetvli a1, zero, e64, m8, ta, ma
160; RV64V-NEXT:    vadd.vx v8, v8, a0
161; RV64V-NEXT:    ret
162  %vret = add <vscale x 8 x i64> %v, splat (i64 4211079935)
163  ret <vscale x 8 x i64> %vret
164}
165
166define <vscale x 8 x i64> @vadd_vx_nxv8i64_11(<vscale x 8 x i64> %v) {
167; RV32V-LABEL: vadd_vx_nxv8i64_11:
168; RV32V:       # %bb.0:
169; RV32V-NEXT:    addi sp, sp, -16
170; RV32V-NEXT:    .cfi_def_cfa_offset 16
171; RV32V-NEXT:    li a0, 1
172; RV32V-NEXT:    lui a1, 1028096
173; RV32V-NEXT:    addi a1, a1, -1281
174; RV32V-NEXT:    sw a1, 8(sp)
175; RV32V-NEXT:    sw a0, 12(sp)
176; RV32V-NEXT:    addi a0, sp, 8
177; RV32V-NEXT:    vsetvli a1, zero, e64, m8, ta, ma
178; RV32V-NEXT:    vlse64.v v16, (a0), zero
179; RV32V-NEXT:    vadd.vv v8, v8, v16
180; RV32V-NEXT:    addi sp, sp, 16
181; RV32V-NEXT:    .cfi_def_cfa_offset 0
182; RV32V-NEXT:    ret
183;
184; RV64V-LABEL: vadd_vx_nxv8i64_11:
185; RV64V:       # %bb.0:
186; RV64V-NEXT:    li a0, 507
187; RV64V-NEXT:    slli a0, a0, 24
188; RV64V-NEXT:    addi a0, a0, -1281
189; RV64V-NEXT:    vsetvli a1, zero, e64, m8, ta, ma
190; RV64V-NEXT:    vadd.vx v8, v8, a0
191; RV64V-NEXT:    ret
192  %vret = add <vscale x 8 x i64> %v, splat (i64 8506047231)
193  ret <vscale x 8 x i64> %vret
194}
195
196define <vscale x 8 x i64> @vadd_vx_nxv8i64_12(<vscale x 8 x i64> %v, i64 %a) {
197; RV32V-LABEL: vadd_vx_nxv8i64_12:
198; RV32V:       # %bb.0:
199; RV32V-NEXT:    addi sp, sp, -16
200; RV32V-NEXT:    .cfi_def_cfa_offset 16
201; RV32V-NEXT:    sw a0, 8(sp)
202; RV32V-NEXT:    sw a1, 12(sp)
203; RV32V-NEXT:    addi a0, sp, 8
204; RV32V-NEXT:    vsetvli a1, zero, e64, m8, ta, ma
205; RV32V-NEXT:    vlse64.v v16, (a0), zero
206; RV32V-NEXT:    vadd.vv v8, v8, v16
207; RV32V-NEXT:    addi sp, sp, 16
208; RV32V-NEXT:    .cfi_def_cfa_offset 0
209; RV32V-NEXT:    ret
210;
211; RV64V-LABEL: vadd_vx_nxv8i64_12:
212; RV64V:       # %bb.0:
213; RV64V-NEXT:    vsetvli a1, zero, e64, m8, ta, ma
214; RV64V-NEXT:    vadd.vx v8, v8, a0
215; RV64V-NEXT:    ret
216  %head = insertelement <vscale x 8 x i64> poison, i64 %a, i32 0
217  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
218  %vret = add <vscale x 8 x i64> %v, %splat
219  ret <vscale x 8 x i64> %vret
220}
221
222define <vscale x 8 x i64> @vsplat_nxv8i64_13(i32 %a) {
223; RV32V-LABEL: vsplat_nxv8i64_13:
224; RV32V:       # %bb.0:
225; RV32V-NEXT:    vsetvli a1, zero, e64, m8, ta, ma
226; RV32V-NEXT:    vmv.v.x v8, a0
227; RV32V-NEXT:    ret
228;
229; RV64V-LABEL: vsplat_nxv8i64_13:
230; RV64V:       # %bb.0:
231; RV64V-NEXT:    sext.w a0, a0
232; RV64V-NEXT:    vsetvli a1, zero, e64, m8, ta, ma
233; RV64V-NEXT:    vmv.v.x v8, a0
234; RV64V-NEXT:    ret
235  %b = sext i32 %a to i64
236  %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
237  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
238  ret <vscale x 8 x i64> %splat
239}
240
241define <vscale x 8 x i64> @vsplat_nxv8i64_14(i32 %a) {
242; RV32V-LABEL: vsplat_nxv8i64_14:
243; RV32V:       # %bb.0:
244; RV32V-NEXT:    addi sp, sp, -16
245; RV32V-NEXT:    .cfi_def_cfa_offset 16
246; RV32V-NEXT:    sw a0, 8(sp)
247; RV32V-NEXT:    sw zero, 12(sp)
248; RV32V-NEXT:    addi a0, sp, 8
249; RV32V-NEXT:    vsetvli a1, zero, e64, m8, ta, ma
250; RV32V-NEXT:    vlse64.v v8, (a0), zero
251; RV32V-NEXT:    addi sp, sp, 16
252; RV32V-NEXT:    .cfi_def_cfa_offset 0
253; RV32V-NEXT:    ret
254;
255; RV64V-LABEL: vsplat_nxv8i64_14:
256; RV64V:       # %bb.0:
257; RV64V-NEXT:    slli a0, a0, 32
258; RV64V-NEXT:    srli a0, a0, 32
259; RV64V-NEXT:    vsetvli a1, zero, e64, m8, ta, ma
260; RV64V-NEXT:    vmv.v.x v8, a0
261; RV64V-NEXT:    ret
262  %b = zext i32 %a to i64
263  %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
264  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
265  ret <vscale x 8 x i64> %splat
266}
267