xref: /llvm-project/llvm/test/CodeGen/RISCV/rvv/vsm3c.ll (revision 09058654f68dd4cc5435f49502de33bac2b7f8fa) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvksh \
3; RUN:   -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
4; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvksh \
5; RUN:   -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
6
7declare <vscale x 8 x i32> @llvm.riscv.vsm3c.nxv8i32.i32(
8  <vscale x 8 x i32>,
9  <vscale x 8 x i32>,
10  iXLen,
11  iXLen,
12  iXLen)
13
14define <vscale x 8 x i32> @intrinsic_vsm3c_vi_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, iXLen %2) nounwind {
15; CHECK-LABEL: intrinsic_vsm3c_vi_nxv8i32_i32:
16; CHECK:       # %bb.0: # %entry
17; CHECK-NEXT:    vsetvli zero, a0, e32, m4, tu, ma
18; CHECK-NEXT:    vsm3c.vi v8, v12, 2
19; CHECK-NEXT:    ret
20entry:
21  %a = call <vscale x 8 x i32> @llvm.riscv.vsm3c.nxv8i32.i32(
22    <vscale x 8 x i32> %0,
23    <vscale x 8 x i32> %1,
24    iXLen 2,
25    iXLen %2,
26    iXLen 2)
27
28  ret <vscale x 8 x i32> %a
29}
30
31declare <vscale x 16 x i32> @llvm.riscv.vsm3c.nxv16i32.i32(
32  <vscale x 16 x i32>,
33  <vscale x 16 x i32>,
34  iXLen,
35  iXLen,
36  iXLen)
37
38define <vscale x 16 x i32> @intrinsic_vsm3c_vi_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, iXLen %2) nounwind {
39; CHECK-LABEL: intrinsic_vsm3c_vi_nxv16i32_i32:
40; CHECK:       # %bb.0: # %entry
41; CHECK-NEXT:    vsetvli zero, a0, e32, m8, tu, ma
42; CHECK-NEXT:    vsm3c.vi v8, v16, 2
43; CHECK-NEXT:    ret
44entry:
45  %a = call <vscale x 16 x i32> @llvm.riscv.vsm3c.nxv16i32.i32(
46    <vscale x 16 x i32> %0,
47    <vscale x 16 x i32> %1,
48    iXLen 2,
49    iXLen %2,
50    iXLen 2)
51
52  ret <vscale x 16 x i32> %a
53}
54