xref: /llvm-project/llvm/test/CodeGen/RISCV/rvv/vsitofp-vp.ll (revision b48e5f0ff3f25e8bdd3ae473dca00511336cbd6f) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+zvfh,+zvfbfmin < %s | FileCheck %s --check-prefixes=CHECK,ZVFH
3; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+zvfh,+zvfbfmin < %s | FileCheck %s --check-prefixes=CHECK,ZVFH
4; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+zvfhmin,+zvfbfmin < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN
5; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+zvfhmin,+zvfbfmin < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN
6
7define <vscale x 2 x bfloat> @vsitofp_nxv2bf16_nxv2i7(<vscale x 2 x i7> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
8; CHECK-LABEL: vsitofp_nxv2bf16_nxv2i7:
9; CHECK:       # %bb.0:
10; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, ma
11; CHECK-NEXT:    vadd.vv v8, v8, v8
12; CHECK-NEXT:    vsra.vi v8, v8, 1
13; CHECK-NEXT:    vsetvli zero, zero, e16, mf2, ta, ma
14; CHECK-NEXT:    vsext.vf2 v9, v8, v0.t
15; CHECK-NEXT:    vfwcvt.f.x.v v10, v9, v0.t
16; CHECK-NEXT:    vsetvli a0, zero, e16, mf2, ta, ma
17; CHECK-NEXT:    vfncvtbf16.f.f.w v8, v10
18; CHECK-NEXT:    ret
19  %v = call <vscale x 2 x bfloat> @llvm.vp.sitofp.nxv2bf16.nxv2i7(<vscale x 2 x i7> %va, <vscale x 2 x i1> %m, i32 %evl)
20  ret <vscale x 2 x bfloat> %v
21}
22
23declare <vscale x 2 x bfloat> @llvm.vp.sitofp.nxv2bf16.nxv2i8(<vscale x 2 x i8>, <vscale x 2 x i1>, i32)
24
25define <vscale x 2 x bfloat> @vsitofp_nxv2bf16_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
26; CHECK-LABEL: vsitofp_nxv2bf16_nxv2i8:
27; CHECK:       # %bb.0:
28; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma
29; CHECK-NEXT:    vsext.vf2 v9, v8, v0.t
30; CHECK-NEXT:    vfwcvt.f.x.v v10, v9, v0.t
31; CHECK-NEXT:    vsetvli a0, zero, e16, mf2, ta, ma
32; CHECK-NEXT:    vfncvtbf16.f.f.w v8, v10
33; CHECK-NEXT:    ret
34  %v = call <vscale x 2 x bfloat> @llvm.vp.sitofp.nxv2bf16.nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i1> %m, i32 %evl)
35  ret <vscale x 2 x bfloat> %v
36}
37
38define <vscale x 2 x bfloat> @vsitofp_nxv2bf16_nxv2i8_unmasked(<vscale x 2 x i8> %va, i32 zeroext %evl) {
39; CHECK-LABEL: vsitofp_nxv2bf16_nxv2i8_unmasked:
40; CHECK:       # %bb.0:
41; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma
42; CHECK-NEXT:    vsext.vf2 v9, v8
43; CHECK-NEXT:    vfwcvt.f.x.v v10, v9
44; CHECK-NEXT:    vsetvli a0, zero, e16, mf2, ta, ma
45; CHECK-NEXT:    vfncvtbf16.f.f.w v8, v10
46; CHECK-NEXT:    ret
47  %v = call <vscale x 2 x bfloat> @llvm.vp.sitofp.nxv2bf16.nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i1> splat (i1 true), i32 %evl)
48  ret <vscale x 2 x bfloat> %v
49}
50
51declare <vscale x 2 x bfloat> @llvm.vp.sitofp.nxv2bf16.nxv2i16(<vscale x 2 x i16>, <vscale x 2 x i1>, i32)
52
53define <vscale x 2 x bfloat> @vsitofp_nxv2bf16_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
54; CHECK-LABEL: vsitofp_nxv2bf16_nxv2i16:
55; CHECK:       # %bb.0:
56; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma
57; CHECK-NEXT:    vfwcvt.f.x.v v9, v8, v0.t
58; CHECK-NEXT:    vsetvli a0, zero, e16, mf2, ta, ma
59; CHECK-NEXT:    vfncvtbf16.f.f.w v8, v9
60; CHECK-NEXT:    ret
61  %v = call <vscale x 2 x bfloat> @llvm.vp.sitofp.nxv2bf16.nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i1> %m, i32 %evl)
62  ret <vscale x 2 x bfloat> %v
63}
64
65define <vscale x 2 x bfloat> @vsitofp_nxv2bf16_nxv2i16_unmasked(<vscale x 2 x i16> %va, i32 zeroext %evl) {
66; CHECK-LABEL: vsitofp_nxv2bf16_nxv2i16_unmasked:
67; CHECK:       # %bb.0:
68; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma
69; CHECK-NEXT:    vfwcvt.f.x.v v9, v8
70; CHECK-NEXT:    vsetvli a0, zero, e16, mf2, ta, ma
71; CHECK-NEXT:    vfncvtbf16.f.f.w v8, v9
72; CHECK-NEXT:    ret
73  %v = call <vscale x 2 x bfloat> @llvm.vp.sitofp.nxv2bf16.nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i1> splat (i1 true), i32 %evl)
74  ret <vscale x 2 x bfloat> %v
75}
76
77declare <vscale x 2 x bfloat> @llvm.vp.sitofp.nxv2bf16.nxv2i32(<vscale x 2 x i32>, <vscale x 2 x i1>, i32)
78
79define <vscale x 2 x bfloat> @vsitofp_nxv2bf16_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
80; CHECK-LABEL: vsitofp_nxv2bf16_nxv2i32:
81; CHECK:       # %bb.0:
82; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma
83; CHECK-NEXT:    vfcvt.f.x.v v9, v8, v0.t
84; CHECK-NEXT:    vsetvli a0, zero, e16, mf2, ta, ma
85; CHECK-NEXT:    vfncvtbf16.f.f.w v8, v9
86; CHECK-NEXT:    ret
87  %v = call <vscale x 2 x bfloat> @llvm.vp.sitofp.nxv2bf16.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i1> %m, i32 %evl)
88  ret <vscale x 2 x bfloat> %v
89}
90
91define <vscale x 2 x bfloat> @vsitofp_nxv2bf16_nxv2i32_unmasked(<vscale x 2 x i32> %va, i32 zeroext %evl) {
92; CHECK-LABEL: vsitofp_nxv2bf16_nxv2i32_unmasked:
93; CHECK:       # %bb.0:
94; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma
95; CHECK-NEXT:    vfcvt.f.x.v v9, v8
96; CHECK-NEXT:    vsetvli a0, zero, e16, mf2, ta, ma
97; CHECK-NEXT:    vfncvtbf16.f.f.w v8, v9
98; CHECK-NEXT:    ret
99  %v = call <vscale x 2 x bfloat> @llvm.vp.sitofp.nxv2bf16.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i1> splat (i1 true), i32 %evl)
100  ret <vscale x 2 x bfloat> %v
101}
102
103declare <vscale x 2 x bfloat> @llvm.vp.sitofp.nxv2bf16.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, i32)
104
105define <vscale x 2 x bfloat> @vsitofp_nxv2bf16_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
106; CHECK-LABEL: vsitofp_nxv2bf16_nxv2i64:
107; CHECK:       # %bb.0:
108; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma
109; CHECK-NEXT:    vfncvt.f.x.w v10, v8, v0.t
110; CHECK-NEXT:    vsetvli a0, zero, e16, mf2, ta, ma
111; CHECK-NEXT:    vfncvtbf16.f.f.w v8, v10
112; CHECK-NEXT:    ret
113  %v = call <vscale x 2 x bfloat> @llvm.vp.sitofp.nxv2bf16.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i1> %m, i32 %evl)
114  ret <vscale x 2 x bfloat> %v
115}
116
117define <vscale x 2 x bfloat> @vsitofp_nxv2bf16_nxv2i64_unmasked(<vscale x 2 x i64> %va, i32 zeroext %evl) {
118; CHECK-LABEL: vsitofp_nxv2bf16_nxv2i64_unmasked:
119; CHECK:       # %bb.0:
120; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma
121; CHECK-NEXT:    vfncvt.f.x.w v10, v8
122; CHECK-NEXT:    vsetvli a0, zero, e16, mf2, ta, ma
123; CHECK-NEXT:    vfncvtbf16.f.f.w v8, v10
124; CHECK-NEXT:    ret
125  %v = call <vscale x 2 x bfloat> @llvm.vp.sitofp.nxv2bf16.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i1> splat (i1 true), i32 %evl)
126  ret <vscale x 2 x bfloat> %v
127}
128
129declare <vscale x 2 x half> @llvm.vp.sitofp.nxv2f16.nxv2i7(<vscale x 2 x i7>, <vscale x 2 x i1>, i32)
130
131define <vscale x 2 x half> @vsitofp_nxv2f16_nxv2i7(<vscale x 2 x i7> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
132; ZVFH-LABEL: vsitofp_nxv2f16_nxv2i7:
133; ZVFH:       # %bb.0:
134; ZVFH-NEXT:    vsetvli zero, a0, e8, mf4, ta, ma
135; ZVFH-NEXT:    vadd.vv v8, v8, v8
136; ZVFH-NEXT:    vsra.vi v9, v8, 1
137; ZVFH-NEXT:    vfwcvt.f.x.v v8, v9, v0.t
138; ZVFH-NEXT:    ret
139;
140; ZVFHMIN-LABEL: vsitofp_nxv2f16_nxv2i7:
141; ZVFHMIN:       # %bb.0:
142; ZVFHMIN-NEXT:    vsetvli zero, a0, e8, mf4, ta, ma
143; ZVFHMIN-NEXT:    vadd.vv v8, v8, v8
144; ZVFHMIN-NEXT:    vsra.vi v8, v8, 1
145; ZVFHMIN-NEXT:    vsetvli zero, zero, e16, mf2, ta, ma
146; ZVFHMIN-NEXT:    vsext.vf2 v9, v8, v0.t
147; ZVFHMIN-NEXT:    vfwcvt.f.x.v v10, v9, v0.t
148; ZVFHMIN-NEXT:    vsetvli a0, zero, e16, mf2, ta, ma
149; ZVFHMIN-NEXT:    vfncvt.f.f.w v8, v10
150; ZVFHMIN-NEXT:    ret
151  %v = call <vscale x 2 x half> @llvm.vp.sitofp.nxv2f16.nxv2i7(<vscale x 2 x i7> %va, <vscale x 2 x i1> %m, i32 %evl)
152  ret <vscale x 2 x half> %v
153}
154
155declare <vscale x 2 x half> @llvm.vp.sitofp.nxv2f16.nxv2i8(<vscale x 2 x i8>, <vscale x 2 x i1>, i32)
156
157define <vscale x 2 x half> @vsitofp_nxv2f16_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
158; ZVFH-LABEL: vsitofp_nxv2f16_nxv2i8:
159; ZVFH:       # %bb.0:
160; ZVFH-NEXT:    vsetvli zero, a0, e8, mf4, ta, ma
161; ZVFH-NEXT:    vfwcvt.f.x.v v9, v8, v0.t
162; ZVFH-NEXT:    vmv1r.v v8, v9
163; ZVFH-NEXT:    ret
164;
165; ZVFHMIN-LABEL: vsitofp_nxv2f16_nxv2i8:
166; ZVFHMIN:       # %bb.0:
167; ZVFHMIN-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma
168; ZVFHMIN-NEXT:    vsext.vf2 v9, v8, v0.t
169; ZVFHMIN-NEXT:    vfwcvt.f.x.v v10, v9, v0.t
170; ZVFHMIN-NEXT:    vsetvli a0, zero, e16, mf2, ta, ma
171; ZVFHMIN-NEXT:    vfncvt.f.f.w v8, v10
172; ZVFHMIN-NEXT:    ret
173  %v = call <vscale x 2 x half> @llvm.vp.sitofp.nxv2f16.nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i1> %m, i32 %evl)
174  ret <vscale x 2 x half> %v
175}
176
177define <vscale x 2 x half> @vsitofp_nxv2f16_nxv2i8_unmasked(<vscale x 2 x i8> %va, i32 zeroext %evl) {
178; ZVFH-LABEL: vsitofp_nxv2f16_nxv2i8_unmasked:
179; ZVFH:       # %bb.0:
180; ZVFH-NEXT:    vsetvli zero, a0, e8, mf4, ta, ma
181; ZVFH-NEXT:    vfwcvt.f.x.v v9, v8
182; ZVFH-NEXT:    vmv1r.v v8, v9
183; ZVFH-NEXT:    ret
184;
185; ZVFHMIN-LABEL: vsitofp_nxv2f16_nxv2i8_unmasked:
186; ZVFHMIN:       # %bb.0:
187; ZVFHMIN-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma
188; ZVFHMIN-NEXT:    vsext.vf2 v9, v8
189; ZVFHMIN-NEXT:    vfwcvt.f.x.v v10, v9
190; ZVFHMIN-NEXT:    vsetvli a0, zero, e16, mf2, ta, ma
191; ZVFHMIN-NEXT:    vfncvt.f.f.w v8, v10
192; ZVFHMIN-NEXT:    ret
193  %v = call <vscale x 2 x half> @llvm.vp.sitofp.nxv2f16.nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i1> splat (i1 true), i32 %evl)
194  ret <vscale x 2 x half> %v
195}
196
197declare <vscale x 2 x half> @llvm.vp.sitofp.nxv2f16.nxv2i16(<vscale x 2 x i16>, <vscale x 2 x i1>, i32)
198
199define <vscale x 2 x half> @vsitofp_nxv2f16_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
200; ZVFH-LABEL: vsitofp_nxv2f16_nxv2i16:
201; ZVFH:       # %bb.0:
202; ZVFH-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma
203; ZVFH-NEXT:    vfcvt.f.x.v v8, v8, v0.t
204; ZVFH-NEXT:    ret
205;
206; ZVFHMIN-LABEL: vsitofp_nxv2f16_nxv2i16:
207; ZVFHMIN:       # %bb.0:
208; ZVFHMIN-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma
209; ZVFHMIN-NEXT:    vfwcvt.f.x.v v9, v8, v0.t
210; ZVFHMIN-NEXT:    vsetvli a0, zero, e16, mf2, ta, ma
211; ZVFHMIN-NEXT:    vfncvt.f.f.w v8, v9
212; ZVFHMIN-NEXT:    ret
213  %v = call <vscale x 2 x half> @llvm.vp.sitofp.nxv2f16.nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i1> %m, i32 %evl)
214  ret <vscale x 2 x half> %v
215}
216
217define <vscale x 2 x half> @vsitofp_nxv2f16_nxv2i16_unmasked(<vscale x 2 x i16> %va, i32 zeroext %evl) {
218; ZVFH-LABEL: vsitofp_nxv2f16_nxv2i16_unmasked:
219; ZVFH:       # %bb.0:
220; ZVFH-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma
221; ZVFH-NEXT:    vfcvt.f.x.v v8, v8
222; ZVFH-NEXT:    ret
223;
224; ZVFHMIN-LABEL: vsitofp_nxv2f16_nxv2i16_unmasked:
225; ZVFHMIN:       # %bb.0:
226; ZVFHMIN-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma
227; ZVFHMIN-NEXT:    vfwcvt.f.x.v v9, v8
228; ZVFHMIN-NEXT:    vsetvli a0, zero, e16, mf2, ta, ma
229; ZVFHMIN-NEXT:    vfncvt.f.f.w v8, v9
230; ZVFHMIN-NEXT:    ret
231  %v = call <vscale x 2 x half> @llvm.vp.sitofp.nxv2f16.nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i1> splat (i1 true), i32 %evl)
232  ret <vscale x 2 x half> %v
233}
234
235declare <vscale x 2 x half> @llvm.vp.sitofp.nxv2f16.nxv2i32(<vscale x 2 x i32>, <vscale x 2 x i1>, i32)
236
237define <vscale x 2 x half> @vsitofp_nxv2f16_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
238; ZVFH-LABEL: vsitofp_nxv2f16_nxv2i32:
239; ZVFH:       # %bb.0:
240; ZVFH-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma
241; ZVFH-NEXT:    vfncvt.f.x.w v9, v8, v0.t
242; ZVFH-NEXT:    vmv1r.v v8, v9
243; ZVFH-NEXT:    ret
244;
245; ZVFHMIN-LABEL: vsitofp_nxv2f16_nxv2i32:
246; ZVFHMIN:       # %bb.0:
247; ZVFHMIN-NEXT:    vsetvli zero, a0, e32, m1, ta, ma
248; ZVFHMIN-NEXT:    vfcvt.f.x.v v9, v8, v0.t
249; ZVFHMIN-NEXT:    vsetvli a0, zero, e16, mf2, ta, ma
250; ZVFHMIN-NEXT:    vfncvt.f.f.w v8, v9
251; ZVFHMIN-NEXT:    ret
252  %v = call <vscale x 2 x half> @llvm.vp.sitofp.nxv2f16.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i1> %m, i32 %evl)
253  ret <vscale x 2 x half> %v
254}
255
256define <vscale x 2 x half> @vsitofp_nxv2f16_nxv2i32_unmasked(<vscale x 2 x i32> %va, i32 zeroext %evl) {
257; ZVFH-LABEL: vsitofp_nxv2f16_nxv2i32_unmasked:
258; ZVFH:       # %bb.0:
259; ZVFH-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma
260; ZVFH-NEXT:    vfncvt.f.x.w v9, v8
261; ZVFH-NEXT:    vmv1r.v v8, v9
262; ZVFH-NEXT:    ret
263;
264; ZVFHMIN-LABEL: vsitofp_nxv2f16_nxv2i32_unmasked:
265; ZVFHMIN:       # %bb.0:
266; ZVFHMIN-NEXT:    vsetvli zero, a0, e32, m1, ta, ma
267; ZVFHMIN-NEXT:    vfcvt.f.x.v v9, v8
268; ZVFHMIN-NEXT:    vsetvli a0, zero, e16, mf2, ta, ma
269; ZVFHMIN-NEXT:    vfncvt.f.f.w v8, v9
270; ZVFHMIN-NEXT:    ret
271  %v = call <vscale x 2 x half> @llvm.vp.sitofp.nxv2f16.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i1> splat (i1 true), i32 %evl)
272  ret <vscale x 2 x half> %v
273}
274
275declare <vscale x 2 x half> @llvm.vp.sitofp.nxv2f16.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, i32)
276
277define <vscale x 2 x half> @vsitofp_nxv2f16_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
278; ZVFH-LABEL: vsitofp_nxv2f16_nxv2i64:
279; ZVFH:       # %bb.0:
280; ZVFH-NEXT:    vsetvli zero, a0, e32, m1, ta, ma
281; ZVFH-NEXT:    vfncvt.f.x.w v10, v8, v0.t
282; ZVFH-NEXT:    vsetvli zero, zero, e16, mf2, ta, ma
283; ZVFH-NEXT:    vfncvt.f.f.w v8, v10, v0.t
284; ZVFH-NEXT:    ret
285;
286; ZVFHMIN-LABEL: vsitofp_nxv2f16_nxv2i64:
287; ZVFHMIN:       # %bb.0:
288; ZVFHMIN-NEXT:    vsetvli zero, a0, e32, m1, ta, ma
289; ZVFHMIN-NEXT:    vfncvt.f.x.w v10, v8, v0.t
290; ZVFHMIN-NEXT:    vsetvli a0, zero, e16, mf2, ta, ma
291; ZVFHMIN-NEXT:    vfncvt.f.f.w v8, v10
292; ZVFHMIN-NEXT:    ret
293  %v = call <vscale x 2 x half> @llvm.vp.sitofp.nxv2f16.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i1> %m, i32 %evl)
294  ret <vscale x 2 x half> %v
295}
296
297define <vscale x 2 x half> @vsitofp_nxv2f16_nxv2i64_unmasked(<vscale x 2 x i64> %va, i32 zeroext %evl) {
298; ZVFH-LABEL: vsitofp_nxv2f16_nxv2i64_unmasked:
299; ZVFH:       # %bb.0:
300; ZVFH-NEXT:    vsetvli zero, a0, e32, m1, ta, ma
301; ZVFH-NEXT:    vfncvt.f.x.w v10, v8
302; ZVFH-NEXT:    vsetvli zero, zero, e16, mf2, ta, ma
303; ZVFH-NEXT:    vfncvt.f.f.w v8, v10
304; ZVFH-NEXT:    ret
305;
306; ZVFHMIN-LABEL: vsitofp_nxv2f16_nxv2i64_unmasked:
307; ZVFHMIN:       # %bb.0:
308; ZVFHMIN-NEXT:    vsetvli zero, a0, e32, m1, ta, ma
309; ZVFHMIN-NEXT:    vfncvt.f.x.w v10, v8
310; ZVFHMIN-NEXT:    vsetvli a0, zero, e16, mf2, ta, ma
311; ZVFHMIN-NEXT:    vfncvt.f.f.w v8, v10
312; ZVFHMIN-NEXT:    ret
313  %v = call <vscale x 2 x half> @llvm.vp.sitofp.nxv2f16.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i1> splat (i1 true), i32 %evl)
314  ret <vscale x 2 x half> %v
315}
316
317declare <vscale x 2 x float> @llvm.vp.sitofp.nxv2f32.nxv2i8(<vscale x 2 x i8>, <vscale x 2 x i1>, i32)
318
319define <vscale x 2 x float> @vsitofp_nxv2f32_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
320; CHECK-LABEL: vsitofp_nxv2f32_nxv2i8:
321; CHECK:       # %bb.0:
322; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma
323; CHECK-NEXT:    vsext.vf2 v9, v8, v0.t
324; CHECK-NEXT:    vfwcvt.f.x.v v8, v9, v0.t
325; CHECK-NEXT:    ret
326  %v = call <vscale x 2 x float> @llvm.vp.sitofp.nxv2f32.nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i1> %m, i32 %evl)
327  ret <vscale x 2 x float> %v
328}
329
330define <vscale x 2 x float> @vsitofp_nxv2f32_nxv2i8_unmasked(<vscale x 2 x i8> %va, i32 zeroext %evl) {
331; CHECK-LABEL: vsitofp_nxv2f32_nxv2i8_unmasked:
332; CHECK:       # %bb.0:
333; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma
334; CHECK-NEXT:    vsext.vf2 v9, v8
335; CHECK-NEXT:    vfwcvt.f.x.v v8, v9
336; CHECK-NEXT:    ret
337  %v = call <vscale x 2 x float> @llvm.vp.sitofp.nxv2f32.nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i1> splat (i1 true), i32 %evl)
338  ret <vscale x 2 x float> %v
339}
340
341declare <vscale x 2 x float> @llvm.vp.sitofp.nxv2f32.nxv2i16(<vscale x 2 x i16>, <vscale x 2 x i1>, i32)
342
343define <vscale x 2 x float> @vsitofp_nxv2f32_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
344; CHECK-LABEL: vsitofp_nxv2f32_nxv2i16:
345; CHECK:       # %bb.0:
346; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma
347; CHECK-NEXT:    vfwcvt.f.x.v v9, v8, v0.t
348; CHECK-NEXT:    vmv1r.v v8, v9
349; CHECK-NEXT:    ret
350  %v = call <vscale x 2 x float> @llvm.vp.sitofp.nxv2f32.nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i1> %m, i32 %evl)
351  ret <vscale x 2 x float> %v
352}
353
354define <vscale x 2 x float> @vsitofp_nxv2f32_nxv2i16_unmasked(<vscale x 2 x i16> %va, i32 zeroext %evl) {
355; CHECK-LABEL: vsitofp_nxv2f32_nxv2i16_unmasked:
356; CHECK:       # %bb.0:
357; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma
358; CHECK-NEXT:    vfwcvt.f.x.v v9, v8
359; CHECK-NEXT:    vmv1r.v v8, v9
360; CHECK-NEXT:    ret
361  %v = call <vscale x 2 x float> @llvm.vp.sitofp.nxv2f32.nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i1> splat (i1 true), i32 %evl)
362  ret <vscale x 2 x float> %v
363}
364
365declare <vscale x 2 x float> @llvm.vp.sitofp.nxv2f32.nxv2i32(<vscale x 2 x i32>, <vscale x 2 x i1>, i32)
366
367define <vscale x 2 x float> @vsitofp_nxv2f32_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
368; CHECK-LABEL: vsitofp_nxv2f32_nxv2i32:
369; CHECK:       # %bb.0:
370; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma
371; CHECK-NEXT:    vfcvt.f.x.v v8, v8, v0.t
372; CHECK-NEXT:    ret
373  %v = call <vscale x 2 x float> @llvm.vp.sitofp.nxv2f32.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i1> %m, i32 %evl)
374  ret <vscale x 2 x float> %v
375}
376
377define <vscale x 2 x float> @vsitofp_nxv2f32_nxv2i32_unmasked(<vscale x 2 x i32> %va, i32 zeroext %evl) {
378; CHECK-LABEL: vsitofp_nxv2f32_nxv2i32_unmasked:
379; CHECK:       # %bb.0:
380; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma
381; CHECK-NEXT:    vfcvt.f.x.v v8, v8
382; CHECK-NEXT:    ret
383  %v = call <vscale x 2 x float> @llvm.vp.sitofp.nxv2f32.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i1> splat (i1 true), i32 %evl)
384  ret <vscale x 2 x float> %v
385}
386
387declare <vscale x 2 x float> @llvm.vp.sitofp.nxv2f32.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, i32)
388
389define <vscale x 2 x float> @vsitofp_nxv2f32_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
390; CHECK-LABEL: vsitofp_nxv2f32_nxv2i64:
391; CHECK:       # %bb.0:
392; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma
393; CHECK-NEXT:    vfncvt.f.x.w v10, v8, v0.t
394; CHECK-NEXT:    vmv.v.v v8, v10
395; CHECK-NEXT:    ret
396  %v = call <vscale x 2 x float> @llvm.vp.sitofp.nxv2f32.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i1> %m, i32 %evl)
397  ret <vscale x 2 x float> %v
398}
399
400define <vscale x 2 x float> @vsitofp_nxv2f32_nxv2i64_unmasked(<vscale x 2 x i64> %va, i32 zeroext %evl) {
401; CHECK-LABEL: vsitofp_nxv2f32_nxv2i64_unmasked:
402; CHECK:       # %bb.0:
403; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma
404; CHECK-NEXT:    vfncvt.f.x.w v10, v8
405; CHECK-NEXT:    vmv.v.v v8, v10
406; CHECK-NEXT:    ret
407  %v = call <vscale x 2 x float> @llvm.vp.sitofp.nxv2f32.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i1> splat (i1 true), i32 %evl)
408  ret <vscale x 2 x float> %v
409}
410
411declare <vscale x 2 x double> @llvm.vp.sitofp.nxv2f64.nxv2i8(<vscale x 2 x i8>, <vscale x 2 x i1>, i32)
412
413define <vscale x 2 x double> @vsitofp_nxv2f64_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
414; CHECK-LABEL: vsitofp_nxv2f64_nxv2i8:
415; CHECK:       # %bb.0:
416; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma
417; CHECK-NEXT:    vsext.vf4 v10, v8, v0.t
418; CHECK-NEXT:    vfwcvt.f.x.v v8, v10, v0.t
419; CHECK-NEXT:    ret
420  %v = call <vscale x 2 x double> @llvm.vp.sitofp.nxv2f64.nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i1> %m, i32 %evl)
421  ret <vscale x 2 x double> %v
422}
423
424define <vscale x 2 x double> @vsitofp_nxv2f64_nxv2i8_unmasked(<vscale x 2 x i8> %va, i32 zeroext %evl) {
425; CHECK-LABEL: vsitofp_nxv2f64_nxv2i8_unmasked:
426; CHECK:       # %bb.0:
427; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma
428; CHECK-NEXT:    vsext.vf4 v10, v8
429; CHECK-NEXT:    vfwcvt.f.x.v v8, v10
430; CHECK-NEXT:    ret
431  %v = call <vscale x 2 x double> @llvm.vp.sitofp.nxv2f64.nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i1> splat (i1 true), i32 %evl)
432  ret <vscale x 2 x double> %v
433}
434
435declare <vscale x 2 x double> @llvm.vp.sitofp.nxv2f64.nxv2i16(<vscale x 2 x i16>, <vscale x 2 x i1>, i32)
436
437define <vscale x 2 x double> @vsitofp_nxv2f64_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
438; CHECK-LABEL: vsitofp_nxv2f64_nxv2i16:
439; CHECK:       # %bb.0:
440; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma
441; CHECK-NEXT:    vsext.vf2 v10, v8, v0.t
442; CHECK-NEXT:    vfwcvt.f.x.v v8, v10, v0.t
443; CHECK-NEXT:    ret
444  %v = call <vscale x 2 x double> @llvm.vp.sitofp.nxv2f64.nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i1> %m, i32 %evl)
445  ret <vscale x 2 x double> %v
446}
447
448define <vscale x 2 x double> @vsitofp_nxv2f64_nxv2i16_unmasked(<vscale x 2 x i16> %va, i32 zeroext %evl) {
449; CHECK-LABEL: vsitofp_nxv2f64_nxv2i16_unmasked:
450; CHECK:       # %bb.0:
451; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma
452; CHECK-NEXT:    vsext.vf2 v10, v8
453; CHECK-NEXT:    vfwcvt.f.x.v v8, v10
454; CHECK-NEXT:    ret
455  %v = call <vscale x 2 x double> @llvm.vp.sitofp.nxv2f64.nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i1> splat (i1 true), i32 %evl)
456  ret <vscale x 2 x double> %v
457}
458
459declare <vscale x 2 x double> @llvm.vp.sitofp.nxv2f64.nxv2i32(<vscale x 2 x i32>, <vscale x 2 x i1>, i32)
460
461define <vscale x 2 x double> @vsitofp_nxv2f64_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
462; CHECK-LABEL: vsitofp_nxv2f64_nxv2i32:
463; CHECK:       # %bb.0:
464; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma
465; CHECK-NEXT:    vfwcvt.f.x.v v10, v8, v0.t
466; CHECK-NEXT:    vmv2r.v v8, v10
467; CHECK-NEXT:    ret
468  %v = call <vscale x 2 x double> @llvm.vp.sitofp.nxv2f64.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i1> %m, i32 %evl)
469  ret <vscale x 2 x double> %v
470}
471
472define <vscale x 2 x double> @vsitofp_nxv2f64_nxv2i32_unmasked(<vscale x 2 x i32> %va, i32 zeroext %evl) {
473; CHECK-LABEL: vsitofp_nxv2f64_nxv2i32_unmasked:
474; CHECK:       # %bb.0:
475; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma
476; CHECK-NEXT:    vfwcvt.f.x.v v10, v8
477; CHECK-NEXT:    vmv2r.v v8, v10
478; CHECK-NEXT:    ret
479  %v = call <vscale x 2 x double> @llvm.vp.sitofp.nxv2f64.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i1> splat (i1 true), i32 %evl)
480  ret <vscale x 2 x double> %v
481}
482
483declare <vscale x 2 x double> @llvm.vp.sitofp.nxv2f64.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, i32)
484
485define <vscale x 2 x double> @vsitofp_nxv2f64_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
486; CHECK-LABEL: vsitofp_nxv2f64_nxv2i64:
487; CHECK:       # %bb.0:
488; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, ma
489; CHECK-NEXT:    vfcvt.f.x.v v8, v8, v0.t
490; CHECK-NEXT:    ret
491  %v = call <vscale x 2 x double> @llvm.vp.sitofp.nxv2f64.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i1> %m, i32 %evl)
492  ret <vscale x 2 x double> %v
493}
494
495define <vscale x 2 x double> @vsitofp_nxv2f64_nxv2i64_unmasked(<vscale x 2 x i64> %va, i32 zeroext %evl) {
496; CHECK-LABEL: vsitofp_nxv2f64_nxv2i64_unmasked:
497; CHECK:       # %bb.0:
498; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, ma
499; CHECK-NEXT:    vfcvt.f.x.v v8, v8
500; CHECK-NEXT:    ret
501  %v = call <vscale x 2 x double> @llvm.vp.sitofp.nxv2f64.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i1> splat (i1 true), i32 %evl)
502  ret <vscale x 2 x double> %v
503}
504
505declare <vscale x 32 x half> @llvm.vp.sitofp.nxv32f16.nxv32i32(<vscale x 32 x i32>, <vscale x 32 x i1>, i32)
506
507define <vscale x 32 x half> @vsitofp_nxv32f16_nxv32i32(<vscale x 32 x i32> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {
508; ZVFH-LABEL: vsitofp_nxv32f16_nxv32i32:
509; ZVFH:       # %bb.0:
510; ZVFH-NEXT:    vsetvli a1, zero, e8, mf2, ta, ma
511; ZVFH-NEXT:    vmv1r.v v24, v0
512; ZVFH-NEXT:    csrr a1, vlenb
513; ZVFH-NEXT:    srli a2, a1, 2
514; ZVFH-NEXT:    slli a1, a1, 1
515; ZVFH-NEXT:    vslidedown.vx v0, v0, a2
516; ZVFH-NEXT:    sub a2, a0, a1
517; ZVFH-NEXT:    sltu a3, a0, a2
518; ZVFH-NEXT:    addi a3, a3, -1
519; ZVFH-NEXT:    and a2, a3, a2
520; ZVFH-NEXT:    vsetvli zero, a2, e16, m4, ta, ma
521; ZVFH-NEXT:    vfncvt.f.x.w v28, v16, v0.t
522; ZVFH-NEXT:    bltu a0, a1, .LBB34_2
523; ZVFH-NEXT:  # %bb.1:
524; ZVFH-NEXT:    mv a0, a1
525; ZVFH-NEXT:  .LBB34_2:
526; ZVFH-NEXT:    vmv1r.v v0, v24
527; ZVFH-NEXT:    vsetvli zero, a0, e16, m4, ta, ma
528; ZVFH-NEXT:    vfncvt.f.x.w v24, v8, v0.t
529; ZVFH-NEXT:    vmv8r.v v8, v24
530; ZVFH-NEXT:    ret
531;
532; ZVFHMIN-LABEL: vsitofp_nxv32f16_nxv32i32:
533; ZVFHMIN:       # %bb.0:
534; ZVFHMIN-NEXT:    vsetvli a1, zero, e8, mf2, ta, ma
535; ZVFHMIN-NEXT:    vmv1r.v v7, v0
536; ZVFHMIN-NEXT:    csrr a1, vlenb
537; ZVFHMIN-NEXT:    srli a2, a1, 2
538; ZVFHMIN-NEXT:    slli a1, a1, 1
539; ZVFHMIN-NEXT:    vslidedown.vx v0, v0, a2
540; ZVFHMIN-NEXT:    sub a2, a0, a1
541; ZVFHMIN-NEXT:    sltu a3, a0, a2
542; ZVFHMIN-NEXT:    addi a3, a3, -1
543; ZVFHMIN-NEXT:    and a2, a3, a2
544; ZVFHMIN-NEXT:    vsetvli zero, a2, e32, m8, ta, ma
545; ZVFHMIN-NEXT:    vfcvt.f.x.v v24, v16, v0.t
546; ZVFHMIN-NEXT:    vsetvli a2, zero, e16, m4, ta, ma
547; ZVFHMIN-NEXT:    vfncvt.f.f.w v20, v24
548; ZVFHMIN-NEXT:    bltu a0, a1, .LBB34_2
549; ZVFHMIN-NEXT:  # %bb.1:
550; ZVFHMIN-NEXT:    mv a0, a1
551; ZVFHMIN-NEXT:  .LBB34_2:
552; ZVFHMIN-NEXT:    vmv1r.v v0, v7
553; ZVFHMIN-NEXT:    vsetvli zero, a0, e32, m8, ta, ma
554; ZVFHMIN-NEXT:    vfcvt.f.x.v v8, v8, v0.t
555; ZVFHMIN-NEXT:    vsetvli a0, zero, e16, m4, ta, ma
556; ZVFHMIN-NEXT:    vfncvt.f.f.w v16, v8
557; ZVFHMIN-NEXT:    vmv8r.v v8, v16
558; ZVFHMIN-NEXT:    ret
559  %v = call <vscale x 32 x half> @llvm.vp.sitofp.nxv32f16.nxv32i32(<vscale x 32 x i32> %va, <vscale x 32 x i1> %m, i32 %evl)
560  ret <vscale x 32 x half> %v
561}
562
563declare <vscale x 32 x float> @llvm.vp.sitofp.nxv32f32.nxv32i32(<vscale x 32 x i32>, <vscale x 32 x i1>, i32)
564
565define <vscale x 32 x float> @vsitofp_nxv32f32_nxv32i32(<vscale x 32 x i32> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {
566; CHECK-LABEL: vsitofp_nxv32f32_nxv32i32:
567; CHECK:       # %bb.0:
568; CHECK-NEXT:    vsetvli a1, zero, e8, mf2, ta, ma
569; CHECK-NEXT:    vmv1r.v v24, v0
570; CHECK-NEXT:    csrr a1, vlenb
571; CHECK-NEXT:    srli a2, a1, 2
572; CHECK-NEXT:    slli a1, a1, 1
573; CHECK-NEXT:    vslidedown.vx v0, v0, a2
574; CHECK-NEXT:    sub a2, a0, a1
575; CHECK-NEXT:    sltu a3, a0, a2
576; CHECK-NEXT:    addi a3, a3, -1
577; CHECK-NEXT:    and a2, a3, a2
578; CHECK-NEXT:    vsetvli zero, a2, e32, m8, ta, ma
579; CHECK-NEXT:    vfcvt.f.x.v v16, v16, v0.t
580; CHECK-NEXT:    bltu a0, a1, .LBB35_2
581; CHECK-NEXT:  # %bb.1:
582; CHECK-NEXT:    mv a0, a1
583; CHECK-NEXT:  .LBB35_2:
584; CHECK-NEXT:    vmv1r.v v0, v24
585; CHECK-NEXT:    vsetvli zero, a0, e32, m8, ta, ma
586; CHECK-NEXT:    vfcvt.f.x.v v8, v8, v0.t
587; CHECK-NEXT:    ret
588  %v = call <vscale x 32 x float> @llvm.vp.sitofp.nxv32f32.nxv32i32(<vscale x 32 x i32> %va, <vscale x 32 x i1> %m, i32 %evl)
589  ret <vscale x 32 x float> %v
590}
591
592define <vscale x 32 x float> @vsitofp_nxv32f32_nxv32i32_unmasked(<vscale x 32 x i32> %va, i32 zeroext %evl) {
593; CHECK-LABEL: vsitofp_nxv32f32_nxv32i32_unmasked:
594; CHECK:       # %bb.0:
595; CHECK-NEXT:    csrr a1, vlenb
596; CHECK-NEXT:    slli a1, a1, 1
597; CHECK-NEXT:    sub a2, a0, a1
598; CHECK-NEXT:    sltu a3, a0, a2
599; CHECK-NEXT:    addi a3, a3, -1
600; CHECK-NEXT:    and a2, a3, a2
601; CHECK-NEXT:    vsetvli zero, a2, e32, m8, ta, ma
602; CHECK-NEXT:    vfcvt.f.x.v v16, v16
603; CHECK-NEXT:    bltu a0, a1, .LBB36_2
604; CHECK-NEXT:  # %bb.1:
605; CHECK-NEXT:    mv a0, a1
606; CHECK-NEXT:  .LBB36_2:
607; CHECK-NEXT:    vsetvli zero, a0, e32, m8, ta, ma
608; CHECK-NEXT:    vfcvt.f.x.v v8, v8
609; CHECK-NEXT:    ret
610  %v = call <vscale x 32 x float> @llvm.vp.sitofp.nxv32f32.nxv32i32(<vscale x 32 x i32> %va, <vscale x 32 x i1> splat (i1 true), i32 %evl)
611  ret <vscale x 32 x float> %v
612}
613