xref: /llvm-project/llvm/test/CodeGen/RISCV/rvv/vsetvl-ext.ll (revision af837d44c7e126eca16426531ed54d94083f3359) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=riscv64 -mattr=+v | FileCheck %s
3
4declare i64 @llvm.riscv.vsetvli(
5  i64, i64, i64);
6
7define signext i32 @vsetvl_sext() {
8; CHECK-LABEL: vsetvl_sext:
9; CHECK:       # %bb.0:
10; CHECK-NEXT:    vsetivli a0, 1, e16, m2, ta, ma
11; CHECK-NEXT:    ret
12  %a = call i64 @llvm.riscv.vsetvli(i64 1, i64 1, i64 1)
13  %b = trunc i64 %a to i32
14  ret i32 %b
15}
16
17define zeroext i32 @vsetvl_zext() {
18; CHECK-LABEL: vsetvl_zext:
19; CHECK:       # %bb.0:
20; CHECK-NEXT:    vsetivli a0, 1, e16, m2, ta, ma
21; CHECK-NEXT:    ret
22  %a = call i64 @llvm.riscv.vsetvli(i64 1, i64 1, i64 1)
23  %b = trunc i64 %a to i32
24  ret i32 %b
25}
26
27define i64 @vsetvl_e8m1_and14bits(i64 %avl) {
28; CHECK-LABEL: vsetvl_e8m1_and14bits:
29; CHECK:       # %bb.0:
30; CHECK-NEXT:    vsetvli a0, a0, e8, m1, ta, ma
31; CHECK-NEXT:    ret
32  %a = call i64 @llvm.riscv.vsetvli(i64 %avl, i64 0, i64 0)
33  %b = and i64 %a, 16383
34  ret i64 %b
35}
36
37define i64 @vsetvl_e8m1_and13bits(i64 %avl) {
38; CHECK-LABEL: vsetvl_e8m1_and13bits:
39; CHECK:       # %bb.0:
40; CHECK-NEXT:    vsetvli a0, a0, e8, m1, ta, ma
41; CHECK-NEXT:    slli a0, a0, 51
42; CHECK-NEXT:    srli a0, a0, 51
43; CHECK-NEXT:    ret
44  %a = call i64 @llvm.riscv.vsetvli(i64 %avl, i64 0, i64 0)
45  %b = and i64 %a, 8191
46  ret i64 %b
47}
48
49define i64 @vsetvl_e8m1_constant_avl() {
50; CHECK-LABEL: vsetvl_e8m1_constant_avl:
51; CHECK:       # %bb.0:
52; CHECK-NEXT:    vsetivli a0, 1, e8, m1, ta, ma
53; CHECK-NEXT:    ret
54  %a = call i64 @llvm.riscv.vsetvli(i64 1, i64 0, i64 0)
55  %b = and i64 %a, 1
56  ret i64 %b
57}
58
59define i64 @vsetvl_e8m2_and15bits(i64 %avl) {
60; CHECK-LABEL: vsetvl_e8m2_and15bits:
61; CHECK:       # %bb.0:
62; CHECK-NEXT:    vsetvli a0, a0, e8, m2, ta, ma
63; CHECK-NEXT:    ret
64  %a = call i64 @llvm.riscv.vsetvli(i64 %avl, i64 0, i64 1)
65  %b = and i64 %a, 32767
66  ret i64 %b
67}
68
69define i64 @vsetvl_e8m2_and14bits(i64 %avl) {
70; CHECK-LABEL: vsetvl_e8m2_and14bits:
71; CHECK:       # %bb.0:
72; CHECK-NEXT:    vsetvli a0, a0, e8, m2, ta, ma
73; CHECK-NEXT:    slli a0, a0, 50
74; CHECK-NEXT:    srli a0, a0, 50
75; CHECK-NEXT:    ret
76  %a = call i64 @llvm.riscv.vsetvli(i64 %avl, i64 0, i64 1)
77  %b = and i64 %a, 16383
78  ret i64 %b
79}
80
81define i64 @vsetvl_e8m4_and16bits(i64 %avl) {
82; CHECK-LABEL: vsetvl_e8m4_and16bits:
83; CHECK:       # %bb.0:
84; CHECK-NEXT:    vsetvli a0, a0, e8, m4, ta, ma
85; CHECK-NEXT:    ret
86  %a = call i64 @llvm.riscv.vsetvli(i64 %avl, i64 0, i64 2)
87  %b = and i64 %a, 65535
88  ret i64 %b
89}
90
91define i64 @vsetvl_e8m4_and15bits(i64 %avl) {
92; CHECK-LABEL: vsetvl_e8m4_and15bits:
93; CHECK:       # %bb.0:
94; CHECK-NEXT:    vsetvli a0, a0, e8, m4, ta, ma
95; CHECK-NEXT:    slli a0, a0, 49
96; CHECK-NEXT:    srli a0, a0, 49
97; CHECK-NEXT:    ret
98  %a = call i64 @llvm.riscv.vsetvli(i64 %avl, i64 0, i64 2)
99  %b = and i64 %a, 32767
100  ret i64 %b
101}
102
103define i64 @vsetvl_e8m8_and17bits(i64 %avl) {
104; CHECK-LABEL: vsetvl_e8m8_and17bits:
105; CHECK:       # %bb.0:
106; CHECK-NEXT:    vsetvli a0, a0, e8, m8, ta, ma
107; CHECK-NEXT:    ret
108  %a = call i64 @llvm.riscv.vsetvli(i64 %avl, i64 0, i64 3)
109  %b = and i64 %a, 131071
110  ret i64 %b
111}
112
113define i64 @vsetvl_e8m8_and16bits(i64 %avl) {
114; CHECK-LABEL: vsetvl_e8m8_and16bits:
115; CHECK:       # %bb.0:
116; CHECK-NEXT:    vsetvli a0, a0, e8, m8, ta, ma
117; CHECK-NEXT:    slli a0, a0, 48
118; CHECK-NEXT:    srli a0, a0, 48
119; CHECK-NEXT:    ret
120  %a = call i64 @llvm.riscv.vsetvli(i64 %avl, i64 0, i64 3)
121  %b = and i64 %a, 65535
122  ret i64 %b
123}
124
125define i64 @vsetvl_e8mf2_and11bits(i64 %avl) {
126; CHECK-LABEL: vsetvl_e8mf2_and11bits:
127; CHECK:       # %bb.0:
128; CHECK-NEXT:    vsetvli a0, a0, e8, mf8, ta, ma
129; CHECK-NEXT:    ret
130  %a = call i64 @llvm.riscv.vsetvli(i64 %avl, i64 0, i64 5)
131  %b = and i64 %a, 2047
132  ret i64 %b
133}
134
135define i64 @vsetvl_e8mf2_and10bits(i64 %avl) {
136; CHECK-LABEL: vsetvl_e8mf2_and10bits:
137; CHECK:       # %bb.0:
138; CHECK-NEXT:    vsetvli a0, a0, e8, mf8, ta, ma
139; CHECK-NEXT:    andi a0, a0, 1023
140; CHECK-NEXT:    ret
141  %a = call i64 @llvm.riscv.vsetvli(i64 %avl, i64 0, i64 5)
142  %b = and i64 %a, 1023
143  ret i64 %b
144}
145
146define i64 @vsetvl_e8mf4_and12bits(i64 %avl) {
147; CHECK-LABEL: vsetvl_e8mf4_and12bits:
148; CHECK:       # %bb.0:
149; CHECK-NEXT:    vsetvli a0, a0, e8, mf4, ta, ma
150; CHECK-NEXT:    ret
151  %a = call i64 @llvm.riscv.vsetvli(i64 %avl, i64 0, i64 6)
152  %b = and i64 %a, 4095
153  ret i64 %b
154}
155
156define i64 @vsetvl_e8mf4_and11bits(i64 %avl) {
157; CHECK-LABEL: vsetvl_e8mf4_and11bits:
158; CHECK:       # %bb.0:
159; CHECK-NEXT:    vsetvli a0, a0, e8, mf4, ta, ma
160; CHECK-NEXT:    andi a0, a0, 2047
161; CHECK-NEXT:    ret
162  %a = call i64 @llvm.riscv.vsetvli(i64 %avl, i64 0, i64 6)
163  %b = and i64 %a, 2047
164  ret i64 %b
165}
166
167define i64 @vsetvl_e8mf8_and13bits(i64 %avl) {
168; CHECK-LABEL: vsetvl_e8mf8_and13bits:
169; CHECK:       # %bb.0:
170; CHECK-NEXT:    vsetvli a0, a0, e8, mf2, ta, ma
171; CHECK-NEXT:    ret
172  %a = call i64 @llvm.riscv.vsetvli(i64 %avl, i64 0, i64 7)
173  %b = and i64 %a, 8191
174  ret i64 %b
175}
176
177define i64 @vsetvl_e8mf8_and12bits(i64 %avl) {
178; CHECK-LABEL: vsetvl_e8mf8_and12bits:
179; CHECK:       # %bb.0:
180; CHECK-NEXT:    vsetvli a0, a0, e8, mf2, ta, ma
181; CHECK-NEXT:    slli a0, a0, 52
182; CHECK-NEXT:    srli a0, a0, 52
183; CHECK-NEXT:    ret
184  %a = call i64 @llvm.riscv.vsetvli(i64 %avl, i64 0, i64 7)
185  %b = and i64 %a, 4095
186  ret i64 %b
187}
188
189define i64 @vsetvl_e16m1_and13bits(i64 %avl) {
190; CHECK-LABEL: vsetvl_e16m1_and13bits:
191; CHECK:       # %bb.0:
192; CHECK-NEXT:    vsetvli a0, a0, e16, m1, ta, ma
193; CHECK-NEXT:    ret
194  %a = call i64 @llvm.riscv.vsetvli(i64 %avl, i64 1, i64 0)
195  %b = and i64 %a, 8191
196  ret i64 %b
197}
198
199define i64 @vsetvl_e16m1_and12bits(i64 %avl) {
200; CHECK-LABEL: vsetvl_e16m1_and12bits:
201; CHECK:       # %bb.0:
202; CHECK-NEXT:    vsetvli a0, a0, e16, m1, ta, ma
203; CHECK-NEXT:    slli a0, a0, 52
204; CHECK-NEXT:    srli a0, a0, 52
205; CHECK-NEXT:    ret
206  %a = call i64 @llvm.riscv.vsetvli(i64 %avl, i64 1, i64 0)
207  %b = and i64 %a, 4095
208  ret i64 %b
209}
210
211define i64 @vsetvl_e16m2_and14bits(i64 %avl) {
212; CHECK-LABEL: vsetvl_e16m2_and14bits:
213; CHECK:       # %bb.0:
214; CHECK-NEXT:    vsetvli a0, a0, e16, m2, ta, ma
215; CHECK-NEXT:    ret
216  %a = call i64 @llvm.riscv.vsetvli(i64 %avl, i64 1, i64 1)
217  %b = and i64 %a, 16383
218  ret i64 %b
219}
220
221define i64 @vsetvl_e16m2_and13bits(i64 %avl) {
222; CHECK-LABEL: vsetvl_e16m2_and13bits:
223; CHECK:       # %bb.0:
224; CHECK-NEXT:    vsetvli a0, a0, e16, m2, ta, ma
225; CHECK-NEXT:    slli a0, a0, 51
226; CHECK-NEXT:    srli a0, a0, 51
227; CHECK-NEXT:    ret
228  %a = call i64 @llvm.riscv.vsetvli(i64 %avl, i64 1, i64 1)
229  %b = and i64 %a, 8191
230  ret i64 %b
231}
232
233define i64 @vsetvl_e16m4_and15bits(i64 %avl) {
234; CHECK-LABEL: vsetvl_e16m4_and15bits:
235; CHECK:       # %bb.0:
236; CHECK-NEXT:    vsetvli a0, a0, e16, m4, ta, ma
237; CHECK-NEXT:    ret
238  %a = call i64 @llvm.riscv.vsetvli(i64 %avl, i64 1, i64 2)
239  %b = and i64 %a, 32767
240  ret i64 %b
241}
242
243define i64 @vsetvl_e16m4_and14bits(i64 %avl) {
244; CHECK-LABEL: vsetvl_e16m4_and14bits:
245; CHECK:       # %bb.0:
246; CHECK-NEXT:    vsetvli a0, a0, e16, m4, ta, ma
247; CHECK-NEXT:    slli a0, a0, 50
248; CHECK-NEXT:    srli a0, a0, 50
249; CHECK-NEXT:    ret
250  %a = call i64 @llvm.riscv.vsetvli(i64 %avl, i64 1, i64 2)
251  %b = and i64 %a, 16383
252  ret i64 %b
253}
254
255define i64 @vsetvl_e16m8_and16bits(i64 %avl) {
256; CHECK-LABEL: vsetvl_e16m8_and16bits:
257; CHECK:       # %bb.0:
258; CHECK-NEXT:    vsetvli a0, a0, e16, m8, ta, ma
259; CHECK-NEXT:    ret
260  %a = call i64 @llvm.riscv.vsetvli(i64 %avl, i64 1, i64 3)
261  %b = and i64 %a, 65535
262  ret i64 %b
263}
264
265define i64 @vsetvl_e16m8_and15bits(i64 %avl) {
266; CHECK-LABEL: vsetvl_e16m8_and15bits:
267; CHECK:       # %bb.0:
268; CHECK-NEXT:    vsetvli a0, a0, e16, m8, ta, ma
269; CHECK-NEXT:    slli a0, a0, 49
270; CHECK-NEXT:    srli a0, a0, 49
271; CHECK-NEXT:    ret
272  %a = call i64 @llvm.riscv.vsetvli(i64 %avl, i64 1, i64 3)
273  %b = and i64 %a, 32767
274  ret i64 %b
275}
276
277define i64 @vsetvl_e16mf2_and10bits(i64 %avl) {
278; CHECK-LABEL: vsetvl_e16mf2_and10bits:
279; CHECK:       # %bb.0:
280; CHECK-NEXT:    vsetvli a0, a0, e16, mf8, ta, ma
281; CHECK-NEXT:    ret
282  %a = call i64 @llvm.riscv.vsetvli(i64 %avl, i64 1, i64 5)
283  %b = and i64 %a, 1023
284  ret i64 %b
285}
286
287define i64 @vsetvl_e16mf2_and9bits(i64 %avl) {
288; CHECK-LABEL: vsetvl_e16mf2_and9bits:
289; CHECK:       # %bb.0:
290; CHECK-NEXT:    vsetvli a0, a0, e16, mf8, ta, ma
291; CHECK-NEXT:    andi a0, a0, 511
292; CHECK-NEXT:    ret
293  %a = call i64 @llvm.riscv.vsetvli(i64 %avl, i64 1, i64 5)
294  %b = and i64 %a, 511
295  ret i64 %b
296}
297
298define i64 @vsetvl_e16mf4_and11bits(i64 %avl) {
299; CHECK-LABEL: vsetvl_e16mf4_and11bits:
300; CHECK:       # %bb.0:
301; CHECK-NEXT:    vsetvli a0, a0, e16, mf4, ta, ma
302; CHECK-NEXT:    ret
303  %a = call i64 @llvm.riscv.vsetvli(i64 %avl, i64 1, i64 6)
304  %b = and i64 %a, 2047
305  ret i64 %b
306}
307
308define i64 @vsetvl_e16mf4_and10bits(i64 %avl) {
309; CHECK-LABEL: vsetvl_e16mf4_and10bits:
310; CHECK:       # %bb.0:
311; CHECK-NEXT:    vsetvli a0, a0, e16, mf4, ta, ma
312; CHECK-NEXT:    andi a0, a0, 1023
313; CHECK-NEXT:    ret
314  %a = call i64 @llvm.riscv.vsetvli(i64 %avl, i64 1, i64 6)
315  %b = and i64 %a, 1023
316  ret i64 %b
317}
318
319define i64 @vsetvl_e16mf8_and12bits(i64 %avl) {
320; CHECK-LABEL: vsetvl_e16mf8_and12bits:
321; CHECK:       # %bb.0:
322; CHECK-NEXT:    vsetvli a0, a0, e16, mf2, ta, ma
323; CHECK-NEXT:    ret
324  %a = call i64 @llvm.riscv.vsetvli(i64 %avl, i64 1, i64 7)
325  %b = and i64 %a, 4095
326  ret i64 %b
327}
328
329define i64 @vsetvl_e16mf8_and11bits(i64 %avl) {
330; CHECK-LABEL: vsetvl_e16mf8_and11bits:
331; CHECK:       # %bb.0:
332; CHECK-NEXT:    vsetvli a0, a0, e16, mf2, ta, ma
333; CHECK-NEXT:    andi a0, a0, 2047
334; CHECK-NEXT:    ret
335  %a = call i64 @llvm.riscv.vsetvli(i64 %avl, i64 1, i64 7)
336  %b = and i64 %a, 2047
337  ret i64 %b
338}
339
340define i64 @vsetvl_e32m1_and12bits(i64 %avl) {
341; CHECK-LABEL: vsetvl_e32m1_and12bits:
342; CHECK:       # %bb.0:
343; CHECK-NEXT:    vsetvli a0, a0, e32, m1, ta, ma
344; CHECK-NEXT:    ret
345  %a = call i64 @llvm.riscv.vsetvli(i64 %avl, i64 2, i64 0)
346  %b = and i64 %a, 4095
347  ret i64 %b
348}
349
350define i64 @vsetvl_e32m1_and11bits(i64 %avl) {
351; CHECK-LABEL: vsetvl_e32m1_and11bits:
352; CHECK:       # %bb.0:
353; CHECK-NEXT:    vsetvli a0, a0, e32, m1, ta, ma
354; CHECK-NEXT:    andi a0, a0, 2047
355; CHECK-NEXT:    ret
356  %a = call i64 @llvm.riscv.vsetvli(i64 %avl, i64 2, i64 0)
357  %b = and i64 %a, 2047
358  ret i64 %b
359}
360
361define i64 @vsetvl_e32m2_and13bits(i64 %avl) {
362; CHECK-LABEL: vsetvl_e32m2_and13bits:
363; CHECK:       # %bb.0:
364; CHECK-NEXT:    vsetvli a0, a0, e32, m2, ta, ma
365; CHECK-NEXT:    ret
366  %a = call i64 @llvm.riscv.vsetvli(i64 %avl, i64 2, i64 1)
367  %b = and i64 %a, 8191
368  ret i64 %b
369}
370
371define i64 @vsetvl_e32m2_and12bits(i64 %avl) {
372; CHECK-LABEL: vsetvl_e32m2_and12bits:
373; CHECK:       # %bb.0:
374; CHECK-NEXT:    vsetvli a0, a0, e32, m2, ta, ma
375; CHECK-NEXT:    slli a0, a0, 52
376; CHECK-NEXT:    srli a0, a0, 52
377; CHECK-NEXT:    ret
378  %a = call i64 @llvm.riscv.vsetvli(i64 %avl, i64 2, i64 1)
379  %b = and i64 %a, 4095
380  ret i64 %b
381}
382
383define i64 @vsetvl_e32m4_and14bits(i64 %avl) {
384; CHECK-LABEL: vsetvl_e32m4_and14bits:
385; CHECK:       # %bb.0:
386; CHECK-NEXT:    vsetvli a0, a0, e32, m4, ta, ma
387; CHECK-NEXT:    ret
388  %a = call i64 @llvm.riscv.vsetvli(i64 %avl, i64 2, i64 2)
389  %b = and i64 %a, 16383
390  ret i64 %b
391}
392
393define i64 @vsetvl_e32m4_and13bits(i64 %avl) {
394; CHECK-LABEL: vsetvl_e32m4_and13bits:
395; CHECK:       # %bb.0:
396; CHECK-NEXT:    vsetvli a0, a0, e32, m4, ta, ma
397; CHECK-NEXT:    slli a0, a0, 51
398; CHECK-NEXT:    srli a0, a0, 51
399; CHECK-NEXT:    ret
400  %a = call i64 @llvm.riscv.vsetvli(i64 %avl, i64 2, i64 2)
401  %b = and i64 %a, 8191
402  ret i64 %b
403}
404
405define i64 @vsetvl_e32m8_and15bits(i64 %avl) {
406; CHECK-LABEL: vsetvl_e32m8_and15bits:
407; CHECK:       # %bb.0:
408; CHECK-NEXT:    vsetvli a0, a0, e32, m8, ta, ma
409; CHECK-NEXT:    ret
410  %a = call i64 @llvm.riscv.vsetvli(i64 %avl, i64 2, i64 3)
411  %b = and i64 %a, 32767
412  ret i64 %b
413}
414
415define i64 @vsetvl_e32m8_and14bits(i64 %avl) {
416; CHECK-LABEL: vsetvl_e32m8_and14bits:
417; CHECK:       # %bb.0:
418; CHECK-NEXT:    vsetvli a0, a0, e32, m8, ta, ma
419; CHECK-NEXT:    slli a0, a0, 50
420; CHECK-NEXT:    srli a0, a0, 50
421; CHECK-NEXT:    ret
422  %a = call i64 @llvm.riscv.vsetvli(i64 %avl, i64 2, i64 3)
423  %b = and i64 %a, 16383
424  ret i64 %b
425}
426
427define i64 @vsetvl_e32mf2_and9bits(i64 %avl) {
428; CHECK-LABEL: vsetvl_e32mf2_and9bits:
429; CHECK:       # %bb.0:
430; CHECK-NEXT:    vsetvli a0, a0, e32, mf8, ta, ma
431; CHECK-NEXT:    ret
432  %a = call i64 @llvm.riscv.vsetvli(i64 %avl, i64 2, i64 5)
433  %b = and i64 %a, 511
434  ret i64 %b
435}
436
437define i64 @vsetvl_e32mf2_and8bits(i64 %avl) {
438; CHECK-LABEL: vsetvl_e32mf2_and8bits:
439; CHECK:       # %bb.0:
440; CHECK-NEXT:    vsetvli a0, a0, e32, mf8, ta, ma
441; CHECK-NEXT:    andi a0, a0, 255
442; CHECK-NEXT:    ret
443  %a = call i64 @llvm.riscv.vsetvli(i64 %avl, i64 2, i64 5)
444  %b = and i64 %a, 255
445  ret i64 %b
446}
447
448define i64 @vsetvl_e32mf4_and10bits(i64 %avl) {
449; CHECK-LABEL: vsetvl_e32mf4_and10bits:
450; CHECK:       # %bb.0:
451; CHECK-NEXT:    vsetvli a0, a0, e32, mf4, ta, ma
452; CHECK-NEXT:    ret
453  %a = call i64 @llvm.riscv.vsetvli(i64 %avl, i64 2, i64 6)
454  %b = and i64 %a, 1023
455  ret i64 %b
456}
457
458define i64 @vsetvl_e32mf4_and9bits(i64 %avl) {
459; CHECK-LABEL: vsetvl_e32mf4_and9bits:
460; CHECK:       # %bb.0:
461; CHECK-NEXT:    vsetvli a0, a0, e32, mf4, ta, ma
462; CHECK-NEXT:    andi a0, a0, 511
463; CHECK-NEXT:    ret
464  %a = call i64 @llvm.riscv.vsetvli(i64 %avl, i64 2, i64 6)
465  %b = and i64 %a, 511
466  ret i64 %b
467}
468
469define i64 @vsetvl_e32mf8_and11bits(i64 %avl) {
470; CHECK-LABEL: vsetvl_e32mf8_and11bits:
471; CHECK:       # %bb.0:
472; CHECK-NEXT:    vsetvli a0, a0, e32, mf2, ta, ma
473; CHECK-NEXT:    ret
474  %a = call i64 @llvm.riscv.vsetvli(i64 %avl, i64 2, i64 7)
475  %b = and i64 %a, 2047
476  ret i64 %b
477}
478
479define i64 @vsetvl_e32mf8_and10bits(i64 %avl) {
480; CHECK-LABEL: vsetvl_e32mf8_and10bits:
481; CHECK:       # %bb.0:
482; CHECK-NEXT:    vsetvli a0, a0, e32, mf2, ta, ma
483; CHECK-NEXT:    andi a0, a0, 1023
484; CHECK-NEXT:    ret
485  %a = call i64 @llvm.riscv.vsetvli(i64 %avl, i64 2, i64 7)
486  %b = and i64 %a, 1023
487  ret i64 %b
488}
489
490define i64 @vsetvl_e64m1_and11bits(i64 %avl) {
491; CHECK-LABEL: vsetvl_e64m1_and11bits:
492; CHECK:       # %bb.0:
493; CHECK-NEXT:    vsetvli a0, a0, e64, m1, ta, ma
494; CHECK-NEXT:    ret
495  %a = call i64 @llvm.riscv.vsetvli(i64 %avl, i64 3, i64 0)
496  %b = and i64 %a, 2047
497  ret i64 %b
498}
499
500define i64 @vsetvl_e64m1_and10bits(i64 %avl) {
501; CHECK-LABEL: vsetvl_e64m1_and10bits:
502; CHECK:       # %bb.0:
503; CHECK-NEXT:    vsetvli a0, a0, e64, m1, ta, ma
504; CHECK-NEXT:    andi a0, a0, 1023
505; CHECK-NEXT:    ret
506  %a = call i64 @llvm.riscv.vsetvli(i64 %avl, i64 3, i64 0)
507  %b = and i64 %a, 1023
508  ret i64 %b
509}
510
511define i64 @vsetvl_e64m2_and12bits(i64 %avl) {
512; CHECK-LABEL: vsetvl_e64m2_and12bits:
513; CHECK:       # %bb.0:
514; CHECK-NEXT:    vsetvli a0, a0, e64, m2, ta, ma
515; CHECK-NEXT:    ret
516  %a = call i64 @llvm.riscv.vsetvli(i64 %avl, i64 3, i64 1)
517  %b = and i64 %a, 4095
518  ret i64 %b
519}
520
521define i64 @vsetvl_e64m2_and11bits(i64 %avl) {
522; CHECK-LABEL: vsetvl_e64m2_and11bits:
523; CHECK:       # %bb.0:
524; CHECK-NEXT:    vsetvli a0, a0, e64, m2, ta, ma
525; CHECK-NEXT:    andi a0, a0, 2047
526; CHECK-NEXT:    ret
527  %a = call i64 @llvm.riscv.vsetvli(i64 %avl, i64 3, i64 1)
528  %b = and i64 %a, 2047
529  ret i64 %b
530}
531
532define i64 @vsetvl_e64m4_and13bits(i64 %avl) {
533; CHECK-LABEL: vsetvl_e64m4_and13bits:
534; CHECK:       # %bb.0:
535; CHECK-NEXT:    vsetvli a0, a0, e64, m4, ta, ma
536; CHECK-NEXT:    ret
537  %a = call i64 @llvm.riscv.vsetvli(i64 %avl, i64 3, i64 2)
538  %b = and i64 %a, 8191
539  ret i64 %b
540}
541
542define i64 @vsetvl_e64m4_and12bits(i64 %avl) {
543; CHECK-LABEL: vsetvl_e64m4_and12bits:
544; CHECK:       # %bb.0:
545; CHECK-NEXT:    vsetvli a0, a0, e64, m4, ta, ma
546; CHECK-NEXT:    slli a0, a0, 52
547; CHECK-NEXT:    srli a0, a0, 52
548; CHECK-NEXT:    ret
549  %a = call i64 @llvm.riscv.vsetvli(i64 %avl, i64 3, i64 2)
550  %b = and i64 %a, 4095
551  ret i64 %b
552}
553
554define i64 @vsetvl_e64m8_and14bits(i64 %avl) {
555; CHECK-LABEL: vsetvl_e64m8_and14bits:
556; CHECK:       # %bb.0:
557; CHECK-NEXT:    vsetvli a0, a0, e64, m8, ta, ma
558; CHECK-NEXT:    ret
559  %a = call i64 @llvm.riscv.vsetvli(i64 %avl, i64 3, i64 3)
560  %b = and i64 %a, 16383
561  ret i64 %b
562}
563
564define i64 @vsetvl_e64m8_and13bits(i64 %avl) {
565; CHECK-LABEL: vsetvl_e64m8_and13bits:
566; CHECK:       # %bb.0:
567; CHECK-NEXT:    vsetvli a0, a0, e64, m8, ta, ma
568; CHECK-NEXT:    slli a0, a0, 51
569; CHECK-NEXT:    srli a0, a0, 51
570; CHECK-NEXT:    ret
571  %a = call i64 @llvm.riscv.vsetvli(i64 %avl, i64 3, i64 3)
572  %b = and i64 %a, 8191
573  ret i64 %b
574}
575
576define i64 @vsetvl_e64mf2_and8bits(i64 %avl) {
577; CHECK-LABEL: vsetvl_e64mf2_and8bits:
578; CHECK:       # %bb.0:
579; CHECK-NEXT:    vsetvli a0, a0, e64, mf8, ta, ma
580; CHECK-NEXT:    ret
581  %a = call i64 @llvm.riscv.vsetvli(i64 %avl, i64 3, i64 5)
582  %b = and i64 %a, 255
583  ret i64 %b
584}
585
586define i64 @vsetvl_e64mf2_and7bits(i64 %avl) {
587; CHECK-LABEL: vsetvl_e64mf2_and7bits:
588; CHECK:       # %bb.0:
589; CHECK-NEXT:    vsetvli a0, a0, e64, mf8, ta, ma
590; CHECK-NEXT:    andi a0, a0, 127
591; CHECK-NEXT:    ret
592  %a = call i64 @llvm.riscv.vsetvli(i64 %avl, i64 3, i64 5)
593  %b = and i64 %a, 127
594  ret i64 %b
595}
596
597define i64 @vsetvl_e64mf4_and9bits(i64 %avl) {
598; CHECK-LABEL: vsetvl_e64mf4_and9bits:
599; CHECK:       # %bb.0:
600; CHECK-NEXT:    vsetvli a0, a0, e64, mf4, ta, ma
601; CHECK-NEXT:    ret
602  %a = call i64 @llvm.riscv.vsetvli(i64 %avl, i64 3, i64 6)
603  %b = and i64 %a, 511
604  ret i64 %b
605}
606
607define i64 @vsetvl_e64mf4_and8bits(i64 %avl) {
608; CHECK-LABEL: vsetvl_e64mf4_and8bits:
609; CHECK:       # %bb.0:
610; CHECK-NEXT:    vsetvli a0, a0, e64, mf4, ta, ma
611; CHECK-NEXT:    andi a0, a0, 255
612; CHECK-NEXT:    ret
613  %a = call i64 @llvm.riscv.vsetvli(i64 %avl, i64 3, i64 6)
614  %b = and i64 %a, 255
615  ret i64 %b
616}
617
618define i64 @vsetvl_e64mf8_and10bits(i64 %avl) {
619; CHECK-LABEL: vsetvl_e64mf8_and10bits:
620; CHECK:       # %bb.0:
621; CHECK-NEXT:    vsetvli a0, a0, e64, mf2, ta, ma
622; CHECK-NEXT:    ret
623  %a = call i64 @llvm.riscv.vsetvli(i64 %avl, i64 3, i64 7)
624  %b = and i64 %a, 1023
625  ret i64 %b
626}
627
628define i64 @vsetvl_e64mf8_and9bits(i64 %avl) {
629; CHECK-LABEL: vsetvl_e64mf8_and9bits:
630; CHECK:       # %bb.0:
631; CHECK-NEXT:    vsetvli a0, a0, e64, mf2, ta, ma
632; CHECK-NEXT:    andi a0, a0, 511
633; CHECK-NEXT:    ret
634  %a = call i64 @llvm.riscv.vsetvli(i64 %avl, i64 3, i64 7)
635  %b = and i64 %a, 511
636  ret i64 %b
637}
638