xref: /llvm-project/llvm/test/CodeGen/RISCV/rvv/vselect-vp.ll (revision b6c0f1bfa79a3a32d841ac5ab1f94c3aee3b5d90) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+d,+m,+zvfh,+v -target-abi=ilp32d \
3; RUN:     -verify-machineinstrs < %s | FileCheck %s
4; RUN: llc -mtriple=riscv64 -mattr=+d,+m,+zvfh,+v -target-abi=lp64d \
5; RUN:     -verify-machineinstrs < %s | FileCheck %s
6; RUN: llc -mtriple=riscv32 -mattr=+d,+m,+zvfhmin,+v -target-abi=ilp32d \
7; RUN:     -verify-machineinstrs < %s | FileCheck %s
8; RUN: llc -mtriple=riscv64 -mattr=+d,+m,+zvfhmin,+v -target-abi=lp64d \
9; RUN:     -verify-machineinstrs < %s | FileCheck %s
10
11declare <vscale x 1 x i1> @llvm.vp.select.nxv1i1(<vscale x 1 x i1>, <vscale x 1 x i1>, <vscale x 1 x i1>, i32)
12
13define <vscale x 1 x i1> @select_nxv1i1(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b, <vscale x 1 x i1> %c, i32 zeroext %evl) {
14; CHECK-LABEL: select_nxv1i1:
15; CHECK:       # %bb.0:
16; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, ma
17; CHECK-NEXT:    vmandn.mm v9, v9, v0
18; CHECK-NEXT:    vmand.mm v8, v8, v0
19; CHECK-NEXT:    vmor.mm v0, v8, v9
20; CHECK-NEXT:    ret
21  %v = call <vscale x 1 x i1> @llvm.vp.select.nxv1i1(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b, <vscale x 1 x i1> %c, i32 %evl)
22  ret <vscale x 1 x i1> %v
23}
24
25declare <vscale x 2 x i1> @llvm.vp.select.nxv2i1(<vscale x 2 x i1>, <vscale x 2 x i1>, <vscale x 2 x i1>, i32)
26
27define <vscale x 2 x i1> @select_nxv2i1(<vscale x 2 x i1> %a, <vscale x 2 x i1> %b, <vscale x 2 x i1> %c, i32 zeroext %evl) {
28; CHECK-LABEL: select_nxv2i1:
29; CHECK:       # %bb.0:
30; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, ma
31; CHECK-NEXT:    vmandn.mm v9, v9, v0
32; CHECK-NEXT:    vmand.mm v8, v8, v0
33; CHECK-NEXT:    vmor.mm v0, v8, v9
34; CHECK-NEXT:    ret
35  %v = call <vscale x 2 x i1> @llvm.vp.select.nxv2i1(<vscale x 2 x i1> %a, <vscale x 2 x i1> %b, <vscale x 2 x i1> %c, i32 %evl)
36  ret <vscale x 2 x i1> %v
37}
38
39declare <vscale x 4 x i1> @llvm.vp.select.nxv4i1(<vscale x 4 x i1>, <vscale x 4 x i1>, <vscale x 4 x i1>, i32)
40
41define <vscale x 4 x i1> @select_nxv4i1(<vscale x 4 x i1> %a, <vscale x 4 x i1> %b, <vscale x 4 x i1> %c, i32 zeroext %evl) {
42; CHECK-LABEL: select_nxv4i1:
43; CHECK:       # %bb.0:
44; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma
45; CHECK-NEXT:    vmandn.mm v9, v9, v0
46; CHECK-NEXT:    vmand.mm v8, v8, v0
47; CHECK-NEXT:    vmor.mm v0, v8, v9
48; CHECK-NEXT:    ret
49  %v = call <vscale x 4 x i1> @llvm.vp.select.nxv4i1(<vscale x 4 x i1> %a, <vscale x 4 x i1> %b, <vscale x 4 x i1> %c, i32 %evl)
50  ret <vscale x 4 x i1> %v
51}
52
53declare <vscale x 8 x i1> @llvm.vp.select.nxv8i1(<vscale x 8 x i1>, <vscale x 8 x i1>, <vscale x 8 x i1>, i32)
54
55define <vscale x 8 x i1> @select_nxv8i1(<vscale x 8 x i1> %a, <vscale x 8 x i1> %b, <vscale x 8 x i1> %c, i32 zeroext %evl) {
56; CHECK-LABEL: select_nxv8i1:
57; CHECK:       # %bb.0:
58; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, ma
59; CHECK-NEXT:    vmandn.mm v9, v9, v0
60; CHECK-NEXT:    vmand.mm v8, v8, v0
61; CHECK-NEXT:    vmor.mm v0, v8, v9
62; CHECK-NEXT:    ret
63  %v = call <vscale x 8 x i1> @llvm.vp.select.nxv8i1(<vscale x 8 x i1> %a, <vscale x 8 x i1> %b, <vscale x 8 x i1> %c, i32 %evl)
64  ret <vscale x 8 x i1> %v
65}
66
67declare <vscale x 16 x i1> @llvm.vp.select.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, i32)
68
69define <vscale x 16 x i1> @select_nxv16i1(<vscale x 16 x i1> %a, <vscale x 16 x i1> %b, <vscale x 16 x i1> %c, i32 zeroext %evl) {
70; CHECK-LABEL: select_nxv16i1:
71; CHECK:       # %bb.0:
72; CHECK-NEXT:    vsetvli zero, a0, e8, m2, ta, ma
73; CHECK-NEXT:    vmandn.mm v9, v9, v0
74; CHECK-NEXT:    vmand.mm v8, v8, v0
75; CHECK-NEXT:    vmor.mm v0, v8, v9
76; CHECK-NEXT:    ret
77  %v = call <vscale x 16 x i1> @llvm.vp.select.nxv16i1(<vscale x 16 x i1> %a, <vscale x 16 x i1> %b, <vscale x 16 x i1> %c, i32 %evl)
78  ret <vscale x 16 x i1> %v
79}
80
81declare <vscale x 32 x i1> @llvm.vp.select.nxv32i1(<vscale x 32 x i1>, <vscale x 32 x i1>, <vscale x 32 x i1>, i32)
82
83define <vscale x 32 x i1> @select_nxv32i1(<vscale x 32 x i1> %a, <vscale x 32 x i1> %b, <vscale x 32 x i1> %c, i32 zeroext %evl) {
84; CHECK-LABEL: select_nxv32i1:
85; CHECK:       # %bb.0:
86; CHECK-NEXT:    vsetvli zero, a0, e8, m4, ta, ma
87; CHECK-NEXT:    vmandn.mm v9, v9, v0
88; CHECK-NEXT:    vmand.mm v8, v8, v0
89; CHECK-NEXT:    vmor.mm v0, v8, v9
90; CHECK-NEXT:    ret
91  %v = call <vscale x 32 x i1> @llvm.vp.select.nxv32i1(<vscale x 32 x i1> %a, <vscale x 32 x i1> %b, <vscale x 32 x i1> %c, i32 %evl)
92  ret <vscale x 32 x i1> %v
93}
94
95declare <vscale x 64 x i1> @llvm.vp.select.nxv64i1(<vscale x 64 x i1>, <vscale x 64 x i1>, <vscale x 64 x i1>, i32)
96
97define <vscale x 64 x i1> @select_nxv64i1(<vscale x 64 x i1> %a, <vscale x 64 x i1> %b, <vscale x 64 x i1> %c, i32 zeroext %evl) {
98; CHECK-LABEL: select_nxv64i1:
99; CHECK:       # %bb.0:
100; CHECK-NEXT:    vsetvli zero, a0, e8, m8, ta, ma
101; CHECK-NEXT:    vmandn.mm v9, v9, v0
102; CHECK-NEXT:    vmand.mm v8, v8, v0
103; CHECK-NEXT:    vmor.mm v0, v8, v9
104; CHECK-NEXT:    ret
105  %v = call <vscale x 64 x i1> @llvm.vp.select.nxv64i1(<vscale x 64 x i1> %a, <vscale x 64 x i1> %b, <vscale x 64 x i1> %c, i32 %evl)
106  ret <vscale x 64 x i1> %v
107}
108
109declare <vscale x 8 x i7> @llvm.vp.select.nxv8i7(<vscale x 8 x i1>, <vscale x 8 x i7>, <vscale x 8 x i7>, i32)
110
111define <vscale x 8 x i7> @select_nxv8i7(<vscale x 8 x i1> %a, <vscale x 8 x i7> %b, <vscale x 8 x i7> %c, i32 zeroext %evl) {
112; CHECK-LABEL: select_nxv8i7:
113; CHECK:       # %bb.0:
114; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, ma
115; CHECK-NEXT:    vmerge.vvm v8, v9, v8, v0
116; CHECK-NEXT:    ret
117  %v = call <vscale x 8 x i7> @llvm.vp.select.nxv8i7(<vscale x 8 x i1> %a, <vscale x 8 x i7> %b, <vscale x 8 x i7> %c, i32 %evl)
118  ret <vscale x 8 x i7> %v
119}
120
121declare <vscale x 1 x i8> @llvm.vp.select.nxv1i8(<vscale x 1 x i1>, <vscale x 1 x i8>, <vscale x 1 x i8>, i32)
122
123define <vscale x 1 x i8> @select_nxv1i8(<vscale x 1 x i1> %a, <vscale x 1 x i8> %b, <vscale x 1 x i8> %c, i32 zeroext %evl) {
124; CHECK-LABEL: select_nxv1i8:
125; CHECK:       # %bb.0:
126; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, ma
127; CHECK-NEXT:    vmerge.vvm v8, v9, v8, v0
128; CHECK-NEXT:    ret
129  %v = call <vscale x 1 x i8> @llvm.vp.select.nxv1i8(<vscale x 1 x i1> %a, <vscale x 1 x i8> %b, <vscale x 1 x i8> %c, i32 %evl)
130  ret <vscale x 1 x i8> %v
131}
132
133declare <vscale x 2 x i8> @llvm.vp.select.nxv2i8(<vscale x 2 x i1>, <vscale x 2 x i8>, <vscale x 2 x i8>, i32)
134
135define <vscale x 2 x i8> @select_nxv2i8(<vscale x 2 x i1> %a, <vscale x 2 x i8> %b, <vscale x 2 x i8> %c, i32 zeroext %evl) {
136; CHECK-LABEL: select_nxv2i8:
137; CHECK:       # %bb.0:
138; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, ma
139; CHECK-NEXT:    vmerge.vvm v8, v9, v8, v0
140; CHECK-NEXT:    ret
141  %v = call <vscale x 2 x i8> @llvm.vp.select.nxv2i8(<vscale x 2 x i1> %a, <vscale x 2 x i8> %b, <vscale x 2 x i8> %c, i32 %evl)
142  ret <vscale x 2 x i8> %v
143}
144
145declare <vscale x 4 x i8> @llvm.vp.select.nxv4i8(<vscale x 4 x i1>, <vscale x 4 x i8>, <vscale x 4 x i8>, i32)
146
147define <vscale x 4 x i8> @select_nxv4i8(<vscale x 4 x i1> %a, <vscale x 4 x i8> %b, <vscale x 4 x i8> %c, i32 zeroext %evl) {
148; CHECK-LABEL: select_nxv4i8:
149; CHECK:       # %bb.0:
150; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma
151; CHECK-NEXT:    vmerge.vvm v8, v9, v8, v0
152; CHECK-NEXT:    ret
153  %v = call <vscale x 4 x i8> @llvm.vp.select.nxv4i8(<vscale x 4 x i1> %a, <vscale x 4 x i8> %b, <vscale x 4 x i8> %c, i32 %evl)
154  ret <vscale x 4 x i8> %v
155}
156
157declare <vscale x 8 x i8> @llvm.vp.select.nxv8i8(<vscale x 8 x i1>, <vscale x 8 x i8>, <vscale x 8 x i8>, i32)
158
159define <vscale x 8 x i8> @select_nxv8i8(<vscale x 8 x i1> %a, <vscale x 8 x i8> %b, <vscale x 8 x i8> %c, i32 zeroext %evl) {
160; CHECK-LABEL: select_nxv8i8:
161; CHECK:       # %bb.0:
162; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, ma
163; CHECK-NEXT:    vmerge.vvm v8, v9, v8, v0
164; CHECK-NEXT:    ret
165  %v = call <vscale x 8 x i8> @llvm.vp.select.nxv8i8(<vscale x 8 x i1> %a, <vscale x 8 x i8> %b, <vscale x 8 x i8> %c, i32 %evl)
166  ret <vscale x 8 x i8> %v
167}
168
169declare <vscale x 14 x i8> @llvm.vp.select.nxv14i8(<vscale x 14 x i1>, <vscale x 14 x i8>, <vscale x 14 x i8>, i32)
170
171define <vscale x 14 x i8> @select_nxv14i8(<vscale x 14 x i1> %a, <vscale x 14 x i8> %b, <vscale x 14 x i8> %c, i32 zeroext %evl) {
172; CHECK-LABEL: select_nxv14i8:
173; CHECK:       # %bb.0:
174; CHECK-NEXT:    vsetvli zero, a0, e8, m2, ta, ma
175; CHECK-NEXT:    vmerge.vvm v8, v10, v8, v0
176; CHECK-NEXT:    ret
177  %v = call <vscale x 14 x i8> @llvm.vp.select.nxv14i8(<vscale x 14 x i1> %a, <vscale x 14 x i8> %b, <vscale x 14 x i8> %c, i32 %evl)
178  ret <vscale x 14 x i8> %v
179}
180
181declare <vscale x 16 x i8> @llvm.vp.select.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32)
182
183define <vscale x 16 x i8> @select_nxv16i8(<vscale x 16 x i1> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c, i32 zeroext %evl) {
184; CHECK-LABEL: select_nxv16i8:
185; CHECK:       # %bb.0:
186; CHECK-NEXT:    vsetvli zero, a0, e8, m2, ta, ma
187; CHECK-NEXT:    vmerge.vvm v8, v10, v8, v0
188; CHECK-NEXT:    ret
189  %v = call <vscale x 16 x i8> @llvm.vp.select.nxv16i8(<vscale x 16 x i1> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c, i32 %evl)
190  ret <vscale x 16 x i8> %v
191}
192
193declare <vscale x 32 x i8> @llvm.vp.select.nxv32i8(<vscale x 32 x i1>, <vscale x 32 x i8>, <vscale x 32 x i8>, i32)
194
195define <vscale x 32 x i8> @select_nxv32i8(<vscale x 32 x i1> %a, <vscale x 32 x i8> %b, <vscale x 32 x i8> %c, i32 zeroext %evl) {
196; CHECK-LABEL: select_nxv32i8:
197; CHECK:       # %bb.0:
198; CHECK-NEXT:    vsetvli zero, a0, e8, m4, ta, ma
199; CHECK-NEXT:    vmerge.vvm v8, v12, v8, v0
200; CHECK-NEXT:    ret
201  %v = call <vscale x 32 x i8> @llvm.vp.select.nxv32i8(<vscale x 32 x i1> %a, <vscale x 32 x i8> %b, <vscale x 32 x i8> %c, i32 %evl)
202  ret <vscale x 32 x i8> %v
203}
204
205declare <vscale x 64 x i8> @llvm.vp.select.nxv64i8(<vscale x 64 x i1>, <vscale x 64 x i8>, <vscale x 64 x i8>, i32)
206
207define <vscale x 64 x i8> @select_nxv64i8(<vscale x 64 x i1> %a, <vscale x 64 x i8> %b, <vscale x 64 x i8> %c, i32 zeroext %evl) {
208; CHECK-LABEL: select_nxv64i8:
209; CHECK:       # %bb.0:
210; CHECK-NEXT:    vsetvli zero, a0, e8, m8, ta, ma
211; CHECK-NEXT:    vmerge.vvm v8, v16, v8, v0
212; CHECK-NEXT:    ret
213  %v = call <vscale x 64 x i8> @llvm.vp.select.nxv64i8(<vscale x 64 x i1> %a, <vscale x 64 x i8> %b, <vscale x 64 x i8> %c, i32 %evl)
214  ret <vscale x 64 x i8> %v
215}
216
217declare <vscale x 1 x i16> @llvm.vp.select.nxv1i16(<vscale x 1 x i1>, <vscale x 1 x i16>, <vscale x 1 x i16>, i32)
218
219define <vscale x 1 x i16> @select_nxv1i16(<vscale x 1 x i1> %a, <vscale x 1 x i16> %b, <vscale x 1 x i16> %c, i32 zeroext %evl) {
220; CHECK-LABEL: select_nxv1i16:
221; CHECK:       # %bb.0:
222; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma
223; CHECK-NEXT:    vmerge.vvm v8, v9, v8, v0
224; CHECK-NEXT:    ret
225  %v = call <vscale x 1 x i16> @llvm.vp.select.nxv1i16(<vscale x 1 x i1> %a, <vscale x 1 x i16> %b, <vscale x 1 x i16> %c, i32 %evl)
226  ret <vscale x 1 x i16> %v
227}
228
229declare <vscale x 2 x i16> @llvm.vp.select.nxv2i16(<vscale x 2 x i1>, <vscale x 2 x i16>, <vscale x 2 x i16>, i32)
230
231define <vscale x 2 x i16> @select_nxv2i16(<vscale x 2 x i1> %a, <vscale x 2 x i16> %b, <vscale x 2 x i16> %c, i32 zeroext %evl) {
232; CHECK-LABEL: select_nxv2i16:
233; CHECK:       # %bb.0:
234; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma
235; CHECK-NEXT:    vmerge.vvm v8, v9, v8, v0
236; CHECK-NEXT:    ret
237  %v = call <vscale x 2 x i16> @llvm.vp.select.nxv2i16(<vscale x 2 x i1> %a, <vscale x 2 x i16> %b, <vscale x 2 x i16> %c, i32 %evl)
238  ret <vscale x 2 x i16> %v
239}
240
241declare <vscale x 4 x i16> @llvm.vp.select.nxv4i16(<vscale x 4 x i1>, <vscale x 4 x i16>, <vscale x 4 x i16>, i32)
242
243define <vscale x 4 x i16> @select_nxv4i16(<vscale x 4 x i1> %a, <vscale x 4 x i16> %b, <vscale x 4 x i16> %c, i32 zeroext %evl) {
244; CHECK-LABEL: select_nxv4i16:
245; CHECK:       # %bb.0:
246; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, ma
247; CHECK-NEXT:    vmerge.vvm v8, v9, v8, v0
248; CHECK-NEXT:    ret
249  %v = call <vscale x 4 x i16> @llvm.vp.select.nxv4i16(<vscale x 4 x i1> %a, <vscale x 4 x i16> %b, <vscale x 4 x i16> %c, i32 %evl)
250  ret <vscale x 4 x i16> %v
251}
252
253declare <vscale x 8 x i16> @llvm.vp.select.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>, i32)
254
255define <vscale x 8 x i16> @select_nxv8i16(<vscale x 8 x i1> %a, <vscale x 8 x i16> %b, <vscale x 8 x i16> %c, i32 zeroext %evl) {
256; CHECK-LABEL: select_nxv8i16:
257; CHECK:       # %bb.0:
258; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, ma
259; CHECK-NEXT:    vmerge.vvm v8, v10, v8, v0
260; CHECK-NEXT:    ret
261  %v = call <vscale x 8 x i16> @llvm.vp.select.nxv8i16(<vscale x 8 x i1> %a, <vscale x 8 x i16> %b, <vscale x 8 x i16> %c, i32 %evl)
262  ret <vscale x 8 x i16> %v
263}
264
265declare <vscale x 16 x i16> @llvm.vp.select.nxv16i16(<vscale x 16 x i1>, <vscale x 16 x i16>, <vscale x 16 x i16>, i32)
266
267define <vscale x 16 x i16> @select_nxv16i16(<vscale x 16 x i1> %a, <vscale x 16 x i16> %b, <vscale x 16 x i16> %c, i32 zeroext %evl) {
268; CHECK-LABEL: select_nxv16i16:
269; CHECK:       # %bb.0:
270; CHECK-NEXT:    vsetvli zero, a0, e16, m4, ta, ma
271; CHECK-NEXT:    vmerge.vvm v8, v12, v8, v0
272; CHECK-NEXT:    ret
273  %v = call <vscale x 16 x i16> @llvm.vp.select.nxv16i16(<vscale x 16 x i1> %a, <vscale x 16 x i16> %b, <vscale x 16 x i16> %c, i32 %evl)
274  ret <vscale x 16 x i16> %v
275}
276
277declare <vscale x 32 x i16> @llvm.vp.select.nxv32i16(<vscale x 32 x i1>, <vscale x 32 x i16>, <vscale x 32 x i16>, i32)
278
279define <vscale x 32 x i16> @select_nxv32i16(<vscale x 32 x i1> %a, <vscale x 32 x i16> %b, <vscale x 32 x i16> %c, i32 zeroext %evl) {
280; CHECK-LABEL: select_nxv32i16:
281; CHECK:       # %bb.0:
282; CHECK-NEXT:    vsetvli zero, a0, e16, m8, ta, ma
283; CHECK-NEXT:    vmerge.vvm v8, v16, v8, v0
284; CHECK-NEXT:    ret
285  %v = call <vscale x 32 x i16> @llvm.vp.select.nxv32i16(<vscale x 32 x i1> %a, <vscale x 32 x i16> %b, <vscale x 32 x i16> %c, i32 %evl)
286  ret <vscale x 32 x i16> %v
287}
288
289declare <vscale x 1 x i32> @llvm.vp.select.nxv1i32(<vscale x 1 x i1>, <vscale x 1 x i32>, <vscale x 1 x i32>, i32)
290
291define <vscale x 1 x i32> @select_nxv1i32(<vscale x 1 x i1> %a, <vscale x 1 x i32> %b, <vscale x 1 x i32> %c, i32 zeroext %evl) {
292; CHECK-LABEL: select_nxv1i32:
293; CHECK:       # %bb.0:
294; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma
295; CHECK-NEXT:    vmerge.vvm v8, v9, v8, v0
296; CHECK-NEXT:    ret
297  %v = call <vscale x 1 x i32> @llvm.vp.select.nxv1i32(<vscale x 1 x i1> %a, <vscale x 1 x i32> %b, <vscale x 1 x i32> %c, i32 %evl)
298  ret <vscale x 1 x i32> %v
299}
300
301declare <vscale x 2 x i32> @llvm.vp.select.nxv2i32(<vscale x 2 x i1>, <vscale x 2 x i32>, <vscale x 2 x i32>, i32)
302
303define <vscale x 2 x i32> @select_nxv2i32(<vscale x 2 x i1> %a, <vscale x 2 x i32> %b, <vscale x 2 x i32> %c, i32 zeroext %evl) {
304; CHECK-LABEL: select_nxv2i32:
305; CHECK:       # %bb.0:
306; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma
307; CHECK-NEXT:    vmerge.vvm v8, v9, v8, v0
308; CHECK-NEXT:    ret
309  %v = call <vscale x 2 x i32> @llvm.vp.select.nxv2i32(<vscale x 2 x i1> %a, <vscale x 2 x i32> %b, <vscale x 2 x i32> %c, i32 %evl)
310  ret <vscale x 2 x i32> %v
311}
312
313declare <vscale x 4 x i32> @llvm.vp.select.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>, i32)
314
315define <vscale x 4 x i32> @select_nxv4i32(<vscale x 4 x i1> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c, i32 zeroext %evl) {
316; CHECK-LABEL: select_nxv4i32:
317; CHECK:       # %bb.0:
318; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma
319; CHECK-NEXT:    vmerge.vvm v8, v10, v8, v0
320; CHECK-NEXT:    ret
321  %v = call <vscale x 4 x i32> @llvm.vp.select.nxv4i32(<vscale x 4 x i1> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c, i32 %evl)
322  ret <vscale x 4 x i32> %v
323}
324
325declare <vscale x 8 x i32> @llvm.vp.select.nxv8i32(<vscale x 8 x i1>, <vscale x 8 x i32>, <vscale x 8 x i32>, i32)
326
327define <vscale x 8 x i32> @select_nxv8i32(<vscale x 8 x i1> %a, <vscale x 8 x i32> %b, <vscale x 8 x i32> %c, i32 zeroext %evl) {
328; CHECK-LABEL: select_nxv8i32:
329; CHECK:       # %bb.0:
330; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, ma
331; CHECK-NEXT:    vmerge.vvm v8, v12, v8, v0
332; CHECK-NEXT:    ret
333  %v = call <vscale x 8 x i32> @llvm.vp.select.nxv8i32(<vscale x 8 x i1> %a, <vscale x 8 x i32> %b, <vscale x 8 x i32> %c, i32 %evl)
334  ret <vscale x 8 x i32> %v
335}
336
337declare <vscale x 16 x i32> @llvm.vp.select.nxv16i32(<vscale x 16 x i1>, <vscale x 16 x i32>, <vscale x 16 x i32>, i32)
338
339define <vscale x 16 x i32> @select_nxv16i32(<vscale x 16 x i1> %a, <vscale x 16 x i32> %b, <vscale x 16 x i32> %c, i32 zeroext %evl) {
340; CHECK-LABEL: select_nxv16i32:
341; CHECK:       # %bb.0:
342; CHECK-NEXT:    vsetvli zero, a0, e32, m8, ta, ma
343; CHECK-NEXT:    vmerge.vvm v8, v16, v8, v0
344; CHECK-NEXT:    ret
345  %v = call <vscale x 16 x i32> @llvm.vp.select.nxv16i32(<vscale x 16 x i1> %a, <vscale x 16 x i32> %b, <vscale x 16 x i32> %c, i32 %evl)
346  ret <vscale x 16 x i32> %v
347}
348
349declare <vscale x 32 x i32> @llvm.vp.select.nxv32i32(<vscale x 32 x i1>, <vscale x 32 x i32>, <vscale x 32 x i32>, i32)
350
351define <vscale x 32 x i32> @select_nxv32i32(<vscale x 32 x i1> %a, <vscale x 32 x i32> %b, <vscale x 32 x i32> %c, i32 zeroext %evl) {
352; CHECK-LABEL: select_nxv32i32:
353; CHECK:       # %bb.0:
354; CHECK-NEXT:    addi sp, sp, -16
355; CHECK-NEXT:    .cfi_def_cfa_offset 16
356; CHECK-NEXT:    csrr a1, vlenb
357; CHECK-NEXT:    slli a1, a1, 4
358; CHECK-NEXT:    sub sp, sp, a1
359; CHECK-NEXT:    .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
360; CHECK-NEXT:    csrr a1, vlenb
361; CHECK-NEXT:    slli a1, a1, 3
362; CHECK-NEXT:    add a1, sp, a1
363; CHECK-NEXT:    addi a1, a1, 16
364; CHECK-NEXT:    vs8r.v v8, (a1) # Unknown-size Folded Spill
365; CHECK-NEXT:    vsetvli a1, zero, e8, mf2, ta, ma
366; CHECK-NEXT:    vmv1r.v v24, v0
367; CHECK-NEXT:    csrr a3, vlenb
368; CHECK-NEXT:    slli a4, a3, 3
369; CHECK-NEXT:    slli a1, a3, 1
370; CHECK-NEXT:    srli a3, a3, 2
371; CHECK-NEXT:    add a4, a0, a4
372; CHECK-NEXT:    sub a5, a2, a1
373; CHECK-NEXT:    vl8re32.v v8, (a4)
374; CHECK-NEXT:    sltu a4, a2, a5
375; CHECK-NEXT:    addi a4, a4, -1
376; CHECK-NEXT:    vl8re32.v v0, (a0)
377; CHECK-NEXT:    addi a0, sp, 16
378; CHECK-NEXT:    vs8r.v v0, (a0) # Unknown-size Folded Spill
379; CHECK-NEXT:    vslidedown.vx v0, v24, a3
380; CHECK-NEXT:    and a4, a4, a5
381; CHECK-NEXT:    vsetvli zero, a4, e32, m8, ta, ma
382; CHECK-NEXT:    vmerge.vvm v16, v8, v16, v0
383; CHECK-NEXT:    bltu a2, a1, .LBB27_2
384; CHECK-NEXT:  # %bb.1:
385; CHECK-NEXT:    mv a2, a1
386; CHECK-NEXT:  .LBB27_2:
387; CHECK-NEXT:    vmv1r.v v0, v24
388; CHECK-NEXT:    csrr a0, vlenb
389; CHECK-NEXT:    slli a0, a0, 3
390; CHECK-NEXT:    add a0, sp, a0
391; CHECK-NEXT:    addi a0, a0, 16
392; CHECK-NEXT:    vl8r.v v8, (a0) # Unknown-size Folded Reload
393; CHECK-NEXT:    addi a0, sp, 16
394; CHECK-NEXT:    vl8r.v v24, (a0) # Unknown-size Folded Reload
395; CHECK-NEXT:    vsetvli zero, a2, e32, m8, ta, ma
396; CHECK-NEXT:    vmerge.vvm v8, v24, v8, v0
397; CHECK-NEXT:    csrr a0, vlenb
398; CHECK-NEXT:    slli a0, a0, 4
399; CHECK-NEXT:    add sp, sp, a0
400; CHECK-NEXT:    .cfi_def_cfa sp, 16
401; CHECK-NEXT:    addi sp, sp, 16
402; CHECK-NEXT:    .cfi_def_cfa_offset 0
403; CHECK-NEXT:    ret
404  %v = call <vscale x 32 x i32> @llvm.vp.select.nxv32i32(<vscale x 32 x i1> %a, <vscale x 32 x i32> %b, <vscale x 32 x i32> %c, i32 %evl)
405  ret <vscale x 32 x i32> %v
406}
407
408declare i32 @llvm.vscale.i32()
409
410define <vscale x 32 x i32> @select_evl_nxv32i32(<vscale x 32 x i1> %a, <vscale x 32 x i32> %b, <vscale x 32 x i32> %c) {
411; CHECK-LABEL: select_evl_nxv32i32:
412; CHECK:       # %bb.0:
413; CHECK-NEXT:    addi sp, sp, -16
414; CHECK-NEXT:    .cfi_def_cfa_offset 16
415; CHECK-NEXT:    csrr a1, vlenb
416; CHECK-NEXT:    slli a1, a1, 4
417; CHECK-NEXT:    sub sp, sp, a1
418; CHECK-NEXT:    .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
419; CHECK-NEXT:    csrr a1, vlenb
420; CHECK-NEXT:    slli a1, a1, 3
421; CHECK-NEXT:    add a1, sp, a1
422; CHECK-NEXT:    addi a1, a1, 16
423; CHECK-NEXT:    vs8r.v v8, (a1) # Unknown-size Folded Spill
424; CHECK-NEXT:    vsetvli a1, zero, e8, mf2, ta, ma
425; CHECK-NEXT:    vmv1r.v v24, v0
426; CHECK-NEXT:    csrr a1, vlenb
427; CHECK-NEXT:    slli a3, a1, 3
428; CHECK-NEXT:    slli a2, a1, 1
429; CHECK-NEXT:    srli a4, a1, 2
430; CHECK-NEXT:    add a3, a0, a3
431; CHECK-NEXT:    sub a5, a1, a2
432; CHECK-NEXT:    vl8re32.v v8, (a3)
433; CHECK-NEXT:    sltu a3, a1, a5
434; CHECK-NEXT:    addi a3, a3, -1
435; CHECK-NEXT:    vl8re32.v v0, (a0)
436; CHECK-NEXT:    addi a0, sp, 16
437; CHECK-NEXT:    vs8r.v v0, (a0) # Unknown-size Folded Spill
438; CHECK-NEXT:    vslidedown.vx v0, v24, a4
439; CHECK-NEXT:    and a3, a3, a5
440; CHECK-NEXT:    vsetvli zero, a3, e32, m8, ta, ma
441; CHECK-NEXT:    vmerge.vvm v16, v8, v16, v0
442; CHECK-NEXT:    bltu a1, a2, .LBB28_2
443; CHECK-NEXT:  # %bb.1:
444; CHECK-NEXT:    mv a1, a2
445; CHECK-NEXT:  .LBB28_2:
446; CHECK-NEXT:    vmv1r.v v0, v24
447; CHECK-NEXT:    csrr a0, vlenb
448; CHECK-NEXT:    slli a0, a0, 3
449; CHECK-NEXT:    add a0, sp, a0
450; CHECK-NEXT:    addi a0, a0, 16
451; CHECK-NEXT:    vl8r.v v8, (a0) # Unknown-size Folded Reload
452; CHECK-NEXT:    addi a0, sp, 16
453; CHECK-NEXT:    vl8r.v v24, (a0) # Unknown-size Folded Reload
454; CHECK-NEXT:    vsetvli zero, a1, e32, m8, ta, ma
455; CHECK-NEXT:    vmerge.vvm v8, v24, v8, v0
456; CHECK-NEXT:    csrr a0, vlenb
457; CHECK-NEXT:    slli a0, a0, 4
458; CHECK-NEXT:    add sp, sp, a0
459; CHECK-NEXT:    .cfi_def_cfa sp, 16
460; CHECK-NEXT:    addi sp, sp, 16
461; CHECK-NEXT:    .cfi_def_cfa_offset 0
462; CHECK-NEXT:    ret
463  %evl = call i32 @llvm.vscale.i32()
464  %evl0 = mul i32 %evl, 8
465  %v = call <vscale x 32 x i32> @llvm.vp.select.nxv32i32(<vscale x 32 x i1> %a, <vscale x 32 x i32> %b, <vscale x 32 x i32> %c, i32 %evl0)
466  ret <vscale x 32 x i32> %v
467}
468
469declare <vscale x 1 x i64> @llvm.vp.select.nxv1i64(<vscale x 1 x i1>, <vscale x 1 x i64>, <vscale x 1 x i64>, i32)
470
471define <vscale x 1 x i64> @select_nxv1i64(<vscale x 1 x i1> %a, <vscale x 1 x i64> %b, <vscale x 1 x i64> %c, i32 zeroext %evl) {
472; CHECK-LABEL: select_nxv1i64:
473; CHECK:       # %bb.0:
474; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, ma
475; CHECK-NEXT:    vmerge.vvm v8, v9, v8, v0
476; CHECK-NEXT:    ret
477  %v = call <vscale x 1 x i64> @llvm.vp.select.nxv1i64(<vscale x 1 x i1> %a, <vscale x 1 x i64> %b, <vscale x 1 x i64> %c, i32 %evl)
478  ret <vscale x 1 x i64> %v
479}
480
481declare <vscale x 2 x i64> @llvm.vp.select.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>, i32)
482
483define <vscale x 2 x i64> @select_nxv2i64(<vscale x 2 x i1> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c, i32 zeroext %evl) {
484; CHECK-LABEL: select_nxv2i64:
485; CHECK:       # %bb.0:
486; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, ma
487; CHECK-NEXT:    vmerge.vvm v8, v10, v8, v0
488; CHECK-NEXT:    ret
489  %v = call <vscale x 2 x i64> @llvm.vp.select.nxv2i64(<vscale x 2 x i1> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c, i32 %evl)
490  ret <vscale x 2 x i64> %v
491}
492
493declare <vscale x 4 x i64> @llvm.vp.select.nxv4i64(<vscale x 4 x i1>, <vscale x 4 x i64>, <vscale x 4 x i64>, i32)
494
495define <vscale x 4 x i64> @select_nxv4i64(<vscale x 4 x i1> %a, <vscale x 4 x i64> %b, <vscale x 4 x i64> %c, i32 zeroext %evl) {
496; CHECK-LABEL: select_nxv4i64:
497; CHECK:       # %bb.0:
498; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, ma
499; CHECK-NEXT:    vmerge.vvm v8, v12, v8, v0
500; CHECK-NEXT:    ret
501  %v = call <vscale x 4 x i64> @llvm.vp.select.nxv4i64(<vscale x 4 x i1> %a, <vscale x 4 x i64> %b, <vscale x 4 x i64> %c, i32 %evl)
502  ret <vscale x 4 x i64> %v
503}
504
505declare <vscale x 8 x i64> @llvm.vp.select.nxv8i64(<vscale x 8 x i1>, <vscale x 8 x i64>, <vscale x 8 x i64>, i32)
506
507define <vscale x 8 x i64> @select_nxv8i64(<vscale x 8 x i1> %a, <vscale x 8 x i64> %b, <vscale x 8 x i64> %c, i32 zeroext %evl) {
508; CHECK-LABEL: select_nxv8i64:
509; CHECK:       # %bb.0:
510; CHECK-NEXT:    vsetvli zero, a0, e64, m8, ta, ma
511; CHECK-NEXT:    vmerge.vvm v8, v16, v8, v0
512; CHECK-NEXT:    ret
513  %v = call <vscale x 8 x i64> @llvm.vp.select.nxv8i64(<vscale x 8 x i1> %a, <vscale x 8 x i64> %b, <vscale x 8 x i64> %c, i32 %evl)
514  ret <vscale x 8 x i64> %v
515}
516
517declare <vscale x 1 x half> @llvm.vp.select.nxv1f16(<vscale x 1 x i1>, <vscale x 1 x half>, <vscale x 1 x half>, i32)
518
519define <vscale x 1 x half> @select_nxv1f16(<vscale x 1 x i1> %a, <vscale x 1 x half> %b, <vscale x 1 x half> %c, i32 zeroext %evl) {
520; CHECK-LABEL: select_nxv1f16:
521; CHECK:       # %bb.0:
522; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma
523; CHECK-NEXT:    vmerge.vvm v8, v9, v8, v0
524; CHECK-NEXT:    ret
525  %v = call <vscale x 1 x half> @llvm.vp.select.nxv1f16(<vscale x 1 x i1> %a, <vscale x 1 x half> %b, <vscale x 1 x half> %c, i32 %evl)
526  ret <vscale x 1 x half> %v
527}
528
529declare <vscale x 2 x half> @llvm.vp.select.nxv2f16(<vscale x 2 x i1>, <vscale x 2 x half>, <vscale x 2 x half>, i32)
530
531define <vscale x 2 x half> @select_nxv2f16(<vscale x 2 x i1> %a, <vscale x 2 x half> %b, <vscale x 2 x half> %c, i32 zeroext %evl) {
532; CHECK-LABEL: select_nxv2f16:
533; CHECK:       # %bb.0:
534; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma
535; CHECK-NEXT:    vmerge.vvm v8, v9, v8, v0
536; CHECK-NEXT:    ret
537  %v = call <vscale x 2 x half> @llvm.vp.select.nxv2f16(<vscale x 2 x i1> %a, <vscale x 2 x half> %b, <vscale x 2 x half> %c, i32 %evl)
538  ret <vscale x 2 x half> %v
539}
540
541declare <vscale x 4 x half> @llvm.vp.select.nxv4f16(<vscale x 4 x i1>, <vscale x 4 x half>, <vscale x 4 x half>, i32)
542
543define <vscale x 4 x half> @select_nxv4f16(<vscale x 4 x i1> %a, <vscale x 4 x half> %b, <vscale x 4 x half> %c, i32 zeroext %evl) {
544; CHECK-LABEL: select_nxv4f16:
545; CHECK:       # %bb.0:
546; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, ma
547; CHECK-NEXT:    vmerge.vvm v8, v9, v8, v0
548; CHECK-NEXT:    ret
549  %v = call <vscale x 4 x half> @llvm.vp.select.nxv4f16(<vscale x 4 x i1> %a, <vscale x 4 x half> %b, <vscale x 4 x half> %c, i32 %evl)
550  ret <vscale x 4 x half> %v
551}
552
553declare <vscale x 8 x half> @llvm.vp.select.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>, i32)
554
555define <vscale x 8 x half> @select_nxv8f16(<vscale x 8 x i1> %a, <vscale x 8 x half> %b, <vscale x 8 x half> %c, i32 zeroext %evl) {
556; CHECK-LABEL: select_nxv8f16:
557; CHECK:       # %bb.0:
558; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, ma
559; CHECK-NEXT:    vmerge.vvm v8, v10, v8, v0
560; CHECK-NEXT:    ret
561  %v = call <vscale x 8 x half> @llvm.vp.select.nxv8f16(<vscale x 8 x i1> %a, <vscale x 8 x half> %b, <vscale x 8 x half> %c, i32 %evl)
562  ret <vscale x 8 x half> %v
563}
564
565declare <vscale x 16 x half> @llvm.vp.select.nxv16f16(<vscale x 16 x i1>, <vscale x 16 x half>, <vscale x 16 x half>, i32)
566
567define <vscale x 16 x half> @select_nxv16f16(<vscale x 16 x i1> %a, <vscale x 16 x half> %b, <vscale x 16 x half> %c, i32 zeroext %evl) {
568; CHECK-LABEL: select_nxv16f16:
569; CHECK:       # %bb.0:
570; CHECK-NEXT:    vsetvli zero, a0, e16, m4, ta, ma
571; CHECK-NEXT:    vmerge.vvm v8, v12, v8, v0
572; CHECK-NEXT:    ret
573  %v = call <vscale x 16 x half> @llvm.vp.select.nxv16f16(<vscale x 16 x i1> %a, <vscale x 16 x half> %b, <vscale x 16 x half> %c, i32 %evl)
574  ret <vscale x 16 x half> %v
575}
576
577declare <vscale x 32 x half> @llvm.vp.select.nxv32f16(<vscale x 32 x i1>, <vscale x 32 x half>, <vscale x 32 x half>, i32)
578
579define <vscale x 32 x half> @select_nxv32f16(<vscale x 32 x i1> %a, <vscale x 32 x half> %b, <vscale x 32 x half> %c, i32 zeroext %evl) {
580; CHECK-LABEL: select_nxv32f16:
581; CHECK:       # %bb.0:
582; CHECK-NEXT:    vsetvli zero, a0, e16, m8, ta, ma
583; CHECK-NEXT:    vmerge.vvm v8, v16, v8, v0
584; CHECK-NEXT:    ret
585  %v = call <vscale x 32 x half> @llvm.vp.select.nxv32f16(<vscale x 32 x i1> %a, <vscale x 32 x half> %b, <vscale x 32 x half> %c, i32 %evl)
586  ret <vscale x 32 x half> %v
587}
588
589declare <vscale x 1 x float> @llvm.vp.select.nxv1f32(<vscale x 1 x i1>, <vscale x 1 x float>, <vscale x 1 x float>, i32)
590
591define <vscale x 1 x float> @select_nxv1f32(<vscale x 1 x i1> %a, <vscale x 1 x float> %b, <vscale x 1 x float> %c, i32 zeroext %evl) {
592; CHECK-LABEL: select_nxv1f32:
593; CHECK:       # %bb.0:
594; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma
595; CHECK-NEXT:    vmerge.vvm v8, v9, v8, v0
596; CHECK-NEXT:    ret
597  %v = call <vscale x 1 x float> @llvm.vp.select.nxv1f32(<vscale x 1 x i1> %a, <vscale x 1 x float> %b, <vscale x 1 x float> %c, i32 %evl)
598  ret <vscale x 1 x float> %v
599}
600
601declare <vscale x 2 x float> @llvm.vp.select.nxv2f32(<vscale x 2 x i1>, <vscale x 2 x float>, <vscale x 2 x float>, i32)
602
603define <vscale x 2 x float> @select_nxv2f32(<vscale x 2 x i1> %a, <vscale x 2 x float> %b, <vscale x 2 x float> %c, i32 zeroext %evl) {
604; CHECK-LABEL: select_nxv2f32:
605; CHECK:       # %bb.0:
606; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma
607; CHECK-NEXT:    vmerge.vvm v8, v9, v8, v0
608; CHECK-NEXT:    ret
609  %v = call <vscale x 2 x float> @llvm.vp.select.nxv2f32(<vscale x 2 x i1> %a, <vscale x 2 x float> %b, <vscale x 2 x float> %c, i32 %evl)
610  ret <vscale x 2 x float> %v
611}
612
613declare <vscale x 4 x float> @llvm.vp.select.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>, i32)
614
615define <vscale x 4 x float> @select_nxv4f32(<vscale x 4 x i1> %a, <vscale x 4 x float> %b, <vscale x 4 x float> %c, i32 zeroext %evl) {
616; CHECK-LABEL: select_nxv4f32:
617; CHECK:       # %bb.0:
618; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma
619; CHECK-NEXT:    vmerge.vvm v8, v10, v8, v0
620; CHECK-NEXT:    ret
621  %v = call <vscale x 4 x float> @llvm.vp.select.nxv4f32(<vscale x 4 x i1> %a, <vscale x 4 x float> %b, <vscale x 4 x float> %c, i32 %evl)
622  ret <vscale x 4 x float> %v
623}
624
625declare <vscale x 8 x float> @llvm.vp.select.nxv8f32(<vscale x 8 x i1>, <vscale x 8 x float>, <vscale x 8 x float>, i32)
626
627define <vscale x 8 x float> @select_nxv8f32(<vscale x 8 x i1> %a, <vscale x 8 x float> %b, <vscale x 8 x float> %c, i32 zeroext %evl) {
628; CHECK-LABEL: select_nxv8f32:
629; CHECK:       # %bb.0:
630; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, ma
631; CHECK-NEXT:    vmerge.vvm v8, v12, v8, v0
632; CHECK-NEXT:    ret
633  %v = call <vscale x 8 x float> @llvm.vp.select.nxv8f32(<vscale x 8 x i1> %a, <vscale x 8 x float> %b, <vscale x 8 x float> %c, i32 %evl)
634  ret <vscale x 8 x float> %v
635}
636
637declare <vscale x 16 x float> @llvm.vp.select.nxv16f32(<vscale x 16 x i1>, <vscale x 16 x float>, <vscale x 16 x float>, i32)
638
639define <vscale x 16 x float> @select_nxv16f32(<vscale x 16 x i1> %a, <vscale x 16 x float> %b, <vscale x 16 x float> %c, i32 zeroext %evl) {
640; CHECK-LABEL: select_nxv16f32:
641; CHECK:       # %bb.0:
642; CHECK-NEXT:    vsetvli zero, a0, e32, m8, ta, ma
643; CHECK-NEXT:    vmerge.vvm v8, v16, v8, v0
644; CHECK-NEXT:    ret
645  %v = call <vscale x 16 x float> @llvm.vp.select.nxv16f32(<vscale x 16 x i1> %a, <vscale x 16 x float> %b, <vscale x 16 x float> %c, i32 %evl)
646  ret <vscale x 16 x float> %v
647}
648
649declare <vscale x 1 x double> @llvm.vp.select.nxv1f64(<vscale x 1 x i1>, <vscale x 1 x double>, <vscale x 1 x double>, i32)
650
651define <vscale x 1 x double> @select_nxv1f64(<vscale x 1 x i1> %a, <vscale x 1 x double> %b, <vscale x 1 x double> %c, i32 zeroext %evl) {
652; CHECK-LABEL: select_nxv1f64:
653; CHECK:       # %bb.0:
654; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, ma
655; CHECK-NEXT:    vmerge.vvm v8, v9, v8, v0
656; CHECK-NEXT:    ret
657  %v = call <vscale x 1 x double> @llvm.vp.select.nxv1f64(<vscale x 1 x i1> %a, <vscale x 1 x double> %b, <vscale x 1 x double> %c, i32 %evl)
658  ret <vscale x 1 x double> %v
659}
660
661declare <vscale x 2 x double> @llvm.vp.select.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>, i32)
662
663define <vscale x 2 x double> @select_nxv2f64(<vscale x 2 x i1> %a, <vscale x 2 x double> %b, <vscale x 2 x double> %c, i32 zeroext %evl) {
664; CHECK-LABEL: select_nxv2f64:
665; CHECK:       # %bb.0:
666; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, ma
667; CHECK-NEXT:    vmerge.vvm v8, v10, v8, v0
668; CHECK-NEXT:    ret
669  %v = call <vscale x 2 x double> @llvm.vp.select.nxv2f64(<vscale x 2 x i1> %a, <vscale x 2 x double> %b, <vscale x 2 x double> %c, i32 %evl)
670  ret <vscale x 2 x double> %v
671}
672
673declare <vscale x 4 x double> @llvm.vp.select.nxv4f64(<vscale x 4 x i1>, <vscale x 4 x double>, <vscale x 4 x double>, i32)
674
675define <vscale x 4 x double> @select_nxv4f64(<vscale x 4 x i1> %a, <vscale x 4 x double> %b, <vscale x 4 x double> %c, i32 zeroext %evl) {
676; CHECK-LABEL: select_nxv4f64:
677; CHECK:       # %bb.0:
678; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, ma
679; CHECK-NEXT:    vmerge.vvm v8, v12, v8, v0
680; CHECK-NEXT:    ret
681  %v = call <vscale x 4 x double> @llvm.vp.select.nxv4f64(<vscale x 4 x i1> %a, <vscale x 4 x double> %b, <vscale x 4 x double> %c, i32 %evl)
682  ret <vscale x 4 x double> %v
683}
684
685declare <vscale x 8 x double> @llvm.vp.select.nxv8f64(<vscale x 8 x i1>, <vscale x 8 x double>, <vscale x 8 x double>, i32)
686
687define <vscale x 8 x double> @select_nxv8f64(<vscale x 8 x i1> %a, <vscale x 8 x double> %b, <vscale x 8 x double> %c, i32 zeroext %evl) {
688; CHECK-LABEL: select_nxv8f64:
689; CHECK:       # %bb.0:
690; CHECK-NEXT:    vsetvli zero, a0, e64, m8, ta, ma
691; CHECK-NEXT:    vmerge.vvm v8, v16, v8, v0
692; CHECK-NEXT:    ret
693  %v = call <vscale x 8 x double> @llvm.vp.select.nxv8f64(<vscale x 8 x i1> %a, <vscale x 8 x double> %b, <vscale x 8 x double> %c, i32 %evl)
694  ret <vscale x 8 x double> %v
695}
696
697declare <vscale x 16 x double> @llvm.vp.select.nxv16f64(<vscale x 16 x i1>, <vscale x 16 x double>, <vscale x 16 x double>, i32)
698
699define <vscale x 16 x double> @select_nxv16f64(<vscale x 16 x i1> %a, <vscale x 16 x double> %b, <vscale x 16 x double> %c, i32 zeroext %evl) {
700; CHECK-LABEL: select_nxv16f64:
701; CHECK:       # %bb.0:
702; CHECK-NEXT:    addi sp, sp, -16
703; CHECK-NEXT:    .cfi_def_cfa_offset 16
704; CHECK-NEXT:    csrr a1, vlenb
705; CHECK-NEXT:    slli a1, a1, 4
706; CHECK-NEXT:    sub sp, sp, a1
707; CHECK-NEXT:    .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
708; CHECK-NEXT:    csrr a1, vlenb
709; CHECK-NEXT:    slli a1, a1, 3
710; CHECK-NEXT:    add a1, sp, a1
711; CHECK-NEXT:    addi a1, a1, 16
712; CHECK-NEXT:    vs8r.v v8, (a1) # Unknown-size Folded Spill
713; CHECK-NEXT:    vsetvli a1, zero, e8, mf4, ta, ma
714; CHECK-NEXT:    vmv1r.v v24, v0
715; CHECK-NEXT:    csrr a1, vlenb
716; CHECK-NEXT:    slli a3, a1, 3
717; CHECK-NEXT:    sub a4, a2, a1
718; CHECK-NEXT:    add a3, a0, a3
719; CHECK-NEXT:    sltu a5, a2, a4
720; CHECK-NEXT:    vl8re64.v v8, (a3)
721; CHECK-NEXT:    addi a5, a5, -1
722; CHECK-NEXT:    srli a3, a1, 3
723; CHECK-NEXT:    vl8re64.v v0, (a0)
724; CHECK-NEXT:    addi a0, sp, 16
725; CHECK-NEXT:    vs8r.v v0, (a0) # Unknown-size Folded Spill
726; CHECK-NEXT:    vslidedown.vx v0, v24, a3
727; CHECK-NEXT:    and a4, a5, a4
728; CHECK-NEXT:    vsetvli zero, a4, e64, m8, ta, ma
729; CHECK-NEXT:    vmerge.vvm v16, v8, v16, v0
730; CHECK-NEXT:    bltu a2, a1, .LBB48_2
731; CHECK-NEXT:  # %bb.1:
732; CHECK-NEXT:    mv a2, a1
733; CHECK-NEXT:  .LBB48_2:
734; CHECK-NEXT:    vmv1r.v v0, v24
735; CHECK-NEXT:    csrr a0, vlenb
736; CHECK-NEXT:    slli a0, a0, 3
737; CHECK-NEXT:    add a0, sp, a0
738; CHECK-NEXT:    addi a0, a0, 16
739; CHECK-NEXT:    vl8r.v v8, (a0) # Unknown-size Folded Reload
740; CHECK-NEXT:    addi a0, sp, 16
741; CHECK-NEXT:    vl8r.v v24, (a0) # Unknown-size Folded Reload
742; CHECK-NEXT:    vsetvli zero, a2, e64, m8, ta, ma
743; CHECK-NEXT:    vmerge.vvm v8, v24, v8, v0
744; CHECK-NEXT:    csrr a0, vlenb
745; CHECK-NEXT:    slli a0, a0, 4
746; CHECK-NEXT:    add sp, sp, a0
747; CHECK-NEXT:    .cfi_def_cfa sp, 16
748; CHECK-NEXT:    addi sp, sp, 16
749; CHECK-NEXT:    .cfi_def_cfa_offset 0
750; CHECK-NEXT:    ret
751  %v = call <vscale x 16 x double> @llvm.vp.select.nxv16f64(<vscale x 16 x i1> %a, <vscale x 16 x double> %b, <vscale x 16 x double> %c, i32 %evl)
752  ret <vscale x 16 x double> %v
753}
754
755define <vscale x 2 x i1> @select_zero(<vscale x 2 x i1> %x, <vscale x 2 x i1> %y, <vscale x 2 x i1> %m, i32 zeroext %evl) {
756; CHECK-LABEL: select_zero:
757; CHECK:       # %bb.0:
758; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, ma
759; CHECK-NEXT:    vmand.mm v0, v0, v8
760; CHECK-NEXT:    ret
761  %a = call <vscale x 2 x i1> @llvm.vp.select.nxv2i1(<vscale x 2 x i1> %x, <vscale x 2 x i1> %y, <vscale x 2 x i1> zeroinitializer, i32 %evl)
762  ret <vscale x 2 x i1> %a
763}
764
765define <vscale x 2 x i1> @select_one(<vscale x 2 x i1> %x, <vscale x 2 x i1> %y, <vscale x 2 x i1> %m, i32 zeroext %evl) {
766; CHECK-LABEL: select_one:
767; CHECK:       # %bb.0:
768; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, ma
769; CHECK-NEXT:    vmorn.mm v0, v8, v0
770; CHECK-NEXT:    ret
771  %a = call <vscale x 2 x i1> @llvm.vp.select.nxv2i1(<vscale x 2 x i1> %x, <vscale x 2 x i1> %y, <vscale x 2 x i1> splat (i1 true), i32 %evl)
772  ret <vscale x 2 x i1> %a
773}
774
775define <vscale x 2 x i1> @select_x_zero(<vscale x 2 x i1> %x, <vscale x 2 x i1> %y, i32 zeroext %evl) {
776; CHECK-LABEL: select_x_zero:
777; CHECK:       # %bb.0:
778; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, ma
779; CHECK-NEXT:    vmand.mm v0, v0, v8
780; CHECK-NEXT:    ret
781  %a = call <vscale x 2 x i1> @llvm.vp.select.nxv2i1(<vscale x 2 x i1> %x, <vscale x 2 x i1> %y, <vscale x 2 x i1> zeroinitializer, i32 %evl)
782  ret <vscale x 2 x i1> %a
783}
784
785define <vscale x 2 x i1> @select_x_one(<vscale x 2 x i1> %x, <vscale x 2 x i1> %y, i32 zeroext %evl) {
786; CHECK-LABEL: select_x_one:
787; CHECK:       # %bb.0:
788; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, ma
789; CHECK-NEXT:    vmorn.mm v0, v8, v0
790; CHECK-NEXT:    ret
791  %a = call <vscale x 2 x i1> @llvm.vp.select.nxv2i1(<vscale x 2 x i1> %x, <vscale x 2 x i1> %y, <vscale x 2 x i1> splat (i1 true), i32 %evl)
792  ret <vscale x 2 x i1> %a
793}
794
795define <vscale x 2 x i1> @select_zero_x(<vscale x 2 x i1> %x, <vscale x 2 x i1> %y, i32 zeroext %evl) {
796; CHECK-LABEL: select_zero_x:
797; CHECK:       # %bb.0:
798; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, ma
799; CHECK-NEXT:    vmandn.mm v0, v8, v0
800; CHECK-NEXT:    ret
801  %a = call <vscale x 2 x i1> @llvm.vp.select.nxv2i1(<vscale x 2 x i1> %x, <vscale x 2 x i1> zeroinitializer, <vscale x 2 x i1> %y, i32 %evl)
802 ret <vscale x 2 x i1> %a
803}
804
805define <vscale x 2 x i1> @select_one_x(<vscale x 2 x i1> %x, <vscale x 2 x i1> %y, i32 zeroext %evl) {
806; CHECK-LABEL: select_one_x:
807; CHECK:       # %bb.0:
808; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, ma
809; CHECK-NEXT:    vmor.mm v0, v0, v8
810; CHECK-NEXT:    ret
811  %a = call <vscale x 2 x i1> @llvm.vp.select.nxv2i1(<vscale x 2 x i1> %x, <vscale x 2 x i1> splat (i1 true), <vscale x 2 x i1> %y, i32 %evl)
812 ret <vscale x 2 x i1> %a
813}
814
815define <vscale x 2 x i1> @select_cond_cond_x(<vscale x 2 x i1> %x, <vscale x 2 x i1> %y, <vscale x 2 x i1> %m, i32 zeroext %evl) {
816; CHECK-LABEL: select_cond_cond_x:
817; CHECK:       # %bb.0:
818; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, ma
819; CHECK-NEXT:    vmor.mm v0, v0, v8
820; CHECK-NEXT:    ret
821  %a = call <vscale x 2 x i1> @llvm.vp.select.nxv2i1(<vscale x 2 x i1> %x, <vscale x 2 x i1> %x, <vscale x 2 x i1> %y, i32 %evl)
822  ret <vscale x 2 x i1> %a
823}
824
825define <vscale x 2 x i1> @select_cond_x_cond(<vscale x 2 x i1> %x, <vscale x 2 x i1> %y, <vscale x 2 x i1> %m, i32 zeroext %evl) {
826; CHECK-LABEL: select_cond_x_cond:
827; CHECK:       # %bb.0:
828; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, ma
829; CHECK-NEXT:    vmand.mm v0, v0, v8
830; CHECK-NEXT:    ret
831  %a = call <vscale x 2 x i1> @llvm.vp.select.nxv2i1(<vscale x 2 x i1> %x, <vscale x 2 x i1> %y, <vscale x 2 x i1> %x, i32 %evl)
832  ret <vscale x 2 x i1> %a
833}
834
835define <vscale x 2 x i1> @select_undef_T_F(<vscale x 2 x i1> %x, <vscale x 2 x i1> %y, i32 zeroext %evl) {
836; CHECK-LABEL: select_undef_T_F:
837; CHECK:       # %bb.0:
838; CHECK-NEXT:    vsetivli zero, 1, e8, m1, ta, ma
839; CHECK-NEXT:    vmv1r.v v0, v8
840; CHECK-NEXT:    ret
841  %a = call <vscale x 2 x i1> @llvm.vp.select.nxv2i1(<vscale x 2 x i1> poison, <vscale x 2 x i1> %x, <vscale x 2 x i1> %y, i32 %evl)
842  ret <vscale x 2 x i1> %a
843}
844
845define <vscale x 2 x i1> @select_undef_undef_F(<vscale x 2 x i1> %x, i32 zeroext %evl) {
846; CHECK-LABEL: select_undef_undef_F:
847; CHECK:       # %bb.0:
848; CHECK-NEXT:    ret
849  %a = call <vscale x 2 x i1> @llvm.vp.select.nxv2i1(<vscale x 2 x i1> poison, <vscale x 2 x i1> undef, <vscale x 2 x i1> %x, i32 %evl)
850  ret <vscale x 2 x i1> %a
851}
852
853define <vscale x 2 x i1> @select_unknown_undef_F(<vscale x 2 x i1> %x, <vscale x 2 x i1> %y, i32 zeroext %evl) {
854; CHECK-LABEL: select_unknown_undef_F:
855; CHECK:       # %bb.0:
856; CHECK-NEXT:    vsetivli zero, 1, e8, m1, ta, ma
857; CHECK-NEXT:    vmv1r.v v0, v8
858; CHECK-NEXT:    ret
859  %a = call <vscale x 2 x i1> @llvm.vp.select.nxv2i1(<vscale x 2 x i1> %x, <vscale x 2 x i1> undef, <vscale x 2 x i1> %y, i32 %evl)
860  ret <vscale x 2 x i1> %a
861}
862
863define <vscale x 2 x i1> @select_unknown_T_undef(<vscale x 2 x i1> %x, <vscale x 2 x i1> %y, i32 zeroext %evl) {
864; CHECK-LABEL: select_unknown_T_undef:
865; CHECK:       # %bb.0:
866; CHECK-NEXT:    vsetivli zero, 1, e8, m1, ta, ma
867; CHECK-NEXT:    vmv1r.v v0, v8
868; CHECK-NEXT:    ret
869  %a = call <vscale x 2 x i1> @llvm.vp.select.nxv2i1(<vscale x 2 x i1> %x, <vscale x 2 x i1> %y, <vscale x 2 x i1> poison, i32 %evl)
870  ret <vscale x 2 x i1> %a
871}
872
873define <vscale x 2 x i1> @select_false_T_F(<vscale x 2 x i1> %x, <vscale x 2 x i1> %y, <vscale x 2 x i1> %z, i32 zeroext %evl) {
874; CHECK-LABEL: select_false_T_F:
875; CHECK:       # %bb.0:
876; CHECK-NEXT:    vsetivli zero, 1, e8, m1, ta, ma
877; CHECK-NEXT:    vmv1r.v v0, v9
878; CHECK-NEXT:    ret
879  %a = call <vscale x 2 x i1> @llvm.vp.select.nxv2i1(<vscale x 2 x i1> zeroinitializer, <vscale x 2 x i1> %y, <vscale x 2 x i1> %z, i32 %evl)
880  ret <vscale x 2 x i1> %a
881}
882
883define <vscale x 2 x i1> @select_unknown_T_T(<vscale x 2 x i1> %x, <vscale x 2 x i1> %y, i32 zeroext %evl) {
884; CHECK-LABEL: select_unknown_T_T:
885; CHECK:       # %bb.0:
886; CHECK-NEXT:    vsetivli zero, 1, e8, m1, ta, ma
887; CHECK-NEXT:    vmv1r.v v0, v8
888; CHECK-NEXT:    ret
889  %a = call <vscale x 2 x i1> @llvm.vp.select.nxv2i1(<vscale x 2 x i1> %x, <vscale x 2 x i1> %y, <vscale x 2 x i1> %y, i32 %evl)
890  ret <vscale x 2 x i1> %a
891}
892