xref: /llvm-project/llvm/test/CodeGen/RISCV/rvv/vselect-bf16.ll (revision b6c0f1bfa79a3a32d841ac5ab1f94c3aee3b5d90) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+m,+d,+v,+zfbfmin,+zvfbfmin -target-abi=ilp32d \
3; RUN:     -verify-machineinstrs < %s | FileCheck %s
4; RUN: llc -mtriple=riscv64 -mattr=+m,+d,+v,+zfbfmin,+zvfbfmin -target-abi=lp64d \
5; RUN:     -verify-machineinstrs < %s | FileCheck %s
6; RUN: llc -mtriple=riscv32 -mattr=+m,+d,+v,+zvfh,+zfbfmin,+zvfbfmin -target-abi=ilp32d \
7; RUN:     -verify-machineinstrs < %s | FileCheck %s
8; RUN: llc -mtriple=riscv64 -mattr=+m,+d,+v,+zvfh,+zfbfmin,+zvfbfmin -target-abi=lp64d \
9; RUN:     -verify-machineinstrs < %s | FileCheck %s
10
11define <vscale x 1 x bfloat> @vfmerge_vv_nxv1bf16(<vscale x 1 x bfloat> %va, <vscale x 1 x bfloat> %vb, <vscale x 1 x i1> %cond) {
12; CHECK-LABEL: vfmerge_vv_nxv1bf16:
13; CHECK:       # %bb.0:
14; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, ma
15; CHECK-NEXT:    vmerge.vvm v8, v9, v8, v0
16; CHECK-NEXT:    ret
17  %vc = select <vscale x 1 x i1> %cond, <vscale x 1 x bfloat> %va, <vscale x 1 x bfloat> %vb
18  ret <vscale x 1 x bfloat> %vc
19}
20
21define <vscale x 1 x bfloat> @vfmerge_fv_nxv1bf16(<vscale x 1 x bfloat> %va, bfloat %b, <vscale x 1 x i1> %cond) {
22; CHECK-LABEL: vfmerge_fv_nxv1bf16:
23; CHECK:       # %bb.0:
24; CHECK-NEXT:    fmv.x.h a0, fa0
25; CHECK-NEXT:    vsetvli a1, zero, e16, mf4, ta, ma
26; CHECK-NEXT:    vmv.v.x v9, a0
27; CHECK-NEXT:    vmerge.vvm v8, v8, v9, v0
28; CHECK-NEXT:    ret
29  %head = insertelement <vscale x 1 x bfloat> poison, bfloat %b, i32 0
30  %splat = shufflevector <vscale x 1 x bfloat> %head, <vscale x 1 x bfloat> poison, <vscale x 1 x i32> zeroinitializer
31  %vc = select <vscale x 1 x i1> %cond, <vscale x 1 x bfloat> %splat, <vscale x 1 x bfloat> %va
32  ret <vscale x 1 x bfloat> %vc
33}
34
35define <vscale x 2 x bfloat> @vfmerge_vv_nxv2bf16(<vscale x 2 x bfloat> %va, <vscale x 2 x bfloat> %vb, <vscale x 2 x i1> %cond) {
36; CHECK-LABEL: vfmerge_vv_nxv2bf16:
37; CHECK:       # %bb.0:
38; CHECK-NEXT:    vsetvli a0, zero, e16, mf2, ta, ma
39; CHECK-NEXT:    vmerge.vvm v8, v9, v8, v0
40; CHECK-NEXT:    ret
41  %vc = select <vscale x 2 x i1> %cond, <vscale x 2 x bfloat> %va, <vscale x 2 x bfloat> %vb
42  ret <vscale x 2 x bfloat> %vc
43}
44
45define <vscale x 2 x bfloat> @vfmerge_fv_nxv2bf16(<vscale x 2 x bfloat> %va, bfloat %b, <vscale x 2 x i1> %cond) {
46; CHECK-LABEL: vfmerge_fv_nxv2bf16:
47; CHECK:       # %bb.0:
48; CHECK-NEXT:    fmv.x.h a0, fa0
49; CHECK-NEXT:    vsetvli a1, zero, e16, mf2, ta, ma
50; CHECK-NEXT:    vmv.v.x v9, a0
51; CHECK-NEXT:    vmerge.vvm v8, v8, v9, v0
52; CHECK-NEXT:    ret
53  %head = insertelement <vscale x 2 x bfloat> poison, bfloat %b, i32 0
54  %splat = shufflevector <vscale x 2 x bfloat> %head, <vscale x 2 x bfloat> poison, <vscale x 2 x i32> zeroinitializer
55  %vc = select <vscale x 2 x i1> %cond, <vscale x 2 x bfloat> %splat, <vscale x 2 x bfloat> %va
56  ret <vscale x 2 x bfloat> %vc
57}
58
59define <vscale x 4 x bfloat> @vfmerge_vv_nxv4bf16(<vscale x 4 x bfloat> %va, <vscale x 4 x bfloat> %vb, <vscale x 4 x i1> %cond) {
60; CHECK-LABEL: vfmerge_vv_nxv4bf16:
61; CHECK:       # %bb.0:
62; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, ma
63; CHECK-NEXT:    vmerge.vvm v8, v9, v8, v0
64; CHECK-NEXT:    ret
65  %vc = select <vscale x 4 x i1> %cond, <vscale x 4 x bfloat> %va, <vscale x 4 x bfloat> %vb
66  ret <vscale x 4 x bfloat> %vc
67}
68
69define <vscale x 4 x bfloat> @vfmerge_fv_nxv4bf16(<vscale x 4 x bfloat> %va, bfloat %b, <vscale x 4 x i1> %cond) {
70; CHECK-LABEL: vfmerge_fv_nxv4bf16:
71; CHECK:       # %bb.0:
72; CHECK-NEXT:    fmv.x.h a0, fa0
73; CHECK-NEXT:    vsetvli a1, zero, e16, m1, ta, ma
74; CHECK-NEXT:    vmv.v.x v9, a0
75; CHECK-NEXT:    vmerge.vvm v8, v8, v9, v0
76; CHECK-NEXT:    ret
77  %head = insertelement <vscale x 4 x bfloat> poison, bfloat %b, i32 0
78  %splat = shufflevector <vscale x 4 x bfloat> %head, <vscale x 4 x bfloat> poison, <vscale x 4 x i32> zeroinitializer
79  %vc = select <vscale x 4 x i1> %cond, <vscale x 4 x bfloat> %splat, <vscale x 4 x bfloat> %va
80  ret <vscale x 4 x bfloat> %vc
81}
82
83define <vscale x 8 x bfloat> @vfmerge_vv_nxv8bf16(<vscale x 8 x bfloat> %va, <vscale x 8 x bfloat> %vb, <vscale x 8 x i1> %cond) {
84; CHECK-LABEL: vfmerge_vv_nxv8bf16:
85; CHECK:       # %bb.0:
86; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, ma
87; CHECK-NEXT:    vmerge.vvm v8, v10, v8, v0
88; CHECK-NEXT:    ret
89  %vc = select <vscale x 8 x i1> %cond, <vscale x 8 x bfloat> %va, <vscale x 8 x bfloat> %vb
90  ret <vscale x 8 x bfloat> %vc
91}
92
93define <vscale x 8 x bfloat> @vfmerge_fv_nxv8bf16(<vscale x 8 x bfloat> %va, bfloat %b, <vscale x 8 x i1> %cond) {
94; CHECK-LABEL: vfmerge_fv_nxv8bf16:
95; CHECK:       # %bb.0:
96; CHECK-NEXT:    fmv.x.h a0, fa0
97; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, ma
98; CHECK-NEXT:    vmv.v.x v10, a0
99; CHECK-NEXT:    vmerge.vvm v8, v8, v10, v0
100; CHECK-NEXT:    ret
101  %head = insertelement <vscale x 8 x bfloat> poison, bfloat %b, i32 0
102  %splat = shufflevector <vscale x 8 x bfloat> %head, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
103  %vc = select <vscale x 8 x i1> %cond, <vscale x 8 x bfloat> %splat, <vscale x 8 x bfloat> %va
104  ret <vscale x 8 x bfloat> %vc
105}
106
107define <vscale x 8 x bfloat> @vfmerge_zv_nxv8bf16(<vscale x 8 x bfloat> %va, <vscale x 8 x i1> %cond) {
108; CHECK-LABEL: vfmerge_zv_nxv8bf16:
109; CHECK:       # %bb.0:
110; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, ma
111; CHECK-NEXT:    vmv.v.i v10, 0
112; CHECK-NEXT:    vmerge.vvm v8, v8, v10, v0
113; CHECK-NEXT:    ret
114  %vc = select <vscale x 8 x i1> %cond, <vscale x 8 x bfloat> splat (bfloat zeroinitializer), <vscale x 8 x bfloat> %va
115  ret <vscale x 8 x bfloat> %vc
116}
117
118define <vscale x 8 x bfloat> @vmerge_truelhs_nxv8bf16_0(<vscale x 8 x bfloat> %va, <vscale x 8 x bfloat> %vb) {
119; CHECK-LABEL: vmerge_truelhs_nxv8bf16_0:
120; CHECK:       # %bb.0:
121; CHECK-NEXT:    ret
122  %vc = select <vscale x 8 x i1> splat (i1 1), <vscale x 8 x bfloat> %va, <vscale x 8 x bfloat> %vb
123  ret <vscale x 8 x bfloat> %vc
124}
125
126define <vscale x 8 x bfloat> @vmerge_falselhs_nxv8bf16_0(<vscale x 8 x bfloat> %va, <vscale x 8 x bfloat> %vb) {
127; CHECK-LABEL: vmerge_falselhs_nxv8bf16_0:
128; CHECK:       # %bb.0:
129; CHECK-NEXT:    vsetivli zero, 1, e8, m1, ta, ma
130; CHECK-NEXT:    vmv2r.v v8, v10
131; CHECK-NEXT:    ret
132  %vc = select <vscale x 8 x i1> zeroinitializer, <vscale x 8 x bfloat> %va, <vscale x 8 x bfloat> %vb
133  ret <vscale x 8 x bfloat> %vc
134}
135
136define <vscale x 16 x bfloat> @vfmerge_vv_nxv16bf16(<vscale x 16 x bfloat> %va, <vscale x 16 x bfloat> %vb, <vscale x 16 x i1> %cond) {
137; CHECK-LABEL: vfmerge_vv_nxv16bf16:
138; CHECK:       # %bb.0:
139; CHECK-NEXT:    vsetvli a0, zero, e16, m4, ta, ma
140; CHECK-NEXT:    vmerge.vvm v8, v12, v8, v0
141; CHECK-NEXT:    ret
142  %vc = select <vscale x 16 x i1> %cond, <vscale x 16 x bfloat> %va, <vscale x 16 x bfloat> %vb
143  ret <vscale x 16 x bfloat> %vc
144}
145
146define <vscale x 16 x bfloat> @vfmerge_fv_nxv16bf16(<vscale x 16 x bfloat> %va, bfloat %b, <vscale x 16 x i1> %cond) {
147; CHECK-LABEL: vfmerge_fv_nxv16bf16:
148; CHECK:       # %bb.0:
149; CHECK-NEXT:    fmv.x.h a0, fa0
150; CHECK-NEXT:    vsetvli a1, zero, e16, m4, ta, ma
151; CHECK-NEXT:    vmv.v.x v12, a0
152; CHECK-NEXT:    vmerge.vvm v8, v8, v12, v0
153; CHECK-NEXT:    ret
154  %head = insertelement <vscale x 16 x bfloat> poison, bfloat %b, i32 0
155  %splat = shufflevector <vscale x 16 x bfloat> %head, <vscale x 16 x bfloat> poison, <vscale x 16 x i32> zeroinitializer
156  %vc = select <vscale x 16 x i1> %cond, <vscale x 16 x bfloat> %splat, <vscale x 16 x bfloat> %va
157  ret <vscale x 16 x bfloat> %vc
158}
159
160define <vscale x 32 x bfloat> @vfmerge_vv_nxv32bf16(<vscale x 32 x bfloat> %va, <vscale x 32 x bfloat> %vb, <vscale x 32 x i1> %cond) {
161; CHECK-LABEL: vfmerge_vv_nxv32bf16:
162; CHECK:       # %bb.0:
163; CHECK-NEXT:    vsetvli a0, zero, e16, m8, ta, ma
164; CHECK-NEXT:    vmerge.vvm v8, v16, v8, v0
165; CHECK-NEXT:    ret
166  %vc = select <vscale x 32 x i1> %cond, <vscale x 32 x bfloat> %va, <vscale x 32 x bfloat> %vb
167  ret <vscale x 32 x bfloat> %vc
168}
169
170define <vscale x 32 x bfloat> @vfmerge_fv_nxv32bf16(<vscale x 32 x bfloat> %va, bfloat %b, <vscale x 32 x i1> %cond) {
171; CHECK-LABEL: vfmerge_fv_nxv32bf16:
172; CHECK:       # %bb.0:
173; CHECK-NEXT:    fmv.x.h a0, fa0
174; CHECK-NEXT:    vsetvli a1, zero, e16, m8, ta, ma
175; CHECK-NEXT:    vmv.v.x v16, a0
176; CHECK-NEXT:    vmerge.vvm v8, v8, v16, v0
177; CHECK-NEXT:    ret
178  %head = insertelement <vscale x 32 x bfloat> poison, bfloat %b, i32 0
179  %splat = shufflevector <vscale x 32 x bfloat> %head, <vscale x 32 x bfloat> poison, <vscale x 32 x i32> zeroinitializer
180  %vc = select <vscale x 32 x i1> %cond, <vscale x 32 x bfloat> %splat, <vscale x 32 x bfloat> %va
181  ret <vscale x 32 x bfloat> %vc
182}
183