xref: /llvm-project/llvm/test/CodeGen/RISCV/rvv/vscale-power-of-two.ll (revision 9122c5235ec85ce0c0ad337e862b006e7b349d84) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv64 -mattr=+v,+m -verify-machineinstrs < %s | FileCheck %s
3; RUN: llc -mtriple=riscv64 -mattr=+Zve64x,+m -verify-machineinstrs < %s | FileCheck %s
4
5declare i64 @llvm.vscale.i64()
6
7define i64 @vscale_lshr(i64 %TC) {
8; CHECK-LABEL: vscale_lshr:
9; CHECK:       # %bb.0:
10; CHECK-NEXT:    csrr a1, vlenb
11; CHECK-NEXT:    srli a1, a1, 6
12; CHECK-NEXT:    addi a1, a1, -1
13; CHECK-NEXT:    and a0, a0, a1
14; CHECK-NEXT:    ret
15  %vscale = call i64 @llvm.vscale.i64()
16  %shifted = lshr i64 %vscale, 3
17  %urem = urem i64 %TC, %shifted
18  ret i64 %urem
19}
20
21define i64 @vscale(i64 %TC) {
22; CHECK-LABEL: vscale:
23; CHECK:       # %bb.0:
24; CHECK-NEXT:    csrr a1, vlenb
25; CHECK-NEXT:    srli a1, a1, 3
26; CHECK-NEXT:    addi a1, a1, -1
27; CHECK-NEXT:    and a0, a0, a1
28; CHECK-NEXT:    ret
29  %vscale = call i64 @llvm.vscale.i64()
30  %urem = urem i64 %TC, %vscale
31  ret i64 %urem
32}
33
34define i64 @vscale_shl(i64 %TC) {
35; CHECK-LABEL: vscale_shl:
36; CHECK:       # %bb.0:
37; CHECK-NEXT:    csrr a1, vlenb
38; CHECK-NEXT:    addi a1, a1, -1
39; CHECK-NEXT:    and a0, a0, a1
40; CHECK-NEXT:    ret
41  %vscale = call i64 @llvm.vscale.i64()
42  %shifted = shl i64 %vscale, 3
43  %urem = urem i64 %TC, %shifted
44  ret i64 %urem
45}
46
47define i64 @TC_minus_rem(i64 %TC) {
48; CHECK-LABEL: TC_minus_rem:
49; CHECK:       # %bb.0:
50; CHECK-NEXT:    csrr a1, vlenb
51; CHECK-NEXT:    srli a1, a1, 3
52; CHECK-NEXT:    neg a1, a1
53; CHECK-NEXT:    and a0, a0, a1
54; CHECK-NEXT:    ret
55  %vscale = call i64 @llvm.vscale.i64()
56  %urem = urem i64 %TC, %vscale
57  %VTC = sub i64 %TC, %urem
58  ret i64 %VTC
59}
60
61define i64 @TC_minus_rem_shl(i64 %TC) {
62; CHECK-LABEL: TC_minus_rem_shl:
63; CHECK:       # %bb.0:
64; CHECK-NEXT:    csrr a1, vlenb
65; CHECK-NEXT:    neg a1, a1
66; CHECK-NEXT:    and a0, a0, a1
67; CHECK-NEXT:    ret
68  %vscale = call i64 @llvm.vscale.i64()
69  %shifted = shl i64 %vscale, 3
70  %urem = urem i64 %TC, %shifted
71  %VTC = sub i64 %TC, %urem
72  ret i64 %VTC
73}
74
75define i64 @con1024_minus_rem() {
76; CHECK-LABEL: con1024_minus_rem:
77; CHECK:       # %bb.0:
78; CHECK-NEXT:    csrr a0, vlenb
79; CHECK-NEXT:    srli a0, a0, 3
80; CHECK-NEXT:    negw a0, a0
81; CHECK-NEXT:    andi a0, a0, 1024
82; CHECK-NEXT:    ret
83  %vscale = call i64 @llvm.vscale.i64()
84  %urem = urem i64 1024, %vscale
85  %VTC = sub i64 1024, %urem
86  ret i64 %VTC
87}
88
89; Maximum VLEN=64k implies Maximum vscale=1024.
90; TODO: This should fold to 2048
91define i64 @con2048_minus_rem() {
92; CHECK-LABEL: con2048_minus_rem:
93; CHECK:       # %bb.0:
94; CHECK-NEXT:    csrr a0, vlenb
95; CHECK-NEXT:    li a1, 1
96; CHECK-NEXT:    srli a0, a0, 3
97; CHECK-NEXT:    neg a0, a0
98; CHECK-NEXT:    slli a1, a1, 11
99; CHECK-NEXT:    and a0, a0, a1
100; CHECK-NEXT:    ret
101  %vscale = call i64 @llvm.vscale.i64()
102  %urem = urem i64 2048, %vscale
103  %VTC = sub i64 2048, %urem
104  ret i64 %VTC
105}
106