xref: /llvm-project/llvm/test/CodeGen/RISCV/rvv/vrsub-sdnode.ll (revision 97982a8c605fac7c86d02e641a6cd7898b3ca343) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
3; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
4
5define <vscale x 1 x i8> @vrsub_vx_nxv1i8(<vscale x 1 x i8> %va, i8 signext %b) {
6; CHECK-LABEL: vrsub_vx_nxv1i8:
7; CHECK:       # %bb.0:
8; CHECK-NEXT:    vsetvli a1, zero, e8, mf8, ta, ma
9; CHECK-NEXT:    vrsub.vx v8, v8, a0
10; CHECK-NEXT:    ret
11  %head = insertelement <vscale x 1 x i8> poison, i8 %b, i32 0
12  %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer
13  %vc = sub <vscale x 1 x i8> %splat, %va
14  ret <vscale x 1 x i8> %vc
15}
16
17define <vscale x 1 x i8> @vrsub_vi_nxv1i8_0(<vscale x 1 x i8> %va) {
18; CHECK-LABEL: vrsub_vi_nxv1i8_0:
19; CHECK:       # %bb.0:
20; CHECK-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
21; CHECK-NEXT:    vrsub.vi v8, v8, -4
22; CHECK-NEXT:    ret
23  %vc = sub <vscale x 1 x i8> splat (i8 -4), %va
24  ret <vscale x 1 x i8> %vc
25}
26
27define <vscale x 2 x i8> @vrsub_vx_nxv2i8(<vscale x 2 x i8> %va, i8 signext %b) {
28; CHECK-LABEL: vrsub_vx_nxv2i8:
29; CHECK:       # %bb.0:
30; CHECK-NEXT:    vsetvli a1, zero, e8, mf4, ta, ma
31; CHECK-NEXT:    vrsub.vx v8, v8, a0
32; CHECK-NEXT:    ret
33  %head = insertelement <vscale x 2 x i8> poison, i8 %b, i32 0
34  %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> poison, <vscale x 2 x i32> zeroinitializer
35  %vc = sub <vscale x 2 x i8> %splat, %va
36  ret <vscale x 2 x i8> %vc
37}
38
39define <vscale x 2 x i8> @vrsub_vi_nxv2i8_0(<vscale x 2 x i8> %va) {
40; CHECK-LABEL: vrsub_vi_nxv2i8_0:
41; CHECK:       # %bb.0:
42; CHECK-NEXT:    vsetvli a0, zero, e8, mf4, ta, ma
43; CHECK-NEXT:    vrsub.vi v8, v8, -4
44; CHECK-NEXT:    ret
45  %vc = sub <vscale x 2 x i8> splat (i8 -4), %va
46  ret <vscale x 2 x i8> %vc
47}
48
49define <vscale x 4 x i8> @vrsub_vx_nxv4i8(<vscale x 4 x i8> %va, i8 signext %b) {
50; CHECK-LABEL: vrsub_vx_nxv4i8:
51; CHECK:       # %bb.0:
52; CHECK-NEXT:    vsetvli a1, zero, e8, mf2, ta, ma
53; CHECK-NEXT:    vrsub.vx v8, v8, a0
54; CHECK-NEXT:    ret
55  %head = insertelement <vscale x 4 x i8> poison, i8 %b, i32 0
56  %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> poison, <vscale x 4 x i32> zeroinitializer
57  %vc = sub <vscale x 4 x i8> %splat, %va
58  ret <vscale x 4 x i8> %vc
59}
60
61define <vscale x 4 x i8> @vrsub_vi_nxv4i8_0(<vscale x 4 x i8> %va) {
62; CHECK-LABEL: vrsub_vi_nxv4i8_0:
63; CHECK:       # %bb.0:
64; CHECK-NEXT:    vsetvli a0, zero, e8, mf2, ta, ma
65; CHECK-NEXT:    vrsub.vi v8, v8, -4
66; CHECK-NEXT:    ret
67  %vc = sub <vscale x 4 x i8> splat (i8 -4), %va
68  ret <vscale x 4 x i8> %vc
69}
70
71define <vscale x 8 x i8> @vrsub_vx_nxv8i8(<vscale x 8 x i8> %va, i8 signext %b) {
72; CHECK-LABEL: vrsub_vx_nxv8i8:
73; CHECK:       # %bb.0:
74; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, ma
75; CHECK-NEXT:    vrsub.vx v8, v8, a0
76; CHECK-NEXT:    ret
77  %head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0
78  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
79  %vc = sub <vscale x 8 x i8> %splat, %va
80  ret <vscale x 8 x i8> %vc
81}
82
83define <vscale x 8 x i8> @vrsub_vi_nxv8i8_0(<vscale x 8 x i8> %va) {
84; CHECK-LABEL: vrsub_vi_nxv8i8_0:
85; CHECK:       # %bb.0:
86; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, ma
87; CHECK-NEXT:    vrsub.vi v8, v8, -4
88; CHECK-NEXT:    ret
89  %vc = sub <vscale x 8 x i8> splat (i8 -4), %va
90  ret <vscale x 8 x i8> %vc
91}
92
93define <vscale x 16 x i8> @vrsub_vx_nxv16i8(<vscale x 16 x i8> %va, i8 signext %b) {
94; CHECK-LABEL: vrsub_vx_nxv16i8:
95; CHECK:       # %bb.0:
96; CHECK-NEXT:    vsetvli a1, zero, e8, m2, ta, ma
97; CHECK-NEXT:    vrsub.vx v8, v8, a0
98; CHECK-NEXT:    ret
99  %head = insertelement <vscale x 16 x i8> poison, i8 %b, i32 0
100  %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
101  %vc = sub <vscale x 16 x i8> %splat, %va
102  ret <vscale x 16 x i8> %vc
103}
104
105define <vscale x 16 x i8> @vrsub_vi_nxv16i8_0(<vscale x 16 x i8> %va) {
106; CHECK-LABEL: vrsub_vi_nxv16i8_0:
107; CHECK:       # %bb.0:
108; CHECK-NEXT:    vsetvli a0, zero, e8, m2, ta, ma
109; CHECK-NEXT:    vrsub.vi v8, v8, -4
110; CHECK-NEXT:    ret
111  %vc = sub <vscale x 16 x i8> splat (i8 -4), %va
112  ret <vscale x 16 x i8> %vc
113}
114
115define <vscale x 32 x i8> @vrsub_vx_nxv32i8(<vscale x 32 x i8> %va, i8 signext %b) {
116; CHECK-LABEL: vrsub_vx_nxv32i8:
117; CHECK:       # %bb.0:
118; CHECK-NEXT:    vsetvli a1, zero, e8, m4, ta, ma
119; CHECK-NEXT:    vrsub.vx v8, v8, a0
120; CHECK-NEXT:    ret
121  %head = insertelement <vscale x 32 x i8> poison, i8 %b, i32 0
122  %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> poison, <vscale x 32 x i32> zeroinitializer
123  %vc = sub <vscale x 32 x i8> %splat, %va
124  ret <vscale x 32 x i8> %vc
125}
126
127define <vscale x 32 x i8> @vrsub_vi_nxv32i8_0(<vscale x 32 x i8> %va) {
128; CHECK-LABEL: vrsub_vi_nxv32i8_0:
129; CHECK:       # %bb.0:
130; CHECK-NEXT:    vsetvli a0, zero, e8, m4, ta, ma
131; CHECK-NEXT:    vrsub.vi v8, v8, -4
132; CHECK-NEXT:    ret
133  %vc = sub <vscale x 32 x i8> splat (i8 -4), %va
134  ret <vscale x 32 x i8> %vc
135}
136
137define <vscale x 64 x i8> @vrsub_vx_nxv64i8(<vscale x 64 x i8> %va, i8 signext %b) {
138; CHECK-LABEL: vrsub_vx_nxv64i8:
139; CHECK:       # %bb.0:
140; CHECK-NEXT:    vsetvli a1, zero, e8, m8, ta, ma
141; CHECK-NEXT:    vrsub.vx v8, v8, a0
142; CHECK-NEXT:    ret
143  %head = insertelement <vscale x 64 x i8> poison, i8 %b, i32 0
144  %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> poison, <vscale x 64 x i32> zeroinitializer
145  %vc = sub <vscale x 64 x i8> %splat, %va
146  ret <vscale x 64 x i8> %vc
147}
148
149define <vscale x 64 x i8> @vrsub_vi_nxv64i8_0(<vscale x 64 x i8> %va) {
150; CHECK-LABEL: vrsub_vi_nxv64i8_0:
151; CHECK:       # %bb.0:
152; CHECK-NEXT:    vsetvli a0, zero, e8, m8, ta, ma
153; CHECK-NEXT:    vrsub.vi v8, v8, -4
154; CHECK-NEXT:    ret
155  %vc = sub <vscale x 64 x i8> splat (i8 -4), %va
156  ret <vscale x 64 x i8> %vc
157}
158
159define <vscale x 1 x i16> @vrsub_vx_nxv1i16(<vscale x 1 x i16> %va, i16 signext %b) {
160; CHECK-LABEL: vrsub_vx_nxv1i16:
161; CHECK:       # %bb.0:
162; CHECK-NEXT:    vsetvli a1, zero, e16, mf4, ta, ma
163; CHECK-NEXT:    vrsub.vx v8, v8, a0
164; CHECK-NEXT:    ret
165  %head = insertelement <vscale x 1 x i16> poison, i16 %b, i32 0
166  %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer
167  %vc = sub <vscale x 1 x i16> %splat, %va
168  ret <vscale x 1 x i16> %vc
169}
170
171define <vscale x 1 x i16> @vrsub_vi_nxv1i16_0(<vscale x 1 x i16> %va) {
172; CHECK-LABEL: vrsub_vi_nxv1i16_0:
173; CHECK:       # %bb.0:
174; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, ma
175; CHECK-NEXT:    vrsub.vi v8, v8, -4
176; CHECK-NEXT:    ret
177  %vc = sub <vscale x 1 x i16> splat (i16 -4), %va
178  ret <vscale x 1 x i16> %vc
179}
180
181define <vscale x 2 x i16> @vrsub_vx_nxv2i16(<vscale x 2 x i16> %va, i16 signext %b) {
182; CHECK-LABEL: vrsub_vx_nxv2i16:
183; CHECK:       # %bb.0:
184; CHECK-NEXT:    vsetvli a1, zero, e16, mf2, ta, ma
185; CHECK-NEXT:    vrsub.vx v8, v8, a0
186; CHECK-NEXT:    ret
187  %head = insertelement <vscale x 2 x i16> poison, i16 %b, i32 0
188  %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer
189  %vc = sub <vscale x 2 x i16> %splat, %va
190  ret <vscale x 2 x i16> %vc
191}
192
193define <vscale x 2 x i16> @vrsub_vi_nxv2i16_0(<vscale x 2 x i16> %va) {
194; CHECK-LABEL: vrsub_vi_nxv2i16_0:
195; CHECK:       # %bb.0:
196; CHECK-NEXT:    vsetvli a0, zero, e16, mf2, ta, ma
197; CHECK-NEXT:    vrsub.vi v8, v8, -4
198; CHECK-NEXT:    ret
199  %vc = sub <vscale x 2 x i16> splat (i16 -4), %va
200  ret <vscale x 2 x i16> %vc
201}
202
203define <vscale x 4 x i16> @vrsub_vx_nxv4i16(<vscale x 4 x i16> %va, i16 signext %b) {
204; CHECK-LABEL: vrsub_vx_nxv4i16:
205; CHECK:       # %bb.0:
206; CHECK-NEXT:    vsetvli a1, zero, e16, m1, ta, ma
207; CHECK-NEXT:    vrsub.vx v8, v8, a0
208; CHECK-NEXT:    ret
209  %head = insertelement <vscale x 4 x i16> poison, i16 %b, i32 0
210  %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> poison, <vscale x 4 x i32> zeroinitializer
211  %vc = sub <vscale x 4 x i16> %splat, %va
212  ret <vscale x 4 x i16> %vc
213}
214
215define <vscale x 4 x i16> @vrsub_vi_nxv4i16_0(<vscale x 4 x i16> %va) {
216; CHECK-LABEL: vrsub_vi_nxv4i16_0:
217; CHECK:       # %bb.0:
218; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, ma
219; CHECK-NEXT:    vrsub.vi v8, v8, -4
220; CHECK-NEXT:    ret
221  %vc = sub <vscale x 4 x i16> splat (i16 -4), %va
222  ret <vscale x 4 x i16> %vc
223}
224
225define <vscale x 8 x i16> @vrsub_vx_nxv8i16(<vscale x 8 x i16> %va, i16 signext %b) {
226; CHECK-LABEL: vrsub_vx_nxv8i16:
227; CHECK:       # %bb.0:
228; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, ma
229; CHECK-NEXT:    vrsub.vx v8, v8, a0
230; CHECK-NEXT:    ret
231  %head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0
232  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
233  %vc = sub <vscale x 8 x i16> %splat, %va
234  ret <vscale x 8 x i16> %vc
235}
236
237define <vscale x 8 x i16> @vrsub_vi_nxv8i16_0(<vscale x 8 x i16> %va) {
238; CHECK-LABEL: vrsub_vi_nxv8i16_0:
239; CHECK:       # %bb.0:
240; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, ma
241; CHECK-NEXT:    vrsub.vi v8, v8, -4
242; CHECK-NEXT:    ret
243  %vc = sub <vscale x 8 x i16> splat (i16 -4), %va
244  ret <vscale x 8 x i16> %vc
245}
246
247define <vscale x 16 x i16> @vrsub_vx_nxv16i16(<vscale x 16 x i16> %va, i16 signext %b) {
248; CHECK-LABEL: vrsub_vx_nxv16i16:
249; CHECK:       # %bb.0:
250; CHECK-NEXT:    vsetvli a1, zero, e16, m4, ta, ma
251; CHECK-NEXT:    vrsub.vx v8, v8, a0
252; CHECK-NEXT:    ret
253  %head = insertelement <vscale x 16 x i16> poison, i16 %b, i32 0
254  %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> poison, <vscale x 16 x i32> zeroinitializer
255  %vc = sub <vscale x 16 x i16> %splat, %va
256  ret <vscale x 16 x i16> %vc
257}
258
259define <vscale x 16 x i16> @vrsub_vi_nxv16i16_0(<vscale x 16 x i16> %va) {
260; CHECK-LABEL: vrsub_vi_nxv16i16_0:
261; CHECK:       # %bb.0:
262; CHECK-NEXT:    vsetvli a0, zero, e16, m4, ta, ma
263; CHECK-NEXT:    vrsub.vi v8, v8, -4
264; CHECK-NEXT:    ret
265  %vc = sub <vscale x 16 x i16> splat (i16 -4), %va
266  ret <vscale x 16 x i16> %vc
267}
268
269define <vscale x 32 x i16> @vrsub_vx_nxv32i16(<vscale x 32 x i16> %va, i16 signext %b) {
270; CHECK-LABEL: vrsub_vx_nxv32i16:
271; CHECK:       # %bb.0:
272; CHECK-NEXT:    vsetvli a1, zero, e16, m8, ta, ma
273; CHECK-NEXT:    vrsub.vx v8, v8, a0
274; CHECK-NEXT:    ret
275  %head = insertelement <vscale x 32 x i16> poison, i16 %b, i32 0
276  %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> poison, <vscale x 32 x i32> zeroinitializer
277  %vc = sub <vscale x 32 x i16> %splat, %va
278  ret <vscale x 32 x i16> %vc
279}
280
281define <vscale x 32 x i16> @vrsub_vi_nxv32i16_0(<vscale x 32 x i16> %va) {
282; CHECK-LABEL: vrsub_vi_nxv32i16_0:
283; CHECK:       # %bb.0:
284; CHECK-NEXT:    vsetvli a0, zero, e16, m8, ta, ma
285; CHECK-NEXT:    vrsub.vi v8, v8, -4
286; CHECK-NEXT:    ret
287  %vc = sub <vscale x 32 x i16> splat (i16 -4), %va
288  ret <vscale x 32 x i16> %vc
289}
290
291define <vscale x 1 x i32> @vrsub_vx_nxv1i32(<vscale x 1 x i32> %va, i32 signext %b) {
292; CHECK-LABEL: vrsub_vx_nxv1i32:
293; CHECK:       # %bb.0:
294; CHECK-NEXT:    vsetvli a1, zero, e32, mf2, ta, ma
295; CHECK-NEXT:    vrsub.vx v8, v8, a0
296; CHECK-NEXT:    ret
297  %head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 0
298  %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer
299  %vc = sub <vscale x 1 x i32> %splat, %va
300  ret <vscale x 1 x i32> %vc
301}
302
303define <vscale x 1 x i32> @vrsub_vi_nxv1i32_0(<vscale x 1 x i32> %va) {
304; CHECK-LABEL: vrsub_vi_nxv1i32_0:
305; CHECK:       # %bb.0:
306; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, ma
307; CHECK-NEXT:    vrsub.vi v8, v8, -4
308; CHECK-NEXT:    ret
309  %vc = sub <vscale x 1 x i32> splat (i32 -4), %va
310  ret <vscale x 1 x i32> %vc
311}
312
313define <vscale x 2 x i32> @vrsub_vx_nxv2i32(<vscale x 2 x i32> %va, i32 signext %b) {
314; CHECK-LABEL: vrsub_vx_nxv2i32:
315; CHECK:       # %bb.0:
316; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, ma
317; CHECK-NEXT:    vrsub.vx v8, v8, a0
318; CHECK-NEXT:    ret
319  %head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0
320  %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer
321  %vc = sub <vscale x 2 x i32> %splat, %va
322  ret <vscale x 2 x i32> %vc
323}
324
325define <vscale x 2 x i32> @vrsub_vi_nxv2i32_0(<vscale x 2 x i32> %va) {
326; CHECK-LABEL: vrsub_vi_nxv2i32_0:
327; CHECK:       # %bb.0:
328; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, ma
329; CHECK-NEXT:    vrsub.vi v8, v8, -4
330; CHECK-NEXT:    ret
331  %vc = sub <vscale x 2 x i32> splat (i32 -4), %va
332  ret <vscale x 2 x i32> %vc
333}
334
335define <vscale x 4 x i32> @vrsub_vx_nxv4i32(<vscale x 4 x i32> %va, i32 signext %b) {
336; CHECK-LABEL: vrsub_vx_nxv4i32:
337; CHECK:       # %bb.0:
338; CHECK-NEXT:    vsetvli a1, zero, e32, m2, ta, ma
339; CHECK-NEXT:    vrsub.vx v8, v8, a0
340; CHECK-NEXT:    ret
341  %head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0
342  %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
343  %vc = sub <vscale x 4 x i32> %splat, %va
344  ret <vscale x 4 x i32> %vc
345}
346
347define <vscale x 4 x i32> @vrsub_vi_nxv4i32_0(<vscale x 4 x i32> %va) {
348; CHECK-LABEL: vrsub_vi_nxv4i32_0:
349; CHECK:       # %bb.0:
350; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, ma
351; CHECK-NEXT:    vrsub.vi v8, v8, -4
352; CHECK-NEXT:    ret
353  %vc = sub <vscale x 4 x i32> splat (i32 -4), %va
354  ret <vscale x 4 x i32> %vc
355}
356
357define <vscale x 8 x i32> @vrsub_vx_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b) {
358; CHECK-LABEL: vrsub_vx_nxv8i32:
359; CHECK:       # %bb.0:
360; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, ma
361; CHECK-NEXT:    vrsub.vx v8, v8, a0
362; CHECK-NEXT:    ret
363  %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
364  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
365  %vc = sub <vscale x 8 x i32> %splat, %va
366  ret <vscale x 8 x i32> %vc
367}
368
369define <vscale x 8 x i32> @vrsub_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
370; CHECK-LABEL: vrsub_vi_nxv8i32_0:
371; CHECK:       # %bb.0:
372; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, ma
373; CHECK-NEXT:    vrsub.vi v8, v8, -4
374; CHECK-NEXT:    ret
375  %vc = sub <vscale x 8 x i32> splat (i32 -4), %va
376  ret <vscale x 8 x i32> %vc
377}
378
379define <vscale x 16 x i32> @vrsub_vx_nxv16i32(<vscale x 16 x i32> %va, i32 signext %b) {
380; CHECK-LABEL: vrsub_vx_nxv16i32:
381; CHECK:       # %bb.0:
382; CHECK-NEXT:    vsetvli a1, zero, e32, m8, ta, ma
383; CHECK-NEXT:    vrsub.vx v8, v8, a0
384; CHECK-NEXT:    ret
385  %head = insertelement <vscale x 16 x i32> poison, i32 %b, i32 0
386  %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> poison, <vscale x 16 x i32> zeroinitializer
387  %vc = sub <vscale x 16 x i32> %splat, %va
388  ret <vscale x 16 x i32> %vc
389}
390
391define <vscale x 16 x i32> @vrsub_vi_nxv16i32_0(<vscale x 16 x i32> %va) {
392; CHECK-LABEL: vrsub_vi_nxv16i32_0:
393; CHECK:       # %bb.0:
394; CHECK-NEXT:    vsetvli a0, zero, e32, m8, ta, ma
395; CHECK-NEXT:    vrsub.vi v8, v8, -4
396; CHECK-NEXT:    ret
397  %vc = sub <vscale x 16 x i32> splat (i32 -4), %va
398  ret <vscale x 16 x i32> %vc
399}
400
401define <vscale x 1 x i64> @vrsub_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b) {
402; RV32-LABEL: vrsub_vx_nxv1i64:
403; RV32:       # %bb.0:
404; RV32-NEXT:    addi sp, sp, -16
405; RV32-NEXT:    .cfi_def_cfa_offset 16
406; RV32-NEXT:    sw a0, 8(sp)
407; RV32-NEXT:    sw a1, 12(sp)
408; RV32-NEXT:    addi a0, sp, 8
409; RV32-NEXT:    vsetvli a1, zero, e64, m1, ta, ma
410; RV32-NEXT:    vlse64.v v9, (a0), zero
411; RV32-NEXT:    vsub.vv v8, v9, v8
412; RV32-NEXT:    addi sp, sp, 16
413; RV32-NEXT:    .cfi_def_cfa_offset 0
414; RV32-NEXT:    ret
415;
416; RV64-LABEL: vrsub_vx_nxv1i64:
417; RV64:       # %bb.0:
418; RV64-NEXT:    vsetvli a1, zero, e64, m1, ta, ma
419; RV64-NEXT:    vrsub.vx v8, v8, a0
420; RV64-NEXT:    ret
421  %head = insertelement <vscale x 1 x i64> poison, i64 %b, i32 0
422  %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer
423  %vc = sub <vscale x 1 x i64> %splat, %va
424  ret <vscale x 1 x i64> %vc
425}
426
427define <vscale x 1 x i64> @vrsub_vi_nxv1i64_0(<vscale x 1 x i64> %va) {
428; CHECK-LABEL: vrsub_vi_nxv1i64_0:
429; CHECK:       # %bb.0:
430; CHECK-NEXT:    vsetvli a0, zero, e64, m1, ta, ma
431; CHECK-NEXT:    vrsub.vi v8, v8, -4
432; CHECK-NEXT:    ret
433  %vc = sub <vscale x 1 x i64> splat (i64 -4), %va
434  ret <vscale x 1 x i64> %vc
435}
436
437define <vscale x 2 x i64> @vrsub_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b) {
438; RV32-LABEL: vrsub_vx_nxv2i64:
439; RV32:       # %bb.0:
440; RV32-NEXT:    addi sp, sp, -16
441; RV32-NEXT:    .cfi_def_cfa_offset 16
442; RV32-NEXT:    sw a0, 8(sp)
443; RV32-NEXT:    sw a1, 12(sp)
444; RV32-NEXT:    addi a0, sp, 8
445; RV32-NEXT:    vsetvli a1, zero, e64, m2, ta, ma
446; RV32-NEXT:    vlse64.v v10, (a0), zero
447; RV32-NEXT:    vsub.vv v8, v10, v8
448; RV32-NEXT:    addi sp, sp, 16
449; RV32-NEXT:    .cfi_def_cfa_offset 0
450; RV32-NEXT:    ret
451;
452; RV64-LABEL: vrsub_vx_nxv2i64:
453; RV64:       # %bb.0:
454; RV64-NEXT:    vsetvli a1, zero, e64, m2, ta, ma
455; RV64-NEXT:    vrsub.vx v8, v8, a0
456; RV64-NEXT:    ret
457  %head = insertelement <vscale x 2 x i64> poison, i64 %b, i32 0
458  %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
459  %vc = sub <vscale x 2 x i64> %splat, %va
460  ret <vscale x 2 x i64> %vc
461}
462
463define <vscale x 2 x i64> @vrsub_vi_nxv2i64_0(<vscale x 2 x i64> %va) {
464; CHECK-LABEL: vrsub_vi_nxv2i64_0:
465; CHECK:       # %bb.0:
466; CHECK-NEXT:    vsetvli a0, zero, e64, m2, ta, ma
467; CHECK-NEXT:    vrsub.vi v8, v8, -4
468; CHECK-NEXT:    ret
469  %vc = sub <vscale x 2 x i64> splat (i64 -4), %va
470  ret <vscale x 2 x i64> %vc
471}
472
473define <vscale x 4 x i64> @vrsub_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b) {
474; RV32-LABEL: vrsub_vx_nxv4i64:
475; RV32:       # %bb.0:
476; RV32-NEXT:    addi sp, sp, -16
477; RV32-NEXT:    .cfi_def_cfa_offset 16
478; RV32-NEXT:    sw a0, 8(sp)
479; RV32-NEXT:    sw a1, 12(sp)
480; RV32-NEXT:    addi a0, sp, 8
481; RV32-NEXT:    vsetvli a1, zero, e64, m4, ta, ma
482; RV32-NEXT:    vlse64.v v12, (a0), zero
483; RV32-NEXT:    vsub.vv v8, v12, v8
484; RV32-NEXT:    addi sp, sp, 16
485; RV32-NEXT:    .cfi_def_cfa_offset 0
486; RV32-NEXT:    ret
487;
488; RV64-LABEL: vrsub_vx_nxv4i64:
489; RV64:       # %bb.0:
490; RV64-NEXT:    vsetvli a1, zero, e64, m4, ta, ma
491; RV64-NEXT:    vrsub.vx v8, v8, a0
492; RV64-NEXT:    ret
493  %head = insertelement <vscale x 4 x i64> poison, i64 %b, i32 0
494  %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer
495  %vc = sub <vscale x 4 x i64> %splat, %va
496  ret <vscale x 4 x i64> %vc
497}
498
499define <vscale x 4 x i64> @vrsub_vi_nxv4i64_0(<vscale x 4 x i64> %va) {
500; CHECK-LABEL: vrsub_vi_nxv4i64_0:
501; CHECK:       # %bb.0:
502; CHECK-NEXT:    vsetvli a0, zero, e64, m4, ta, ma
503; CHECK-NEXT:    vrsub.vi v8, v8, -4
504; CHECK-NEXT:    ret
505  %vc = sub <vscale x 4 x i64> splat (i64 -4), %va
506  ret <vscale x 4 x i64> %vc
507}
508
509define <vscale x 8 x i64> @vrsub_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
510; RV32-LABEL: vrsub_vx_nxv8i64:
511; RV32:       # %bb.0:
512; RV32-NEXT:    addi sp, sp, -16
513; RV32-NEXT:    .cfi_def_cfa_offset 16
514; RV32-NEXT:    sw a0, 8(sp)
515; RV32-NEXT:    sw a1, 12(sp)
516; RV32-NEXT:    addi a0, sp, 8
517; RV32-NEXT:    vsetvli a1, zero, e64, m8, ta, ma
518; RV32-NEXT:    vlse64.v v16, (a0), zero
519; RV32-NEXT:    vsub.vv v8, v16, v8
520; RV32-NEXT:    addi sp, sp, 16
521; RV32-NEXT:    .cfi_def_cfa_offset 0
522; RV32-NEXT:    ret
523;
524; RV64-LABEL: vrsub_vx_nxv8i64:
525; RV64:       # %bb.0:
526; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, ma
527; RV64-NEXT:    vrsub.vx v8, v8, a0
528; RV64-NEXT:    ret
529  %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
530  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
531  %vc = sub <vscale x 8 x i64> %splat, %va
532  ret <vscale x 8 x i64> %vc
533}
534
535define <vscale x 8 x i64> @vrsub_vi_nxv8i64_0(<vscale x 8 x i64> %va) {
536; CHECK-LABEL: vrsub_vi_nxv8i64_0:
537; CHECK:       # %bb.0:
538; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, ma
539; CHECK-NEXT:    vrsub.vi v8, v8, -4
540; CHECK-NEXT:    ret
541  %vc = sub <vscale x 8 x i64> splat (i64 -4), %va
542  ret <vscale x 8 x i64> %vc
543}
544