xref: /llvm-project/llvm/test/CodeGen/RISCV/rvv/vrol-sdnode.ll (revision 9122c5235ec85ce0c0ad337e862b006e7b349d84) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-RV32
3; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-RV64
4; RUN: llc -mtriple=riscv32 -mattr=+v,+zvkb -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK-ZVKB
5; RUN: llc -mtriple=riscv64 -mattr=+v,+zvkb -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK-ZVKB
6
7declare <vscale x 1 x i8> @llvm.fshl.nxv1i8(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>)
8
9define <vscale x 1 x i8> @vrol_vv_nxv1i8(<vscale x 1 x i8> %a, <vscale x 1 x i8> %b) {
10; CHECK-LABEL: vrol_vv_nxv1i8:
11; CHECK:       # %bb.0:
12; CHECK-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
13; CHECK-NEXT:    vand.vi v10, v9, 7
14; CHECK-NEXT:    vrsub.vi v9, v9, 0
15; CHECK-NEXT:    vsll.vv v10, v8, v10
16; CHECK-NEXT:    vand.vi v9, v9, 7
17; CHECK-NEXT:    vsrl.vv v8, v8, v9
18; CHECK-NEXT:    vor.vv v8, v10, v8
19; CHECK-NEXT:    ret
20;
21; CHECK-ZVKB-LABEL: vrol_vv_nxv1i8:
22; CHECK-ZVKB:       # %bb.0:
23; CHECK-ZVKB-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
24; CHECK-ZVKB-NEXT:    vrol.vv v8, v8, v9
25; CHECK-ZVKB-NEXT:    ret
26  %x = call <vscale x 1 x i8> @llvm.fshl.nxv1i8(<vscale x 1 x i8> %a, <vscale x 1 x i8> %a, <vscale x 1 x i8> %b)
27  ret <vscale x 1 x i8> %x
28}
29
30define <vscale x 1 x i8> @vrol_vx_nxv1i8(<vscale x 1 x i8> %a, i8 %b) {
31; CHECK-LABEL: vrol_vx_nxv1i8:
32; CHECK:       # %bb.0:
33; CHECK-NEXT:    vsetvli a1, zero, e8, mf8, ta, ma
34; CHECK-NEXT:    vmv.v.x v9, a0
35; CHECK-NEXT:    vand.vi v10, v9, 7
36; CHECK-NEXT:    vrsub.vi v9, v9, 0
37; CHECK-NEXT:    vsll.vv v10, v8, v10
38; CHECK-NEXT:    vand.vi v9, v9, 7
39; CHECK-NEXT:    vsrl.vv v8, v8, v9
40; CHECK-NEXT:    vor.vv v8, v10, v8
41; CHECK-NEXT:    ret
42;
43; CHECK-ZVKB-LABEL: vrol_vx_nxv1i8:
44; CHECK-ZVKB:       # %bb.0:
45; CHECK-ZVKB-NEXT:    vsetvli a1, zero, e8, mf8, ta, ma
46; CHECK-ZVKB-NEXT:    vrol.vx v8, v8, a0
47; CHECK-ZVKB-NEXT:    ret
48  %b.head = insertelement <vscale x 1 x i8> poison, i8 %b, i32 0
49  %b.splat = shufflevector <vscale x 1 x i8> %b.head, <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer
50  %x = call <vscale x 1 x i8> @llvm.fshl.nxv1i8(<vscale x 1 x i8> %a, <vscale x 1 x i8> %a, <vscale x 1 x i8> %b.splat)
51  ret <vscale x 1 x i8> %x
52}
53
54declare <vscale x 2 x i8> @llvm.fshl.nxv2i8(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>)
55
56define <vscale x 2 x i8> @vrol_vv_nxv2i8(<vscale x 2 x i8> %a, <vscale x 2 x i8> %b) {
57; CHECK-LABEL: vrol_vv_nxv2i8:
58; CHECK:       # %bb.0:
59; CHECK-NEXT:    vsetvli a0, zero, e8, mf4, ta, ma
60; CHECK-NEXT:    vand.vi v10, v9, 7
61; CHECK-NEXT:    vrsub.vi v9, v9, 0
62; CHECK-NEXT:    vsll.vv v10, v8, v10
63; CHECK-NEXT:    vand.vi v9, v9, 7
64; CHECK-NEXT:    vsrl.vv v8, v8, v9
65; CHECK-NEXT:    vor.vv v8, v10, v8
66; CHECK-NEXT:    ret
67;
68; CHECK-ZVKB-LABEL: vrol_vv_nxv2i8:
69; CHECK-ZVKB:       # %bb.0:
70; CHECK-ZVKB-NEXT:    vsetvli a0, zero, e8, mf4, ta, ma
71; CHECK-ZVKB-NEXT:    vrol.vv v8, v8, v9
72; CHECK-ZVKB-NEXT:    ret
73  %x = call <vscale x 2 x i8> @llvm.fshl.nxv2i8(<vscale x 2 x i8> %a, <vscale x 2 x i8> %a, <vscale x 2 x i8> %b)
74  ret <vscale x 2 x i8> %x
75}
76
77define <vscale x 2 x i8> @vrol_vx_nxv2i8(<vscale x 2 x i8> %a, i8 %b) {
78; CHECK-LABEL: vrol_vx_nxv2i8:
79; CHECK:       # %bb.0:
80; CHECK-NEXT:    vsetvli a1, zero, e8, mf4, ta, ma
81; CHECK-NEXT:    vmv.v.x v9, a0
82; CHECK-NEXT:    vand.vi v10, v9, 7
83; CHECK-NEXT:    vrsub.vi v9, v9, 0
84; CHECK-NEXT:    vsll.vv v10, v8, v10
85; CHECK-NEXT:    vand.vi v9, v9, 7
86; CHECK-NEXT:    vsrl.vv v8, v8, v9
87; CHECK-NEXT:    vor.vv v8, v10, v8
88; CHECK-NEXT:    ret
89;
90; CHECK-ZVKB-LABEL: vrol_vx_nxv2i8:
91; CHECK-ZVKB:       # %bb.0:
92; CHECK-ZVKB-NEXT:    vsetvli a1, zero, e8, mf4, ta, ma
93; CHECK-ZVKB-NEXT:    vrol.vx v8, v8, a0
94; CHECK-ZVKB-NEXT:    ret
95  %b.head = insertelement <vscale x 2 x i8> poison, i8 %b, i32 0
96  %b.splat = shufflevector <vscale x 2 x i8> %b.head, <vscale x 2 x i8> poison, <vscale x 2 x i32> zeroinitializer
97  %x = call <vscale x 2 x i8> @llvm.fshl.nxv2i8(<vscale x 2 x i8> %a, <vscale x 2 x i8> %a, <vscale x 2 x i8> %b.splat)
98  ret <vscale x 2 x i8> %x
99}
100
101declare <vscale x 4 x i8> @llvm.fshl.nxv4i8(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>)
102
103define <vscale x 4 x i8> @vrol_vv_nxv4i8(<vscale x 4 x i8> %a, <vscale x 4 x i8> %b) {
104; CHECK-LABEL: vrol_vv_nxv4i8:
105; CHECK:       # %bb.0:
106; CHECK-NEXT:    vsetvli a0, zero, e8, mf2, ta, ma
107; CHECK-NEXT:    vand.vi v10, v9, 7
108; CHECK-NEXT:    vrsub.vi v9, v9, 0
109; CHECK-NEXT:    vsll.vv v10, v8, v10
110; CHECK-NEXT:    vand.vi v9, v9, 7
111; CHECK-NEXT:    vsrl.vv v8, v8, v9
112; CHECK-NEXT:    vor.vv v8, v10, v8
113; CHECK-NEXT:    ret
114;
115; CHECK-ZVKB-LABEL: vrol_vv_nxv4i8:
116; CHECK-ZVKB:       # %bb.0:
117; CHECK-ZVKB-NEXT:    vsetvli a0, zero, e8, mf2, ta, ma
118; CHECK-ZVKB-NEXT:    vrol.vv v8, v8, v9
119; CHECK-ZVKB-NEXT:    ret
120  %x = call <vscale x 4 x i8> @llvm.fshl.nxv4i8(<vscale x 4 x i8> %a, <vscale x 4 x i8> %a, <vscale x 4 x i8> %b)
121  ret <vscale x 4 x i8> %x
122}
123
124define <vscale x 4 x i8> @vrol_vx_nxv4i8(<vscale x 4 x i8> %a, i8 %b) {
125; CHECK-LABEL: vrol_vx_nxv4i8:
126; CHECK:       # %bb.0:
127; CHECK-NEXT:    vsetvli a1, zero, e8, mf2, ta, ma
128; CHECK-NEXT:    vmv.v.x v9, a0
129; CHECK-NEXT:    vand.vi v10, v9, 7
130; CHECK-NEXT:    vrsub.vi v9, v9, 0
131; CHECK-NEXT:    vsll.vv v10, v8, v10
132; CHECK-NEXT:    vand.vi v9, v9, 7
133; CHECK-NEXT:    vsrl.vv v8, v8, v9
134; CHECK-NEXT:    vor.vv v8, v10, v8
135; CHECK-NEXT:    ret
136;
137; CHECK-ZVKB-LABEL: vrol_vx_nxv4i8:
138; CHECK-ZVKB:       # %bb.0:
139; CHECK-ZVKB-NEXT:    vsetvli a1, zero, e8, mf2, ta, ma
140; CHECK-ZVKB-NEXT:    vrol.vx v8, v8, a0
141; CHECK-ZVKB-NEXT:    ret
142  %b.head = insertelement <vscale x 4 x i8> poison, i8 %b, i32 0
143  %b.splat = shufflevector <vscale x 4 x i8> %b.head, <vscale x 4 x i8> poison, <vscale x 4 x i32> zeroinitializer
144  %x = call <vscale x 4 x i8> @llvm.fshl.nxv4i8(<vscale x 4 x i8> %a, <vscale x 4 x i8> %a, <vscale x 4 x i8> %b.splat)
145  ret <vscale x 4 x i8> %x
146}
147
148declare <vscale x 8 x i8> @llvm.fshl.nxv8i8(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>)
149
150define <vscale x 8 x i8> @vrol_vv_nxv8i8(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b) {
151; CHECK-LABEL: vrol_vv_nxv8i8:
152; CHECK:       # %bb.0:
153; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, ma
154; CHECK-NEXT:    vand.vi v10, v9, 7
155; CHECK-NEXT:    vrsub.vi v9, v9, 0
156; CHECK-NEXT:    vsll.vv v10, v8, v10
157; CHECK-NEXT:    vand.vi v9, v9, 7
158; CHECK-NEXT:    vsrl.vv v8, v8, v9
159; CHECK-NEXT:    vor.vv v8, v10, v8
160; CHECK-NEXT:    ret
161;
162; CHECK-ZVKB-LABEL: vrol_vv_nxv8i8:
163; CHECK-ZVKB:       # %bb.0:
164; CHECK-ZVKB-NEXT:    vsetvli a0, zero, e8, m1, ta, ma
165; CHECK-ZVKB-NEXT:    vrol.vv v8, v8, v9
166; CHECK-ZVKB-NEXT:    ret
167  %x = call <vscale x 8 x i8> @llvm.fshl.nxv8i8(<vscale x 8 x i8> %a, <vscale x 8 x i8> %a, <vscale x 8 x i8> %b)
168  ret <vscale x 8 x i8> %x
169}
170
171define <vscale x 8 x i8> @vrol_vx_nxv8i8(<vscale x 8 x i8> %a, i8 %b) {
172; CHECK-LABEL: vrol_vx_nxv8i8:
173; CHECK:       # %bb.0:
174; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, ma
175; CHECK-NEXT:    vmv.v.x v9, a0
176; CHECK-NEXT:    vand.vi v10, v9, 7
177; CHECK-NEXT:    vrsub.vi v9, v9, 0
178; CHECK-NEXT:    vsll.vv v10, v8, v10
179; CHECK-NEXT:    vand.vi v9, v9, 7
180; CHECK-NEXT:    vsrl.vv v8, v8, v9
181; CHECK-NEXT:    vor.vv v8, v10, v8
182; CHECK-NEXT:    ret
183;
184; CHECK-ZVKB-LABEL: vrol_vx_nxv8i8:
185; CHECK-ZVKB:       # %bb.0:
186; CHECK-ZVKB-NEXT:    vsetvli a1, zero, e8, m1, ta, ma
187; CHECK-ZVKB-NEXT:    vrol.vx v8, v8, a0
188; CHECK-ZVKB-NEXT:    ret
189  %b.head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0
190  %b.splat = shufflevector <vscale x 8 x i8> %b.head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
191  %x = call <vscale x 8 x i8> @llvm.fshl.nxv8i8(<vscale x 8 x i8> %a, <vscale x 8 x i8> %a, <vscale x 8 x i8> %b.splat)
192  ret <vscale x 8 x i8> %x
193}
194
195declare <vscale x 16 x i8> @llvm.fshl.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>)
196
197define <vscale x 16 x i8> @vrol_vv_nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
198; CHECK-LABEL: vrol_vv_nxv16i8:
199; CHECK:       # %bb.0:
200; CHECK-NEXT:    vsetvli a0, zero, e8, m2, ta, ma
201; CHECK-NEXT:    vand.vi v12, v10, 7
202; CHECK-NEXT:    vrsub.vi v10, v10, 0
203; CHECK-NEXT:    vsll.vv v12, v8, v12
204; CHECK-NEXT:    vand.vi v10, v10, 7
205; CHECK-NEXT:    vsrl.vv v8, v8, v10
206; CHECK-NEXT:    vor.vv v8, v12, v8
207; CHECK-NEXT:    ret
208;
209; CHECK-ZVKB-LABEL: vrol_vv_nxv16i8:
210; CHECK-ZVKB:       # %bb.0:
211; CHECK-ZVKB-NEXT:    vsetvli a0, zero, e8, m2, ta, ma
212; CHECK-ZVKB-NEXT:    vrol.vv v8, v8, v10
213; CHECK-ZVKB-NEXT:    ret
214  %x = call <vscale x 16 x i8> @llvm.fshl.nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b)
215  ret <vscale x 16 x i8> %x
216}
217
218define <vscale x 16 x i8> @vrol_vx_nxv16i8(<vscale x 16 x i8> %a, i8 %b) {
219; CHECK-LABEL: vrol_vx_nxv16i8:
220; CHECK:       # %bb.0:
221; CHECK-NEXT:    vsetvli a1, zero, e8, m2, ta, ma
222; CHECK-NEXT:    vmv.v.x v10, a0
223; CHECK-NEXT:    vand.vi v12, v10, 7
224; CHECK-NEXT:    vrsub.vi v10, v10, 0
225; CHECK-NEXT:    vsll.vv v12, v8, v12
226; CHECK-NEXT:    vand.vi v10, v10, 7
227; CHECK-NEXT:    vsrl.vv v8, v8, v10
228; CHECK-NEXT:    vor.vv v8, v12, v8
229; CHECK-NEXT:    ret
230;
231; CHECK-ZVKB-LABEL: vrol_vx_nxv16i8:
232; CHECK-ZVKB:       # %bb.0:
233; CHECK-ZVKB-NEXT:    vsetvli a1, zero, e8, m2, ta, ma
234; CHECK-ZVKB-NEXT:    vrol.vx v8, v8, a0
235; CHECK-ZVKB-NEXT:    ret
236  %b.head = insertelement <vscale x 16 x i8> poison, i8 %b, i32 0
237  %b.splat = shufflevector <vscale x 16 x i8> %b.head, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
238  %x = call <vscale x 16 x i8> @llvm.fshl.nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b.splat)
239  ret <vscale x 16 x i8> %x
240}
241
242declare <vscale x 32 x i8> @llvm.fshl.nxv32i8(<vscale x 32 x i8>, <vscale x 32 x i8>, <vscale x 32 x i8>)
243
244define <vscale x 32 x i8> @vrol_vv_nxv32i8(<vscale x 32 x i8> %a, <vscale x 32 x i8> %b) {
245; CHECK-LABEL: vrol_vv_nxv32i8:
246; CHECK:       # %bb.0:
247; CHECK-NEXT:    vsetvli a0, zero, e8, m4, ta, ma
248; CHECK-NEXT:    vand.vi v16, v12, 7
249; CHECK-NEXT:    vrsub.vi v12, v12, 0
250; CHECK-NEXT:    vsll.vv v16, v8, v16
251; CHECK-NEXT:    vand.vi v12, v12, 7
252; CHECK-NEXT:    vsrl.vv v8, v8, v12
253; CHECK-NEXT:    vor.vv v8, v16, v8
254; CHECK-NEXT:    ret
255;
256; CHECK-ZVKB-LABEL: vrol_vv_nxv32i8:
257; CHECK-ZVKB:       # %bb.0:
258; CHECK-ZVKB-NEXT:    vsetvli a0, zero, e8, m4, ta, ma
259; CHECK-ZVKB-NEXT:    vrol.vv v8, v8, v12
260; CHECK-ZVKB-NEXT:    ret
261  %x = call <vscale x 32 x i8> @llvm.fshl.nxv32i8(<vscale x 32 x i8> %a, <vscale x 32 x i8> %a, <vscale x 32 x i8> %b)
262  ret <vscale x 32 x i8> %x
263}
264
265define <vscale x 32 x i8> @vrol_vx_nxv32i8(<vscale x 32 x i8> %a, i8 %b) {
266; CHECK-LABEL: vrol_vx_nxv32i8:
267; CHECK:       # %bb.0:
268; CHECK-NEXT:    vsetvli a1, zero, e8, m4, ta, ma
269; CHECK-NEXT:    vmv.v.x v12, a0
270; CHECK-NEXT:    vand.vi v16, v12, 7
271; CHECK-NEXT:    vrsub.vi v12, v12, 0
272; CHECK-NEXT:    vsll.vv v16, v8, v16
273; CHECK-NEXT:    vand.vi v12, v12, 7
274; CHECK-NEXT:    vsrl.vv v8, v8, v12
275; CHECK-NEXT:    vor.vv v8, v16, v8
276; CHECK-NEXT:    ret
277;
278; CHECK-ZVKB-LABEL: vrol_vx_nxv32i8:
279; CHECK-ZVKB:       # %bb.0:
280; CHECK-ZVKB-NEXT:    vsetvli a1, zero, e8, m4, ta, ma
281; CHECK-ZVKB-NEXT:    vrol.vx v8, v8, a0
282; CHECK-ZVKB-NEXT:    ret
283  %b.head = insertelement <vscale x 32 x i8> poison, i8 %b, i32 0
284  %b.splat = shufflevector <vscale x 32 x i8> %b.head, <vscale x 32 x i8> poison, <vscale x 32 x i32> zeroinitializer
285  %x = call <vscale x 32 x i8> @llvm.fshl.nxv32i8(<vscale x 32 x i8> %a, <vscale x 32 x i8> %a, <vscale x 32 x i8> %b.splat)
286  ret <vscale x 32 x i8> %x
287}
288
289declare <vscale x 64 x i8> @llvm.fshl.nxv64i8(<vscale x 64 x i8>, <vscale x 64 x i8>, <vscale x 64 x i8>)
290
291define <vscale x 64 x i8> @vrol_vv_nxv64i8(<vscale x 64 x i8> %a, <vscale x 64 x i8> %b) {
292; CHECK-LABEL: vrol_vv_nxv64i8:
293; CHECK:       # %bb.0:
294; CHECK-NEXT:    vsetvli a0, zero, e8, m8, ta, ma
295; CHECK-NEXT:    vand.vi v24, v16, 7
296; CHECK-NEXT:    vrsub.vi v16, v16, 0
297; CHECK-NEXT:    vsll.vv v24, v8, v24
298; CHECK-NEXT:    vand.vi v16, v16, 7
299; CHECK-NEXT:    vsrl.vv v8, v8, v16
300; CHECK-NEXT:    vor.vv v8, v24, v8
301; CHECK-NEXT:    ret
302;
303; CHECK-ZVKB-LABEL: vrol_vv_nxv64i8:
304; CHECK-ZVKB:       # %bb.0:
305; CHECK-ZVKB-NEXT:    vsetvli a0, zero, e8, m8, ta, ma
306; CHECK-ZVKB-NEXT:    vrol.vv v8, v8, v16
307; CHECK-ZVKB-NEXT:    ret
308  %x = call <vscale x 64 x i8> @llvm.fshl.nxv64i8(<vscale x 64 x i8> %a, <vscale x 64 x i8> %a, <vscale x 64 x i8> %b)
309  ret <vscale x 64 x i8> %x
310}
311
312define <vscale x 64 x i8> @vrol_vx_nxv64i8(<vscale x 64 x i8> %a, i8 %b) {
313; CHECK-LABEL: vrol_vx_nxv64i8:
314; CHECK:       # %bb.0:
315; CHECK-NEXT:    vsetvli a1, zero, e8, m8, ta, ma
316; CHECK-NEXT:    vmv.v.x v16, a0
317; CHECK-NEXT:    vand.vi v24, v16, 7
318; CHECK-NEXT:    vrsub.vi v16, v16, 0
319; CHECK-NEXT:    vsll.vv v24, v8, v24
320; CHECK-NEXT:    vand.vi v16, v16, 7
321; CHECK-NEXT:    vsrl.vv v8, v8, v16
322; CHECK-NEXT:    vor.vv v8, v24, v8
323; CHECK-NEXT:    ret
324;
325; CHECK-ZVKB-LABEL: vrol_vx_nxv64i8:
326; CHECK-ZVKB:       # %bb.0:
327; CHECK-ZVKB-NEXT:    vsetvli a1, zero, e8, m8, ta, ma
328; CHECK-ZVKB-NEXT:    vrol.vx v8, v8, a0
329; CHECK-ZVKB-NEXT:    ret
330  %b.head = insertelement <vscale x 64 x i8> poison, i8 %b, i32 0
331  %b.splat = shufflevector <vscale x 64 x i8> %b.head, <vscale x 64 x i8> poison, <vscale x 64 x i32> zeroinitializer
332  %x = call <vscale x 64 x i8> @llvm.fshl.nxv64i8(<vscale x 64 x i8> %a, <vscale x 64 x i8> %a, <vscale x 64 x i8> %b.splat)
333  ret <vscale x 64 x i8> %x
334}
335
336declare <vscale x 1 x i16> @llvm.fshl.nxv1i16(<vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>)
337
338define <vscale x 1 x i16> @vrol_vv_nxv1i16(<vscale x 1 x i16> %a, <vscale x 1 x i16> %b) {
339; CHECK-LABEL: vrol_vv_nxv1i16:
340; CHECK:       # %bb.0:
341; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, ma
342; CHECK-NEXT:    vand.vi v10, v9, 15
343; CHECK-NEXT:    vrsub.vi v9, v9, 0
344; CHECK-NEXT:    vsll.vv v10, v8, v10
345; CHECK-NEXT:    vand.vi v9, v9, 15
346; CHECK-NEXT:    vsrl.vv v8, v8, v9
347; CHECK-NEXT:    vor.vv v8, v10, v8
348; CHECK-NEXT:    ret
349;
350; CHECK-ZVKB-LABEL: vrol_vv_nxv1i16:
351; CHECK-ZVKB:       # %bb.0:
352; CHECK-ZVKB-NEXT:    vsetvli a0, zero, e16, mf4, ta, ma
353; CHECK-ZVKB-NEXT:    vrol.vv v8, v8, v9
354; CHECK-ZVKB-NEXT:    ret
355  %x = call <vscale x 1 x i16> @llvm.fshl.nxv1i16(<vscale x 1 x i16> %a, <vscale x 1 x i16> %a, <vscale x 1 x i16> %b)
356  ret <vscale x 1 x i16> %x
357}
358
359define <vscale x 1 x i16> @vrol_vx_nxv1i16(<vscale x 1 x i16> %a, i16 %b) {
360; CHECK-LABEL: vrol_vx_nxv1i16:
361; CHECK:       # %bb.0:
362; CHECK-NEXT:    vsetvli a1, zero, e16, mf4, ta, ma
363; CHECK-NEXT:    vmv.v.x v9, a0
364; CHECK-NEXT:    vand.vi v10, v9, 15
365; CHECK-NEXT:    vrsub.vi v9, v9, 0
366; CHECK-NEXT:    vsll.vv v10, v8, v10
367; CHECK-NEXT:    vand.vi v9, v9, 15
368; CHECK-NEXT:    vsrl.vv v8, v8, v9
369; CHECK-NEXT:    vor.vv v8, v10, v8
370; CHECK-NEXT:    ret
371;
372; CHECK-ZVKB-LABEL: vrol_vx_nxv1i16:
373; CHECK-ZVKB:       # %bb.0:
374; CHECK-ZVKB-NEXT:    vsetvli a1, zero, e16, mf4, ta, ma
375; CHECK-ZVKB-NEXT:    vrol.vx v8, v8, a0
376; CHECK-ZVKB-NEXT:    ret
377  %b.head = insertelement <vscale x 1 x i16> poison, i16 %b, i32 0
378  %b.splat = shufflevector <vscale x 1 x i16> %b.head, <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer
379  %x = call <vscale x 1 x i16> @llvm.fshl.nxv1i16(<vscale x 1 x i16> %a, <vscale x 1 x i16> %a, <vscale x 1 x i16> %b.splat)
380  ret <vscale x 1 x i16> %x
381}
382
383declare <vscale x 2 x i16> @llvm.fshl.nxv2i16(<vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>)
384
385define <vscale x 2 x i16> @vrol_vv_nxv2i16(<vscale x 2 x i16> %a, <vscale x 2 x i16> %b) {
386; CHECK-LABEL: vrol_vv_nxv2i16:
387; CHECK:       # %bb.0:
388; CHECK-NEXT:    vsetvli a0, zero, e16, mf2, ta, ma
389; CHECK-NEXT:    vand.vi v10, v9, 15
390; CHECK-NEXT:    vrsub.vi v9, v9, 0
391; CHECK-NEXT:    vsll.vv v10, v8, v10
392; CHECK-NEXT:    vand.vi v9, v9, 15
393; CHECK-NEXT:    vsrl.vv v8, v8, v9
394; CHECK-NEXT:    vor.vv v8, v10, v8
395; CHECK-NEXT:    ret
396;
397; CHECK-ZVKB-LABEL: vrol_vv_nxv2i16:
398; CHECK-ZVKB:       # %bb.0:
399; CHECK-ZVKB-NEXT:    vsetvli a0, zero, e16, mf2, ta, ma
400; CHECK-ZVKB-NEXT:    vrol.vv v8, v8, v9
401; CHECK-ZVKB-NEXT:    ret
402  %x = call <vscale x 2 x i16> @llvm.fshl.nxv2i16(<vscale x 2 x i16> %a, <vscale x 2 x i16> %a, <vscale x 2 x i16> %b)
403  ret <vscale x 2 x i16> %x
404}
405
406define <vscale x 2 x i16> @vrol_vx_nxv2i16(<vscale x 2 x i16> %a, i16 %b) {
407; CHECK-LABEL: vrol_vx_nxv2i16:
408; CHECK:       # %bb.0:
409; CHECK-NEXT:    vsetvli a1, zero, e16, mf2, ta, ma
410; CHECK-NEXT:    vmv.v.x v9, a0
411; CHECK-NEXT:    vand.vi v10, v9, 15
412; CHECK-NEXT:    vrsub.vi v9, v9, 0
413; CHECK-NEXT:    vsll.vv v10, v8, v10
414; CHECK-NEXT:    vand.vi v9, v9, 15
415; CHECK-NEXT:    vsrl.vv v8, v8, v9
416; CHECK-NEXT:    vor.vv v8, v10, v8
417; CHECK-NEXT:    ret
418;
419; CHECK-ZVKB-LABEL: vrol_vx_nxv2i16:
420; CHECK-ZVKB:       # %bb.0:
421; CHECK-ZVKB-NEXT:    vsetvli a1, zero, e16, mf2, ta, ma
422; CHECK-ZVKB-NEXT:    vrol.vx v8, v8, a0
423; CHECK-ZVKB-NEXT:    ret
424  %b.head = insertelement <vscale x 2 x i16> poison, i16 %b, i32 0
425  %b.splat = shufflevector <vscale x 2 x i16> %b.head, <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer
426  %x = call <vscale x 2 x i16> @llvm.fshl.nxv2i16(<vscale x 2 x i16> %a, <vscale x 2 x i16> %a, <vscale x 2 x i16> %b.splat)
427  ret <vscale x 2 x i16> %x
428}
429
430declare <vscale x 4 x i16> @llvm.fshl.nxv4i16(<vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>)
431
432define <vscale x 4 x i16> @vrol_vv_nxv4i16(<vscale x 4 x i16> %a, <vscale x 4 x i16> %b) {
433; CHECK-LABEL: vrol_vv_nxv4i16:
434; CHECK:       # %bb.0:
435; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, ma
436; CHECK-NEXT:    vand.vi v10, v9, 15
437; CHECK-NEXT:    vrsub.vi v9, v9, 0
438; CHECK-NEXT:    vsll.vv v10, v8, v10
439; CHECK-NEXT:    vand.vi v9, v9, 15
440; CHECK-NEXT:    vsrl.vv v8, v8, v9
441; CHECK-NEXT:    vor.vv v8, v10, v8
442; CHECK-NEXT:    ret
443;
444; CHECK-ZVKB-LABEL: vrol_vv_nxv4i16:
445; CHECK-ZVKB:       # %bb.0:
446; CHECK-ZVKB-NEXT:    vsetvli a0, zero, e16, m1, ta, ma
447; CHECK-ZVKB-NEXT:    vrol.vv v8, v8, v9
448; CHECK-ZVKB-NEXT:    ret
449  %x = call <vscale x 4 x i16> @llvm.fshl.nxv4i16(<vscale x 4 x i16> %a, <vscale x 4 x i16> %a, <vscale x 4 x i16> %b)
450  ret <vscale x 4 x i16> %x
451}
452
453define <vscale x 4 x i16> @vrol_vx_nxv4i16(<vscale x 4 x i16> %a, i16 %b) {
454; CHECK-LABEL: vrol_vx_nxv4i16:
455; CHECK:       # %bb.0:
456; CHECK-NEXT:    vsetvli a1, zero, e16, m1, ta, ma
457; CHECK-NEXT:    vmv.v.x v9, a0
458; CHECK-NEXT:    vand.vi v10, v9, 15
459; CHECK-NEXT:    vrsub.vi v9, v9, 0
460; CHECK-NEXT:    vsll.vv v10, v8, v10
461; CHECK-NEXT:    vand.vi v9, v9, 15
462; CHECK-NEXT:    vsrl.vv v8, v8, v9
463; CHECK-NEXT:    vor.vv v8, v10, v8
464; CHECK-NEXT:    ret
465;
466; CHECK-ZVKB-LABEL: vrol_vx_nxv4i16:
467; CHECK-ZVKB:       # %bb.0:
468; CHECK-ZVKB-NEXT:    vsetvli a1, zero, e16, m1, ta, ma
469; CHECK-ZVKB-NEXT:    vrol.vx v8, v8, a0
470; CHECK-ZVKB-NEXT:    ret
471  %b.head = insertelement <vscale x 4 x i16> poison, i16 %b, i32 0
472  %b.splat = shufflevector <vscale x 4 x i16> %b.head, <vscale x 4 x i16> poison, <vscale x 4 x i32> zeroinitializer
473  %x = call <vscale x 4 x i16> @llvm.fshl.nxv4i16(<vscale x 4 x i16> %a, <vscale x 4 x i16> %a, <vscale x 4 x i16> %b.splat)
474  ret <vscale x 4 x i16> %x
475}
476
477declare <vscale x 8 x i16> @llvm.fshl.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>)
478
479define <vscale x 8 x i16> @vrol_vv_nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
480; CHECK-LABEL: vrol_vv_nxv8i16:
481; CHECK:       # %bb.0:
482; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, ma
483; CHECK-NEXT:    vand.vi v12, v10, 15
484; CHECK-NEXT:    vrsub.vi v10, v10, 0
485; CHECK-NEXT:    vsll.vv v12, v8, v12
486; CHECK-NEXT:    vand.vi v10, v10, 15
487; CHECK-NEXT:    vsrl.vv v8, v8, v10
488; CHECK-NEXT:    vor.vv v8, v12, v8
489; CHECK-NEXT:    ret
490;
491; CHECK-ZVKB-LABEL: vrol_vv_nxv8i16:
492; CHECK-ZVKB:       # %bb.0:
493; CHECK-ZVKB-NEXT:    vsetvli a0, zero, e16, m2, ta, ma
494; CHECK-ZVKB-NEXT:    vrol.vv v8, v8, v10
495; CHECK-ZVKB-NEXT:    ret
496  %x = call <vscale x 8 x i16> @llvm.fshl.nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b)
497  ret <vscale x 8 x i16> %x
498}
499
500define <vscale x 8 x i16> @vrol_vx_nxv8i16(<vscale x 8 x i16> %a, i16 %b) {
501; CHECK-LABEL: vrol_vx_nxv8i16:
502; CHECK:       # %bb.0:
503; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, ma
504; CHECK-NEXT:    vmv.v.x v10, a0
505; CHECK-NEXT:    vand.vi v12, v10, 15
506; CHECK-NEXT:    vrsub.vi v10, v10, 0
507; CHECK-NEXT:    vsll.vv v12, v8, v12
508; CHECK-NEXT:    vand.vi v10, v10, 15
509; CHECK-NEXT:    vsrl.vv v8, v8, v10
510; CHECK-NEXT:    vor.vv v8, v12, v8
511; CHECK-NEXT:    ret
512;
513; CHECK-ZVKB-LABEL: vrol_vx_nxv8i16:
514; CHECK-ZVKB:       # %bb.0:
515; CHECK-ZVKB-NEXT:    vsetvli a1, zero, e16, m2, ta, ma
516; CHECK-ZVKB-NEXT:    vrol.vx v8, v8, a0
517; CHECK-ZVKB-NEXT:    ret
518  %b.head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0
519  %b.splat = shufflevector <vscale x 8 x i16> %b.head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
520  %x = call <vscale x 8 x i16> @llvm.fshl.nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b.splat)
521  ret <vscale x 8 x i16> %x
522}
523
524declare <vscale x 16 x i16> @llvm.fshl.nxv16i16(<vscale x 16 x i16>, <vscale x 16 x i16>, <vscale x 16 x i16>)
525
526define <vscale x 16 x i16> @vrol_vv_nxv16i16(<vscale x 16 x i16> %a, <vscale x 16 x i16> %b) {
527; CHECK-LABEL: vrol_vv_nxv16i16:
528; CHECK:       # %bb.0:
529; CHECK-NEXT:    vsetvli a0, zero, e16, m4, ta, ma
530; CHECK-NEXT:    vand.vi v16, v12, 15
531; CHECK-NEXT:    vrsub.vi v12, v12, 0
532; CHECK-NEXT:    vsll.vv v16, v8, v16
533; CHECK-NEXT:    vand.vi v12, v12, 15
534; CHECK-NEXT:    vsrl.vv v8, v8, v12
535; CHECK-NEXT:    vor.vv v8, v16, v8
536; CHECK-NEXT:    ret
537;
538; CHECK-ZVKB-LABEL: vrol_vv_nxv16i16:
539; CHECK-ZVKB:       # %bb.0:
540; CHECK-ZVKB-NEXT:    vsetvli a0, zero, e16, m4, ta, ma
541; CHECK-ZVKB-NEXT:    vrol.vv v8, v8, v12
542; CHECK-ZVKB-NEXT:    ret
543  %x = call <vscale x 16 x i16> @llvm.fshl.nxv16i16(<vscale x 16 x i16> %a, <vscale x 16 x i16> %a, <vscale x 16 x i16> %b)
544  ret <vscale x 16 x i16> %x
545}
546
547define <vscale x 16 x i16> @vrol_vx_nxv16i16(<vscale x 16 x i16> %a, i16 %b) {
548; CHECK-LABEL: vrol_vx_nxv16i16:
549; CHECK:       # %bb.0:
550; CHECK-NEXT:    vsetvli a1, zero, e16, m4, ta, ma
551; CHECK-NEXT:    vmv.v.x v12, a0
552; CHECK-NEXT:    vand.vi v16, v12, 15
553; CHECK-NEXT:    vrsub.vi v12, v12, 0
554; CHECK-NEXT:    vsll.vv v16, v8, v16
555; CHECK-NEXT:    vand.vi v12, v12, 15
556; CHECK-NEXT:    vsrl.vv v8, v8, v12
557; CHECK-NEXT:    vor.vv v8, v16, v8
558; CHECK-NEXT:    ret
559;
560; CHECK-ZVKB-LABEL: vrol_vx_nxv16i16:
561; CHECK-ZVKB:       # %bb.0:
562; CHECK-ZVKB-NEXT:    vsetvli a1, zero, e16, m4, ta, ma
563; CHECK-ZVKB-NEXT:    vrol.vx v8, v8, a0
564; CHECK-ZVKB-NEXT:    ret
565  %b.head = insertelement <vscale x 16 x i16> poison, i16 %b, i32 0
566  %b.splat = shufflevector <vscale x 16 x i16> %b.head, <vscale x 16 x i16> poison, <vscale x 16 x i32> zeroinitializer
567  %x = call <vscale x 16 x i16> @llvm.fshl.nxv16i16(<vscale x 16 x i16> %a, <vscale x 16 x i16> %a, <vscale x 16 x i16> %b.splat)
568  ret <vscale x 16 x i16> %x
569}
570
571declare <vscale x 32 x i16> @llvm.fshl.nxv32i16(<vscale x 32 x i16>, <vscale x 32 x i16>, <vscale x 32 x i16>)
572
573define <vscale x 32 x i16> @vrol_vv_nxv32i16(<vscale x 32 x i16> %a, <vscale x 32 x i16> %b) {
574; CHECK-LABEL: vrol_vv_nxv32i16:
575; CHECK:       # %bb.0:
576; CHECK-NEXT:    vsetvli a0, zero, e16, m8, ta, ma
577; CHECK-NEXT:    vand.vi v24, v16, 15
578; CHECK-NEXT:    vrsub.vi v16, v16, 0
579; CHECK-NEXT:    vsll.vv v24, v8, v24
580; CHECK-NEXT:    vand.vi v16, v16, 15
581; CHECK-NEXT:    vsrl.vv v8, v8, v16
582; CHECK-NEXT:    vor.vv v8, v24, v8
583; CHECK-NEXT:    ret
584;
585; CHECK-ZVKB-LABEL: vrol_vv_nxv32i16:
586; CHECK-ZVKB:       # %bb.0:
587; CHECK-ZVKB-NEXT:    vsetvli a0, zero, e16, m8, ta, ma
588; CHECK-ZVKB-NEXT:    vrol.vv v8, v8, v16
589; CHECK-ZVKB-NEXT:    ret
590  %x = call <vscale x 32 x i16> @llvm.fshl.nxv32i16(<vscale x 32 x i16> %a, <vscale x 32 x i16> %a, <vscale x 32 x i16> %b)
591  ret <vscale x 32 x i16> %x
592}
593
594define <vscale x 32 x i16> @vrol_vx_nxv32i16(<vscale x 32 x i16> %a, i16 %b) {
595; CHECK-LABEL: vrol_vx_nxv32i16:
596; CHECK:       # %bb.0:
597; CHECK-NEXT:    vsetvli a1, zero, e16, m8, ta, ma
598; CHECK-NEXT:    vmv.v.x v16, a0
599; CHECK-NEXT:    vand.vi v24, v16, 15
600; CHECK-NEXT:    vrsub.vi v16, v16, 0
601; CHECK-NEXT:    vsll.vv v24, v8, v24
602; CHECK-NEXT:    vand.vi v16, v16, 15
603; CHECK-NEXT:    vsrl.vv v8, v8, v16
604; CHECK-NEXT:    vor.vv v8, v24, v8
605; CHECK-NEXT:    ret
606;
607; CHECK-ZVKB-LABEL: vrol_vx_nxv32i16:
608; CHECK-ZVKB:       # %bb.0:
609; CHECK-ZVKB-NEXT:    vsetvli a1, zero, e16, m8, ta, ma
610; CHECK-ZVKB-NEXT:    vrol.vx v8, v8, a0
611; CHECK-ZVKB-NEXT:    ret
612  %b.head = insertelement <vscale x 32 x i16> poison, i16 %b, i32 0
613  %b.splat = shufflevector <vscale x 32 x i16> %b.head, <vscale x 32 x i16> poison, <vscale x 32 x i32> zeroinitializer
614  %x = call <vscale x 32 x i16> @llvm.fshl.nxv32i16(<vscale x 32 x i16> %a, <vscale x 32 x i16> %a, <vscale x 32 x i16> %b.splat)
615  ret <vscale x 32 x i16> %x
616}
617
618declare <vscale x 1 x i32> @llvm.fshl.nxv1i32(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>)
619
620define <vscale x 1 x i32> @vrol_vv_nxv1i32(<vscale x 1 x i32> %a, <vscale x 1 x i32> %b) {
621; CHECK-LABEL: vrol_vv_nxv1i32:
622; CHECK:       # %bb.0:
623; CHECK-NEXT:    li a0, 31
624; CHECK-NEXT:    vsetvli a1, zero, e32, mf2, ta, ma
625; CHECK-NEXT:    vrsub.vi v10, v9, 0
626; CHECK-NEXT:    vand.vx v9, v9, a0
627; CHECK-NEXT:    vand.vx v10, v10, a0
628; CHECK-NEXT:    vsll.vv v9, v8, v9
629; CHECK-NEXT:    vsrl.vv v8, v8, v10
630; CHECK-NEXT:    vor.vv v8, v9, v8
631; CHECK-NEXT:    ret
632;
633; CHECK-ZVKB-LABEL: vrol_vv_nxv1i32:
634; CHECK-ZVKB:       # %bb.0:
635; CHECK-ZVKB-NEXT:    vsetvli a0, zero, e32, mf2, ta, ma
636; CHECK-ZVKB-NEXT:    vrol.vv v8, v8, v9
637; CHECK-ZVKB-NEXT:    ret
638  %x = call <vscale x 1 x i32> @llvm.fshl.nxv1i32(<vscale x 1 x i32> %a, <vscale x 1 x i32> %a, <vscale x 1 x i32> %b)
639  ret <vscale x 1 x i32> %x
640}
641
642define <vscale x 1 x i32> @vrol_vx_nxv1i32(<vscale x 1 x i32> %a, i32 %b) {
643; CHECK-RV32-LABEL: vrol_vx_nxv1i32:
644; CHECK-RV32:       # %bb.0:
645; CHECK-RV32-NEXT:    andi a1, a0, 31
646; CHECK-RV32-NEXT:    neg a0, a0
647; CHECK-RV32-NEXT:    vsetvli a2, zero, e32, mf2, ta, ma
648; CHECK-RV32-NEXT:    vsll.vx v9, v8, a1
649; CHECK-RV32-NEXT:    andi a0, a0, 31
650; CHECK-RV32-NEXT:    vsrl.vx v8, v8, a0
651; CHECK-RV32-NEXT:    vor.vv v8, v9, v8
652; CHECK-RV32-NEXT:    ret
653;
654; CHECK-RV64-LABEL: vrol_vx_nxv1i32:
655; CHECK-RV64:       # %bb.0:
656; CHECK-RV64-NEXT:    vsetvli a1, zero, e32, mf2, ta, ma
657; CHECK-RV64-NEXT:    vmv.v.x v9, a0
658; CHECK-RV64-NEXT:    li a0, 31
659; CHECK-RV64-NEXT:    vand.vx v10, v9, a0
660; CHECK-RV64-NEXT:    vrsub.vi v9, v9, 0
661; CHECK-RV64-NEXT:    vsll.vv v10, v8, v10
662; CHECK-RV64-NEXT:    vand.vx v9, v9, a0
663; CHECK-RV64-NEXT:    vsrl.vv v8, v8, v9
664; CHECK-RV64-NEXT:    vor.vv v8, v10, v8
665; CHECK-RV64-NEXT:    ret
666;
667; CHECK-ZVKB-LABEL: vrol_vx_nxv1i32:
668; CHECK-ZVKB:       # %bb.0:
669; CHECK-ZVKB-NEXT:    vsetvli a1, zero, e32, mf2, ta, ma
670; CHECK-ZVKB-NEXT:    vrol.vx v8, v8, a0
671; CHECK-ZVKB-NEXT:    ret
672  %b.head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 0
673  %b.splat = shufflevector <vscale x 1 x i32> %b.head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer
674  %x = call <vscale x 1 x i32> @llvm.fshl.nxv1i32(<vscale x 1 x i32> %a, <vscale x 1 x i32> %a, <vscale x 1 x i32> %b.splat)
675  ret <vscale x 1 x i32> %x
676}
677
678declare <vscale x 2 x i32> @llvm.fshl.nxv2i32(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>)
679
680define <vscale x 2 x i32> @vrol_vv_nxv2i32(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b) {
681; CHECK-LABEL: vrol_vv_nxv2i32:
682; CHECK:       # %bb.0:
683; CHECK-NEXT:    li a0, 31
684; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, ma
685; CHECK-NEXT:    vrsub.vi v10, v9, 0
686; CHECK-NEXT:    vand.vx v9, v9, a0
687; CHECK-NEXT:    vand.vx v10, v10, a0
688; CHECK-NEXT:    vsll.vv v9, v8, v9
689; CHECK-NEXT:    vsrl.vv v8, v8, v10
690; CHECK-NEXT:    vor.vv v8, v9, v8
691; CHECK-NEXT:    ret
692;
693; CHECK-ZVKB-LABEL: vrol_vv_nxv2i32:
694; CHECK-ZVKB:       # %bb.0:
695; CHECK-ZVKB-NEXT:    vsetvli a0, zero, e32, m1, ta, ma
696; CHECK-ZVKB-NEXT:    vrol.vv v8, v8, v9
697; CHECK-ZVKB-NEXT:    ret
698  %x = call <vscale x 2 x i32> @llvm.fshl.nxv2i32(<vscale x 2 x i32> %a, <vscale x 2 x i32> %a, <vscale x 2 x i32> %b)
699  ret <vscale x 2 x i32> %x
700}
701
702define <vscale x 2 x i32> @vrol_vx_nxv2i32(<vscale x 2 x i32> %a, i32 %b) {
703; CHECK-RV32-LABEL: vrol_vx_nxv2i32:
704; CHECK-RV32:       # %bb.0:
705; CHECK-RV32-NEXT:    andi a1, a0, 31
706; CHECK-RV32-NEXT:    neg a0, a0
707; CHECK-RV32-NEXT:    vsetvli a2, zero, e32, m1, ta, ma
708; CHECK-RV32-NEXT:    vsll.vx v9, v8, a1
709; CHECK-RV32-NEXT:    andi a0, a0, 31
710; CHECK-RV32-NEXT:    vsrl.vx v8, v8, a0
711; CHECK-RV32-NEXT:    vor.vv v8, v9, v8
712; CHECK-RV32-NEXT:    ret
713;
714; CHECK-RV64-LABEL: vrol_vx_nxv2i32:
715; CHECK-RV64:       # %bb.0:
716; CHECK-RV64-NEXT:    vsetvli a1, zero, e32, m1, ta, ma
717; CHECK-RV64-NEXT:    vmv.v.x v9, a0
718; CHECK-RV64-NEXT:    li a0, 31
719; CHECK-RV64-NEXT:    vand.vx v10, v9, a0
720; CHECK-RV64-NEXT:    vrsub.vi v9, v9, 0
721; CHECK-RV64-NEXT:    vsll.vv v10, v8, v10
722; CHECK-RV64-NEXT:    vand.vx v9, v9, a0
723; CHECK-RV64-NEXT:    vsrl.vv v8, v8, v9
724; CHECK-RV64-NEXT:    vor.vv v8, v10, v8
725; CHECK-RV64-NEXT:    ret
726;
727; CHECK-ZVKB-LABEL: vrol_vx_nxv2i32:
728; CHECK-ZVKB:       # %bb.0:
729; CHECK-ZVKB-NEXT:    vsetvli a1, zero, e32, m1, ta, ma
730; CHECK-ZVKB-NEXT:    vrol.vx v8, v8, a0
731; CHECK-ZVKB-NEXT:    ret
732  %b.head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0
733  %b.splat = shufflevector <vscale x 2 x i32> %b.head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer
734  %x = call <vscale x 2 x i32> @llvm.fshl.nxv2i32(<vscale x 2 x i32> %a, <vscale x 2 x i32> %a, <vscale x 2 x i32> %b.splat)
735  ret <vscale x 2 x i32> %x
736}
737
738declare <vscale x 4 x i32> @llvm.fshl.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>)
739
740define <vscale x 4 x i32> @vrol_vv_nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
741; CHECK-LABEL: vrol_vv_nxv4i32:
742; CHECK:       # %bb.0:
743; CHECK-NEXT:    li a0, 31
744; CHECK-NEXT:    vsetvli a1, zero, e32, m2, ta, ma
745; CHECK-NEXT:    vrsub.vi v12, v10, 0
746; CHECK-NEXT:    vand.vx v10, v10, a0
747; CHECK-NEXT:    vand.vx v12, v12, a0
748; CHECK-NEXT:    vsll.vv v10, v8, v10
749; CHECK-NEXT:    vsrl.vv v8, v8, v12
750; CHECK-NEXT:    vor.vv v8, v10, v8
751; CHECK-NEXT:    ret
752;
753; CHECK-ZVKB-LABEL: vrol_vv_nxv4i32:
754; CHECK-ZVKB:       # %bb.0:
755; CHECK-ZVKB-NEXT:    vsetvli a0, zero, e32, m2, ta, ma
756; CHECK-ZVKB-NEXT:    vrol.vv v8, v8, v10
757; CHECK-ZVKB-NEXT:    ret
758  %x = call <vscale x 4 x i32> @llvm.fshl.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b)
759  ret <vscale x 4 x i32> %x
760}
761
762define <vscale x 4 x i32> @vrol_vx_nxv4i32(<vscale x 4 x i32> %a, i32 %b) {
763; CHECK-RV32-LABEL: vrol_vx_nxv4i32:
764; CHECK-RV32:       # %bb.0:
765; CHECK-RV32-NEXT:    andi a1, a0, 31
766; CHECK-RV32-NEXT:    neg a0, a0
767; CHECK-RV32-NEXT:    vsetvli a2, zero, e32, m2, ta, ma
768; CHECK-RV32-NEXT:    vsll.vx v10, v8, a1
769; CHECK-RV32-NEXT:    andi a0, a0, 31
770; CHECK-RV32-NEXT:    vsrl.vx v8, v8, a0
771; CHECK-RV32-NEXT:    vor.vv v8, v10, v8
772; CHECK-RV32-NEXT:    ret
773;
774; CHECK-RV64-LABEL: vrol_vx_nxv4i32:
775; CHECK-RV64:       # %bb.0:
776; CHECK-RV64-NEXT:    vsetvli a1, zero, e32, m2, ta, ma
777; CHECK-RV64-NEXT:    vmv.v.x v10, a0
778; CHECK-RV64-NEXT:    li a0, 31
779; CHECK-RV64-NEXT:    vand.vx v12, v10, a0
780; CHECK-RV64-NEXT:    vrsub.vi v10, v10, 0
781; CHECK-RV64-NEXT:    vsll.vv v12, v8, v12
782; CHECK-RV64-NEXT:    vand.vx v10, v10, a0
783; CHECK-RV64-NEXT:    vsrl.vv v8, v8, v10
784; CHECK-RV64-NEXT:    vor.vv v8, v12, v8
785; CHECK-RV64-NEXT:    ret
786;
787; CHECK-ZVKB-LABEL: vrol_vx_nxv4i32:
788; CHECK-ZVKB:       # %bb.0:
789; CHECK-ZVKB-NEXT:    vsetvli a1, zero, e32, m2, ta, ma
790; CHECK-ZVKB-NEXT:    vrol.vx v8, v8, a0
791; CHECK-ZVKB-NEXT:    ret
792  %b.head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0
793  %b.splat = shufflevector <vscale x 4 x i32> %b.head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
794  %x = call <vscale x 4 x i32> @llvm.fshl.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b.splat)
795  ret <vscale x 4 x i32> %x
796}
797
798declare <vscale x 8 x i32> @llvm.fshl.nxv8i32(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>)
799
800define <vscale x 8 x i32> @vrol_vv_nxv8i32(<vscale x 8 x i32> %a, <vscale x 8 x i32> %b) {
801; CHECK-LABEL: vrol_vv_nxv8i32:
802; CHECK:       # %bb.0:
803; CHECK-NEXT:    li a0, 31
804; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, ma
805; CHECK-NEXT:    vrsub.vi v16, v12, 0
806; CHECK-NEXT:    vand.vx v12, v12, a0
807; CHECK-NEXT:    vand.vx v16, v16, a0
808; CHECK-NEXT:    vsll.vv v12, v8, v12
809; CHECK-NEXT:    vsrl.vv v8, v8, v16
810; CHECK-NEXT:    vor.vv v8, v12, v8
811; CHECK-NEXT:    ret
812;
813; CHECK-ZVKB-LABEL: vrol_vv_nxv8i32:
814; CHECK-ZVKB:       # %bb.0:
815; CHECK-ZVKB-NEXT:    vsetvli a0, zero, e32, m4, ta, ma
816; CHECK-ZVKB-NEXT:    vrol.vv v8, v8, v12
817; CHECK-ZVKB-NEXT:    ret
818  %x = call <vscale x 8 x i32> @llvm.fshl.nxv8i32(<vscale x 8 x i32> %a, <vscale x 8 x i32> %a, <vscale x 8 x i32> %b)
819  ret <vscale x 8 x i32> %x
820}
821
822define <vscale x 8 x i32> @vrol_vx_nxv8i32(<vscale x 8 x i32> %a, i32 %b) {
823; CHECK-RV32-LABEL: vrol_vx_nxv8i32:
824; CHECK-RV32:       # %bb.0:
825; CHECK-RV32-NEXT:    andi a1, a0, 31
826; CHECK-RV32-NEXT:    neg a0, a0
827; CHECK-RV32-NEXT:    vsetvli a2, zero, e32, m4, ta, ma
828; CHECK-RV32-NEXT:    vsll.vx v12, v8, a1
829; CHECK-RV32-NEXT:    andi a0, a0, 31
830; CHECK-RV32-NEXT:    vsrl.vx v8, v8, a0
831; CHECK-RV32-NEXT:    vor.vv v8, v12, v8
832; CHECK-RV32-NEXT:    ret
833;
834; CHECK-RV64-LABEL: vrol_vx_nxv8i32:
835; CHECK-RV64:       # %bb.0:
836; CHECK-RV64-NEXT:    vsetvli a1, zero, e32, m4, ta, ma
837; CHECK-RV64-NEXT:    vmv.v.x v12, a0
838; CHECK-RV64-NEXT:    li a0, 31
839; CHECK-RV64-NEXT:    vand.vx v16, v12, a0
840; CHECK-RV64-NEXT:    vrsub.vi v12, v12, 0
841; CHECK-RV64-NEXT:    vsll.vv v16, v8, v16
842; CHECK-RV64-NEXT:    vand.vx v12, v12, a0
843; CHECK-RV64-NEXT:    vsrl.vv v8, v8, v12
844; CHECK-RV64-NEXT:    vor.vv v8, v16, v8
845; CHECK-RV64-NEXT:    ret
846;
847; CHECK-ZVKB-LABEL: vrol_vx_nxv8i32:
848; CHECK-ZVKB:       # %bb.0:
849; CHECK-ZVKB-NEXT:    vsetvli a1, zero, e32, m4, ta, ma
850; CHECK-ZVKB-NEXT:    vrol.vx v8, v8, a0
851; CHECK-ZVKB-NEXT:    ret
852  %b.head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
853  %b.splat = shufflevector <vscale x 8 x i32> %b.head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
854  %x = call <vscale x 8 x i32> @llvm.fshl.nxv8i32(<vscale x 8 x i32> %a, <vscale x 8 x i32> %a, <vscale x 8 x i32> %b.splat)
855  ret <vscale x 8 x i32> %x
856}
857
858declare <vscale x 16 x i32> @llvm.fshl.nxv16i32(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>)
859
860define <vscale x 16 x i32> @vrol_vv_nxv16i32(<vscale x 16 x i32> %a, <vscale x 16 x i32> %b) {
861; CHECK-LABEL: vrol_vv_nxv16i32:
862; CHECK:       # %bb.0:
863; CHECK-NEXT:    li a0, 31
864; CHECK-NEXT:    vsetvli a1, zero, e32, m8, ta, ma
865; CHECK-NEXT:    vrsub.vi v24, v16, 0
866; CHECK-NEXT:    vand.vx v16, v16, a0
867; CHECK-NEXT:    vand.vx v24, v24, a0
868; CHECK-NEXT:    vsll.vv v16, v8, v16
869; CHECK-NEXT:    vsrl.vv v8, v8, v24
870; CHECK-NEXT:    vor.vv v8, v16, v8
871; CHECK-NEXT:    ret
872;
873; CHECK-ZVKB-LABEL: vrol_vv_nxv16i32:
874; CHECK-ZVKB:       # %bb.0:
875; CHECK-ZVKB-NEXT:    vsetvli a0, zero, e32, m8, ta, ma
876; CHECK-ZVKB-NEXT:    vrol.vv v8, v8, v16
877; CHECK-ZVKB-NEXT:    ret
878  %x = call <vscale x 16 x i32> @llvm.fshl.nxv16i32(<vscale x 16 x i32> %a, <vscale x 16 x i32> %a, <vscale x 16 x i32> %b)
879  ret <vscale x 16 x i32> %x
880}
881
882define <vscale x 16 x i32> @vrol_vx_nxv16i32(<vscale x 16 x i32> %a, i32 %b) {
883; CHECK-RV32-LABEL: vrol_vx_nxv16i32:
884; CHECK-RV32:       # %bb.0:
885; CHECK-RV32-NEXT:    andi a1, a0, 31
886; CHECK-RV32-NEXT:    neg a0, a0
887; CHECK-RV32-NEXT:    vsetvli a2, zero, e32, m8, ta, ma
888; CHECK-RV32-NEXT:    vsll.vx v16, v8, a1
889; CHECK-RV32-NEXT:    andi a0, a0, 31
890; CHECK-RV32-NEXT:    vsrl.vx v8, v8, a0
891; CHECK-RV32-NEXT:    vor.vv v8, v16, v8
892; CHECK-RV32-NEXT:    ret
893;
894; CHECK-RV64-LABEL: vrol_vx_nxv16i32:
895; CHECK-RV64:       # %bb.0:
896; CHECK-RV64-NEXT:    vsetvli a1, zero, e32, m8, ta, ma
897; CHECK-RV64-NEXT:    vmv.v.x v16, a0
898; CHECK-RV64-NEXT:    li a0, 31
899; CHECK-RV64-NEXT:    vand.vx v24, v16, a0
900; CHECK-RV64-NEXT:    vrsub.vi v16, v16, 0
901; CHECK-RV64-NEXT:    vsll.vv v24, v8, v24
902; CHECK-RV64-NEXT:    vand.vx v16, v16, a0
903; CHECK-RV64-NEXT:    vsrl.vv v8, v8, v16
904; CHECK-RV64-NEXT:    vor.vv v8, v24, v8
905; CHECK-RV64-NEXT:    ret
906;
907; CHECK-ZVKB-LABEL: vrol_vx_nxv16i32:
908; CHECK-ZVKB:       # %bb.0:
909; CHECK-ZVKB-NEXT:    vsetvli a1, zero, e32, m8, ta, ma
910; CHECK-ZVKB-NEXT:    vrol.vx v8, v8, a0
911; CHECK-ZVKB-NEXT:    ret
912  %b.head = insertelement <vscale x 16 x i32> poison, i32 %b, i32 0
913  %b.splat = shufflevector <vscale x 16 x i32> %b.head, <vscale x 16 x i32> poison, <vscale x 16 x i32> zeroinitializer
914  %x = call <vscale x 16 x i32> @llvm.fshl.nxv16i32(<vscale x 16 x i32> %a, <vscale x 16 x i32> %a, <vscale x 16 x i32> %b.splat)
915  ret <vscale x 16 x i32> %x
916}
917
918declare <vscale x 1 x i64> @llvm.fshl.nxv1i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>)
919
920define <vscale x 1 x i64> @vrol_vv_nxv1i64(<vscale x 1 x i64> %a, <vscale x 1 x i64> %b) {
921; CHECK-LABEL: vrol_vv_nxv1i64:
922; CHECK:       # %bb.0:
923; CHECK-NEXT:    li a0, 63
924; CHECK-NEXT:    vsetvli a1, zero, e64, m1, ta, ma
925; CHECK-NEXT:    vrsub.vi v10, v9, 0
926; CHECK-NEXT:    vand.vx v9, v9, a0
927; CHECK-NEXT:    vand.vx v10, v10, a0
928; CHECK-NEXT:    vsll.vv v9, v8, v9
929; CHECK-NEXT:    vsrl.vv v8, v8, v10
930; CHECK-NEXT:    vor.vv v8, v9, v8
931; CHECK-NEXT:    ret
932;
933; CHECK-ZVKB-LABEL: vrol_vv_nxv1i64:
934; CHECK-ZVKB:       # %bb.0:
935; CHECK-ZVKB-NEXT:    vsetvli a0, zero, e64, m1, ta, ma
936; CHECK-ZVKB-NEXT:    vrol.vv v8, v8, v9
937; CHECK-ZVKB-NEXT:    ret
938  %x = call <vscale x 1 x i64> @llvm.fshl.nxv1i64(<vscale x 1 x i64> %a, <vscale x 1 x i64> %a, <vscale x 1 x i64> %b)
939  ret <vscale x 1 x i64> %x
940}
941
942define <vscale x 1 x i64> @vrol_vx_nxv1i64(<vscale x 1 x i64> %a, i64 %b) {
943; CHECK-RV32-LABEL: vrol_vx_nxv1i64:
944; CHECK-RV32:       # %bb.0:
945; CHECK-RV32-NEXT:    vsetvli a1, zero, e64, m1, ta, ma
946; CHECK-RV32-NEXT:    vmv.v.x v9, a0
947; CHECK-RV32-NEXT:    vsetvli zero, zero, e32, mf2, ta, ma
948; CHECK-RV32-NEXT:    vmv.v.i v10, 0
949; CHECK-RV32-NEXT:    vwsub.vx v11, v10, a0
950; CHECK-RV32-NEXT:    li a0, 63
951; CHECK-RV32-NEXT:    vsetvli zero, zero, e64, m1, ta, ma
952; CHECK-RV32-NEXT:    vand.vx v9, v9, a0
953; CHECK-RV32-NEXT:    vand.vx v10, v11, a0
954; CHECK-RV32-NEXT:    vsrl.vv v10, v8, v10
955; CHECK-RV32-NEXT:    vsll.vv v8, v8, v9
956; CHECK-RV32-NEXT:    vor.vv v8, v8, v10
957; CHECK-RV32-NEXT:    ret
958;
959; CHECK-RV64-LABEL: vrol_vx_nxv1i64:
960; CHECK-RV64:       # %bb.0:
961; CHECK-RV64-NEXT:    andi a1, a0, 63
962; CHECK-RV64-NEXT:    negw a0, a0
963; CHECK-RV64-NEXT:    vsetvli a2, zero, e64, m1, ta, ma
964; CHECK-RV64-NEXT:    vsll.vx v9, v8, a1
965; CHECK-RV64-NEXT:    andi a0, a0, 63
966; CHECK-RV64-NEXT:    vsrl.vx v8, v8, a0
967; CHECK-RV64-NEXT:    vor.vv v8, v9, v8
968; CHECK-RV64-NEXT:    ret
969;
970; CHECK-ZVKB-LABEL: vrol_vx_nxv1i64:
971; CHECK-ZVKB:       # %bb.0:
972; CHECK-ZVKB-NEXT:    vsetvli a1, zero, e64, m1, ta, ma
973; CHECK-ZVKB-NEXT:    vrol.vx v8, v8, a0
974; CHECK-ZVKB-NEXT:    ret
975  %b.head = insertelement <vscale x 1 x i64> poison, i64 %b, i32 0
976  %b.splat = shufflevector <vscale x 1 x i64> %b.head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer
977  %x = call <vscale x 1 x i64> @llvm.fshl.nxv1i64(<vscale x 1 x i64> %a, <vscale x 1 x i64> %a, <vscale x 1 x i64> %b.splat)
978  ret <vscale x 1 x i64> %x
979}
980
981declare <vscale x 2 x i64> @llvm.fshl.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>)
982
983define <vscale x 2 x i64> @vrol_vv_nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
984; CHECK-LABEL: vrol_vv_nxv2i64:
985; CHECK:       # %bb.0:
986; CHECK-NEXT:    li a0, 63
987; CHECK-NEXT:    vsetvli a1, zero, e64, m2, ta, ma
988; CHECK-NEXT:    vrsub.vi v12, v10, 0
989; CHECK-NEXT:    vand.vx v10, v10, a0
990; CHECK-NEXT:    vand.vx v12, v12, a0
991; CHECK-NEXT:    vsll.vv v10, v8, v10
992; CHECK-NEXT:    vsrl.vv v8, v8, v12
993; CHECK-NEXT:    vor.vv v8, v10, v8
994; CHECK-NEXT:    ret
995;
996; CHECK-ZVKB-LABEL: vrol_vv_nxv2i64:
997; CHECK-ZVKB:       # %bb.0:
998; CHECK-ZVKB-NEXT:    vsetvli a0, zero, e64, m2, ta, ma
999; CHECK-ZVKB-NEXT:    vrol.vv v8, v8, v10
1000; CHECK-ZVKB-NEXT:    ret
1001  %x = call <vscale x 2 x i64> @llvm.fshl.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b)
1002  ret <vscale x 2 x i64> %x
1003}
1004
1005define <vscale x 2 x i64> @vrol_vx_nxv2i64(<vscale x 2 x i64> %a, i64 %b) {
1006; CHECK-RV32-LABEL: vrol_vx_nxv2i64:
1007; CHECK-RV32:       # %bb.0:
1008; CHECK-RV32-NEXT:    vsetvli a1, zero, e64, m2, ta, ma
1009; CHECK-RV32-NEXT:    vmv.v.x v10, a0
1010; CHECK-RV32-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
1011; CHECK-RV32-NEXT:    vmv.v.i v12, 0
1012; CHECK-RV32-NEXT:    vwsub.vx v14, v12, a0
1013; CHECK-RV32-NEXT:    li a0, 63
1014; CHECK-RV32-NEXT:    vsetvli zero, zero, e64, m2, ta, ma
1015; CHECK-RV32-NEXT:    vand.vx v10, v10, a0
1016; CHECK-RV32-NEXT:    vand.vx v12, v14, a0
1017; CHECK-RV32-NEXT:    vsrl.vv v12, v8, v12
1018; CHECK-RV32-NEXT:    vsll.vv v8, v8, v10
1019; CHECK-RV32-NEXT:    vor.vv v8, v8, v12
1020; CHECK-RV32-NEXT:    ret
1021;
1022; CHECK-RV64-LABEL: vrol_vx_nxv2i64:
1023; CHECK-RV64:       # %bb.0:
1024; CHECK-RV64-NEXT:    andi a1, a0, 63
1025; CHECK-RV64-NEXT:    negw a0, a0
1026; CHECK-RV64-NEXT:    vsetvli a2, zero, e64, m2, ta, ma
1027; CHECK-RV64-NEXT:    vsll.vx v10, v8, a1
1028; CHECK-RV64-NEXT:    andi a0, a0, 63
1029; CHECK-RV64-NEXT:    vsrl.vx v8, v8, a0
1030; CHECK-RV64-NEXT:    vor.vv v8, v10, v8
1031; CHECK-RV64-NEXT:    ret
1032;
1033; CHECK-ZVKB-LABEL: vrol_vx_nxv2i64:
1034; CHECK-ZVKB:       # %bb.0:
1035; CHECK-ZVKB-NEXT:    vsetvli a1, zero, e64, m2, ta, ma
1036; CHECK-ZVKB-NEXT:    vrol.vx v8, v8, a0
1037; CHECK-ZVKB-NEXT:    ret
1038  %b.head = insertelement <vscale x 2 x i64> poison, i64 %b, i32 0
1039  %b.splat = shufflevector <vscale x 2 x i64> %b.head, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
1040  %x = call <vscale x 2 x i64> @llvm.fshl.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b.splat)
1041  ret <vscale x 2 x i64> %x
1042}
1043
1044declare <vscale x 4 x i64> @llvm.fshl.nxv4i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>)
1045
1046define <vscale x 4 x i64> @vrol_vv_nxv4i64(<vscale x 4 x i64> %a, <vscale x 4 x i64> %b) {
1047; CHECK-LABEL: vrol_vv_nxv4i64:
1048; CHECK:       # %bb.0:
1049; CHECK-NEXT:    li a0, 63
1050; CHECK-NEXT:    vsetvli a1, zero, e64, m4, ta, ma
1051; CHECK-NEXT:    vrsub.vi v16, v12, 0
1052; CHECK-NEXT:    vand.vx v12, v12, a0
1053; CHECK-NEXT:    vand.vx v16, v16, a0
1054; CHECK-NEXT:    vsll.vv v12, v8, v12
1055; CHECK-NEXT:    vsrl.vv v8, v8, v16
1056; CHECK-NEXT:    vor.vv v8, v12, v8
1057; CHECK-NEXT:    ret
1058;
1059; CHECK-ZVKB-LABEL: vrol_vv_nxv4i64:
1060; CHECK-ZVKB:       # %bb.0:
1061; CHECK-ZVKB-NEXT:    vsetvli a0, zero, e64, m4, ta, ma
1062; CHECK-ZVKB-NEXT:    vrol.vv v8, v8, v12
1063; CHECK-ZVKB-NEXT:    ret
1064  %x = call <vscale x 4 x i64> @llvm.fshl.nxv4i64(<vscale x 4 x i64> %a, <vscale x 4 x i64> %a, <vscale x 4 x i64> %b)
1065  ret <vscale x 4 x i64> %x
1066}
1067
1068define <vscale x 4 x i64> @vrol_vx_nxv4i64(<vscale x 4 x i64> %a, i64 %b) {
1069; CHECK-RV32-LABEL: vrol_vx_nxv4i64:
1070; CHECK-RV32:       # %bb.0:
1071; CHECK-RV32-NEXT:    vsetvli a1, zero, e64, m4, ta, ma
1072; CHECK-RV32-NEXT:    vmv.v.x v12, a0
1073; CHECK-RV32-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
1074; CHECK-RV32-NEXT:    vmv.v.i v16, 0
1075; CHECK-RV32-NEXT:    vwsub.vx v20, v16, a0
1076; CHECK-RV32-NEXT:    li a0, 63
1077; CHECK-RV32-NEXT:    vsetvli zero, zero, e64, m4, ta, ma
1078; CHECK-RV32-NEXT:    vand.vx v12, v12, a0
1079; CHECK-RV32-NEXT:    vand.vx v16, v20, a0
1080; CHECK-RV32-NEXT:    vsrl.vv v16, v8, v16
1081; CHECK-RV32-NEXT:    vsll.vv v8, v8, v12
1082; CHECK-RV32-NEXT:    vor.vv v8, v8, v16
1083; CHECK-RV32-NEXT:    ret
1084;
1085; CHECK-RV64-LABEL: vrol_vx_nxv4i64:
1086; CHECK-RV64:       # %bb.0:
1087; CHECK-RV64-NEXT:    andi a1, a0, 63
1088; CHECK-RV64-NEXT:    negw a0, a0
1089; CHECK-RV64-NEXT:    vsetvli a2, zero, e64, m4, ta, ma
1090; CHECK-RV64-NEXT:    vsll.vx v12, v8, a1
1091; CHECK-RV64-NEXT:    andi a0, a0, 63
1092; CHECK-RV64-NEXT:    vsrl.vx v8, v8, a0
1093; CHECK-RV64-NEXT:    vor.vv v8, v12, v8
1094; CHECK-RV64-NEXT:    ret
1095;
1096; CHECK-ZVKB-LABEL: vrol_vx_nxv4i64:
1097; CHECK-ZVKB:       # %bb.0:
1098; CHECK-ZVKB-NEXT:    vsetvli a1, zero, e64, m4, ta, ma
1099; CHECK-ZVKB-NEXT:    vrol.vx v8, v8, a0
1100; CHECK-ZVKB-NEXT:    ret
1101  %b.head = insertelement <vscale x 4 x i64> poison, i64 %b, i32 0
1102  %b.splat = shufflevector <vscale x 4 x i64> %b.head, <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer
1103  %x = call <vscale x 4 x i64> @llvm.fshl.nxv4i64(<vscale x 4 x i64> %a, <vscale x 4 x i64> %a, <vscale x 4 x i64> %b.splat)
1104  ret <vscale x 4 x i64> %x
1105}
1106
1107declare <vscale x 8 x i64> @llvm.fshl.nxv8i64(<vscale x 8 x i64>, <vscale x 8 x i64>, <vscale x 8 x i64>)
1108
1109define <vscale x 8 x i64> @vrol_vv_nxv8i64(<vscale x 8 x i64> %a, <vscale x 8 x i64> %b) {
1110; CHECK-LABEL: vrol_vv_nxv8i64:
1111; CHECK:       # %bb.0:
1112; CHECK-NEXT:    li a0, 63
1113; CHECK-NEXT:    vsetvli a1, zero, e64, m8, ta, ma
1114; CHECK-NEXT:    vrsub.vi v24, v16, 0
1115; CHECK-NEXT:    vand.vx v16, v16, a0
1116; CHECK-NEXT:    vand.vx v24, v24, a0
1117; CHECK-NEXT:    vsll.vv v16, v8, v16
1118; CHECK-NEXT:    vsrl.vv v8, v8, v24
1119; CHECK-NEXT:    vor.vv v8, v16, v8
1120; CHECK-NEXT:    ret
1121;
1122; CHECK-ZVKB-LABEL: vrol_vv_nxv8i64:
1123; CHECK-ZVKB:       # %bb.0:
1124; CHECK-ZVKB-NEXT:    vsetvli a0, zero, e64, m8, ta, ma
1125; CHECK-ZVKB-NEXT:    vrol.vv v8, v8, v16
1126; CHECK-ZVKB-NEXT:    ret
1127  %x = call <vscale x 8 x i64> @llvm.fshl.nxv8i64(<vscale x 8 x i64> %a, <vscale x 8 x i64> %a, <vscale x 8 x i64> %b)
1128  ret <vscale x 8 x i64> %x
1129}
1130
1131define <vscale x 8 x i64> @vrol_vx_nxv8i64(<vscale x 8 x i64> %a, i64 %b) {
1132; CHECK-RV32-LABEL: vrol_vx_nxv8i64:
1133; CHECK-RV32:       # %bb.0:
1134; CHECK-RV32-NEXT:    vsetvli a1, zero, e64, m8, ta, ma
1135; CHECK-RV32-NEXT:    vmv.v.x v16, a0
1136; CHECK-RV32-NEXT:    vsetvli zero, zero, e32, m4, ta, ma
1137; CHECK-RV32-NEXT:    vmv.v.i v24, 0
1138; CHECK-RV32-NEXT:    vwsub.vx v0, v24, a0
1139; CHECK-RV32-NEXT:    li a0, 63
1140; CHECK-RV32-NEXT:    vsetvli zero, zero, e64, m8, ta, ma
1141; CHECK-RV32-NEXT:    vand.vx v16, v16, a0
1142; CHECK-RV32-NEXT:    vand.vx v24, v0, a0
1143; CHECK-RV32-NEXT:    vsrl.vv v24, v8, v24
1144; CHECK-RV32-NEXT:    vsll.vv v8, v8, v16
1145; CHECK-RV32-NEXT:    vor.vv v8, v8, v24
1146; CHECK-RV32-NEXT:    ret
1147;
1148; CHECK-RV64-LABEL: vrol_vx_nxv8i64:
1149; CHECK-RV64:       # %bb.0:
1150; CHECK-RV64-NEXT:    andi a1, a0, 63
1151; CHECK-RV64-NEXT:    negw a0, a0
1152; CHECK-RV64-NEXT:    vsetvli a2, zero, e64, m8, ta, ma
1153; CHECK-RV64-NEXT:    vsll.vx v16, v8, a1
1154; CHECK-RV64-NEXT:    andi a0, a0, 63
1155; CHECK-RV64-NEXT:    vsrl.vx v8, v8, a0
1156; CHECK-RV64-NEXT:    vor.vv v8, v16, v8
1157; CHECK-RV64-NEXT:    ret
1158;
1159; CHECK-ZVKB-LABEL: vrol_vx_nxv8i64:
1160; CHECK-ZVKB:       # %bb.0:
1161; CHECK-ZVKB-NEXT:    vsetvli a1, zero, e64, m8, ta, ma
1162; CHECK-ZVKB-NEXT:    vrol.vx v8, v8, a0
1163; CHECK-ZVKB-NEXT:    ret
1164  %b.head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
1165  %b.splat = shufflevector <vscale x 8 x i64> %b.head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
1166  %x = call <vscale x 8 x i64> @llvm.fshl.nxv8i64(<vscale x 8 x i64> %a, <vscale x 8 x i64> %a, <vscale x 8 x i64> %b.splat)
1167  ret <vscale x 8 x i64> %x
1168}
1169