xref: /llvm-project/llvm/test/CodeGen/RISCV/rvv/vrem-sdnode.ll (revision 9122c5235ec85ce0c0ad337e862b006e7b349d84) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,RV32-V
3; RUN: llc -mtriple=riscv32 -mattr=+zve64x -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,ZVE64X
4; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,RV64-V
5; RUN: llc -mtriple=riscv64 -mattr=+zve64x -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,ZVE64X
6
7define <vscale x 1 x i8> @vrem_vv_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %vb) {
8; CHECK-LABEL: vrem_vv_nxv1i8:
9; CHECK:       # %bb.0:
10; CHECK-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
11; CHECK-NEXT:    vrem.vv v8, v8, v9
12; CHECK-NEXT:    ret
13  %vc = srem <vscale x 1 x i8> %va, %vb
14  ret <vscale x 1 x i8> %vc
15}
16
17define <vscale x 1 x i8> @vrem_vx_nxv1i8(<vscale x 1 x i8> %va, i8 signext %b) {
18; CHECK-LABEL: vrem_vx_nxv1i8:
19; CHECK:       # %bb.0:
20; CHECK-NEXT:    vsetvli a1, zero, e8, mf8, ta, ma
21; CHECK-NEXT:    vrem.vx v8, v8, a0
22; CHECK-NEXT:    ret
23  %head = insertelement <vscale x 1 x i8> poison, i8 %b, i32 0
24  %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer
25  %vc = srem <vscale x 1 x i8> %va, %splat
26  ret <vscale x 1 x i8> %vc
27}
28
29define <vscale x 1 x i8> @vrem_vi_nxv1i8_0(<vscale x 1 x i8> %va) {
30; CHECK-LABEL: vrem_vi_nxv1i8_0:
31; CHECK:       # %bb.0:
32; CHECK-NEXT:    li a0, 109
33; CHECK-NEXT:    vsetvli a1, zero, e8, mf8, ta, ma
34; CHECK-NEXT:    vmulh.vx v9, v8, a0
35; CHECK-NEXT:    vsub.vv v9, v9, v8
36; CHECK-NEXT:    vsra.vi v9, v9, 2
37; CHECK-NEXT:    vsrl.vi v10, v9, 7
38; CHECK-NEXT:    vadd.vv v9, v9, v10
39; CHECK-NEXT:    li a0, -7
40; CHECK-NEXT:    vnmsac.vx v8, a0, v9
41; CHECK-NEXT:    ret
42  %vc = srem <vscale x 1 x i8> %va, splat (i8 -7)
43  ret <vscale x 1 x i8> %vc
44}
45
46define <vscale x 1 x i8> @vrem_vv_nxv1i8_sext_twice(<vscale x 1 x i8> %va, <vscale x 1 x i8> %vb) {
47; CHECK-LABEL: vrem_vv_nxv1i8_sext_twice:
48; CHECK:       # %bb.0:
49; CHECK-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
50; CHECK-NEXT:    vrem.vv v8, v8, v9
51; CHECK-NEXT:    ret
52  %sext_va = sext <vscale x 1 x i8> %va to <vscale x 1 x i16>
53  %sext_vb = sext <vscale x 1 x i8> %vb to <vscale x 1 x i16>
54  %vc_ext = srem <vscale x 1 x i16> %sext_va, %sext_vb
55  %vc = trunc <vscale x 1 x i16> %vc_ext to <vscale x 1 x i8>
56  ret <vscale x 1 x i8> %vc
57}
58
59define <vscale x 2 x i8> @vrem_vv_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %vb) {
60; CHECK-LABEL: vrem_vv_nxv2i8:
61; CHECK:       # %bb.0:
62; CHECK-NEXT:    vsetvli a0, zero, e8, mf4, ta, ma
63; CHECK-NEXT:    vrem.vv v8, v8, v9
64; CHECK-NEXT:    ret
65  %vc = srem <vscale x 2 x i8> %va, %vb
66  ret <vscale x 2 x i8> %vc
67}
68
69define <vscale x 2 x i8> @vrem_vx_nxv2i8(<vscale x 2 x i8> %va, i8 signext %b) {
70; CHECK-LABEL: vrem_vx_nxv2i8:
71; CHECK:       # %bb.0:
72; CHECK-NEXT:    vsetvli a1, zero, e8, mf4, ta, ma
73; CHECK-NEXT:    vrem.vx v8, v8, a0
74; CHECK-NEXT:    ret
75  %head = insertelement <vscale x 2 x i8> poison, i8 %b, i32 0
76  %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> poison, <vscale x 2 x i32> zeroinitializer
77  %vc = srem <vscale x 2 x i8> %va, %splat
78  ret <vscale x 2 x i8> %vc
79}
80
81define <vscale x 2 x i8> @vrem_vi_nxv2i8_0(<vscale x 2 x i8> %va) {
82; CHECK-LABEL: vrem_vi_nxv2i8_0:
83; CHECK:       # %bb.0:
84; CHECK-NEXT:    li a0, 109
85; CHECK-NEXT:    vsetvli a1, zero, e8, mf4, ta, ma
86; CHECK-NEXT:    vmulh.vx v9, v8, a0
87; CHECK-NEXT:    vsub.vv v9, v9, v8
88; CHECK-NEXT:    vsra.vi v9, v9, 2
89; CHECK-NEXT:    vsrl.vi v10, v9, 7
90; CHECK-NEXT:    vadd.vv v9, v9, v10
91; CHECK-NEXT:    li a0, -7
92; CHECK-NEXT:    vnmsac.vx v8, a0, v9
93; CHECK-NEXT:    ret
94  %vc = srem <vscale x 2 x i8> %va, splat (i8 -7)
95  ret <vscale x 2 x i8> %vc
96}
97
98define <vscale x 2 x i8> @vrem_vv_nxv2i8_sext_twice(<vscale x 2 x i8> %va, <vscale x 2 x i8> %vb) {
99; CHECK-LABEL: vrem_vv_nxv2i8_sext_twice:
100; CHECK:       # %bb.0:
101; CHECK-NEXT:    vsetvli a0, zero, e8, mf4, ta, ma
102; CHECK-NEXT:    vrem.vv v8, v8, v9
103; CHECK-NEXT:    ret
104  %sext_va = sext <vscale x 2 x i8> %va to <vscale x 2 x i16>
105  %sext_vb = sext <vscale x 2 x i8> %vb to <vscale x 2 x i16>
106  %vc_ext = srem <vscale x 2 x i16> %sext_va, %sext_vb
107  %vc = trunc <vscale x 2 x i16> %vc_ext to <vscale x 2 x i8>
108  ret <vscale x 2 x i8> %vc
109}
110
111define <vscale x 4 x i8> @vrem_vv_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %vb) {
112; CHECK-LABEL: vrem_vv_nxv4i8:
113; CHECK:       # %bb.0:
114; CHECK-NEXT:    vsetvli a0, zero, e8, mf2, ta, ma
115; CHECK-NEXT:    vrem.vv v8, v8, v9
116; CHECK-NEXT:    ret
117  %vc = srem <vscale x 4 x i8> %va, %vb
118  ret <vscale x 4 x i8> %vc
119}
120
121define <vscale x 4 x i8> @vrem_vx_nxv4i8(<vscale x 4 x i8> %va, i8 signext %b) {
122; CHECK-LABEL: vrem_vx_nxv4i8:
123; CHECK:       # %bb.0:
124; CHECK-NEXT:    vsetvli a1, zero, e8, mf2, ta, ma
125; CHECK-NEXT:    vrem.vx v8, v8, a0
126; CHECK-NEXT:    ret
127  %head = insertelement <vscale x 4 x i8> poison, i8 %b, i32 0
128  %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> poison, <vscale x 4 x i32> zeroinitializer
129  %vc = srem <vscale x 4 x i8> %va, %splat
130  ret <vscale x 4 x i8> %vc
131}
132
133define <vscale x 4 x i8> @vrem_vi_nxv4i8_0(<vscale x 4 x i8> %va) {
134; CHECK-LABEL: vrem_vi_nxv4i8_0:
135; CHECK:       # %bb.0:
136; CHECK-NEXT:    li a0, 109
137; CHECK-NEXT:    vsetvli a1, zero, e8, mf2, ta, ma
138; CHECK-NEXT:    vmulh.vx v9, v8, a0
139; CHECK-NEXT:    vsub.vv v9, v9, v8
140; CHECK-NEXT:    vsra.vi v9, v9, 2
141; CHECK-NEXT:    vsrl.vi v10, v9, 7
142; CHECK-NEXT:    vadd.vv v9, v9, v10
143; CHECK-NEXT:    li a0, -7
144; CHECK-NEXT:    vnmsac.vx v8, a0, v9
145; CHECK-NEXT:    ret
146  %vc = srem <vscale x 4 x i8> %va, splat (i8 -7)
147  ret <vscale x 4 x i8> %vc
148}
149
150define <vscale x 4 x i8> @vrem_vv_nxv4i8_sext_twice(<vscale x 4 x i8> %va, <vscale x 4 x i8> %vb) {
151; CHECK-LABEL: vrem_vv_nxv4i8_sext_twice:
152; CHECK:       # %bb.0:
153; CHECK-NEXT:    vsetvli a0, zero, e8, mf2, ta, ma
154; CHECK-NEXT:    vrem.vv v8, v8, v9
155; CHECK-NEXT:    ret
156  %sext_va = sext <vscale x 4 x i8> %va to <vscale x 4 x i16>
157  %sext_vb = sext <vscale x 4 x i8> %vb to <vscale x 4 x i16>
158  %vc_ext = srem <vscale x 4 x i16> %sext_va, %sext_vb
159  %vc = trunc <vscale x 4 x i16> %vc_ext to <vscale x 4 x i8>
160  ret <vscale x 4 x i8> %vc
161}
162
163define <vscale x 8 x i8> @vrem_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) {
164; CHECK-LABEL: vrem_vv_nxv8i8:
165; CHECK:       # %bb.0:
166; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, ma
167; CHECK-NEXT:    vrem.vv v8, v8, v9
168; CHECK-NEXT:    ret
169  %vc = srem <vscale x 8 x i8> %va, %vb
170  ret <vscale x 8 x i8> %vc
171}
172
173define <vscale x 8 x i8> @vrem_vx_nxv8i8(<vscale x 8 x i8> %va, i8 signext %b) {
174; CHECK-LABEL: vrem_vx_nxv8i8:
175; CHECK:       # %bb.0:
176; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, ma
177; CHECK-NEXT:    vrem.vx v8, v8, a0
178; CHECK-NEXT:    ret
179  %head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0
180  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
181  %vc = srem <vscale x 8 x i8> %va, %splat
182  ret <vscale x 8 x i8> %vc
183}
184
185define <vscale x 8 x i8> @vrem_vi_nxv8i8_0(<vscale x 8 x i8> %va) {
186; CHECK-LABEL: vrem_vi_nxv8i8_0:
187; CHECK:       # %bb.0:
188; CHECK-NEXT:    li a0, 109
189; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, ma
190; CHECK-NEXT:    vmulh.vx v9, v8, a0
191; CHECK-NEXT:    vsub.vv v9, v9, v8
192; CHECK-NEXT:    vsra.vi v9, v9, 2
193; CHECK-NEXT:    vsrl.vi v10, v9, 7
194; CHECK-NEXT:    vadd.vv v9, v9, v10
195; CHECK-NEXT:    li a0, -7
196; CHECK-NEXT:    vnmsac.vx v8, a0, v9
197; CHECK-NEXT:    ret
198  %vc = srem <vscale x 8 x i8> %va, splat (i8 -7)
199  ret <vscale x 8 x i8> %vc
200}
201
202define <vscale x 8 x i8> @vrem_vv_nxv8i8_sext_twice(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) {
203; CHECK-LABEL: vrem_vv_nxv8i8_sext_twice:
204; CHECK:       # %bb.0:
205; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, ma
206; CHECK-NEXT:    vrem.vv v8, v8, v9
207; CHECK-NEXT:    ret
208  %sext_va = sext <vscale x 8 x i8> %va to <vscale x 8 x i16>
209  %sext_vb = sext <vscale x 8 x i8> %vb to <vscale x 8 x i16>
210  %vc_ext = srem <vscale x 8 x i16> %sext_va, %sext_vb
211  %vc = trunc <vscale x 8 x i16> %vc_ext to <vscale x 8 x i8>
212  ret <vscale x 8 x i8> %vc
213}
214
215define <vscale x 16 x i8> @vrem_vv_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %vb) {
216; CHECK-LABEL: vrem_vv_nxv16i8:
217; CHECK:       # %bb.0:
218; CHECK-NEXT:    vsetvli a0, zero, e8, m2, ta, ma
219; CHECK-NEXT:    vrem.vv v8, v8, v10
220; CHECK-NEXT:    ret
221  %vc = srem <vscale x 16 x i8> %va, %vb
222  ret <vscale x 16 x i8> %vc
223}
224
225define <vscale x 16 x i8> @vrem_vx_nxv16i8(<vscale x 16 x i8> %va, i8 signext %b) {
226; CHECK-LABEL: vrem_vx_nxv16i8:
227; CHECK:       # %bb.0:
228; CHECK-NEXT:    vsetvli a1, zero, e8, m2, ta, ma
229; CHECK-NEXT:    vrem.vx v8, v8, a0
230; CHECK-NEXT:    ret
231  %head = insertelement <vscale x 16 x i8> poison, i8 %b, i32 0
232  %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
233  %vc = srem <vscale x 16 x i8> %va, %splat
234  ret <vscale x 16 x i8> %vc
235}
236
237define <vscale x 16 x i8> @vrem_vi_nxv16i8_0(<vscale x 16 x i8> %va) {
238; CHECK-LABEL: vrem_vi_nxv16i8_0:
239; CHECK:       # %bb.0:
240; CHECK-NEXT:    li a0, 109
241; CHECK-NEXT:    vsetvli a1, zero, e8, m2, ta, ma
242; CHECK-NEXT:    vmulh.vx v10, v8, a0
243; CHECK-NEXT:    vsub.vv v10, v10, v8
244; CHECK-NEXT:    vsra.vi v10, v10, 2
245; CHECK-NEXT:    vsrl.vi v12, v10, 7
246; CHECK-NEXT:    vadd.vv v10, v10, v12
247; CHECK-NEXT:    li a0, -7
248; CHECK-NEXT:    vnmsac.vx v8, a0, v10
249; CHECK-NEXT:    ret
250  %vc = srem <vscale x 16 x i8> %va, splat (i8 -7)
251  ret <vscale x 16 x i8> %vc
252}
253
254define <vscale x 16 x i8> @vrem_vv_nxv16i8_sext_twice(<vscale x 16 x i8> %va, <vscale x 16 x i8> %vb) {
255; CHECK-LABEL: vrem_vv_nxv16i8_sext_twice:
256; CHECK:       # %bb.0:
257; CHECK-NEXT:    vsetvli a0, zero, e8, m2, ta, ma
258; CHECK-NEXT:    vrem.vv v8, v8, v10
259; CHECK-NEXT:    ret
260  %sext_va = sext <vscale x 16 x i8> %va to <vscale x 16 x i16>
261  %sext_vb = sext <vscale x 16 x i8> %vb to <vscale x 16 x i16>
262  %vc_ext = srem <vscale x 16 x i16> %sext_va, %sext_vb
263  %vc = trunc <vscale x 16 x i16> %vc_ext to <vscale x 16 x i8>
264  ret <vscale x 16 x i8> %vc
265}
266
267define <vscale x 32 x i8> @vrem_vv_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %vb) {
268; CHECK-LABEL: vrem_vv_nxv32i8:
269; CHECK:       # %bb.0:
270; CHECK-NEXT:    vsetvli a0, zero, e8, m4, ta, ma
271; CHECK-NEXT:    vrem.vv v8, v8, v12
272; CHECK-NEXT:    ret
273  %vc = srem <vscale x 32 x i8> %va, %vb
274  ret <vscale x 32 x i8> %vc
275}
276
277define <vscale x 32 x i8> @vrem_vx_nxv32i8(<vscale x 32 x i8> %va, i8 signext %b) {
278; CHECK-LABEL: vrem_vx_nxv32i8:
279; CHECK:       # %bb.0:
280; CHECK-NEXT:    vsetvli a1, zero, e8, m4, ta, ma
281; CHECK-NEXT:    vrem.vx v8, v8, a0
282; CHECK-NEXT:    ret
283  %head = insertelement <vscale x 32 x i8> poison, i8 %b, i32 0
284  %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> poison, <vscale x 32 x i32> zeroinitializer
285  %vc = srem <vscale x 32 x i8> %va, %splat
286  ret <vscale x 32 x i8> %vc
287}
288
289define <vscale x 32 x i8> @vrem_vi_nxv32i8_0(<vscale x 32 x i8> %va) {
290; CHECK-LABEL: vrem_vi_nxv32i8_0:
291; CHECK:       # %bb.0:
292; CHECK-NEXT:    li a0, 109
293; CHECK-NEXT:    vsetvli a1, zero, e8, m4, ta, ma
294; CHECK-NEXT:    vmulh.vx v12, v8, a0
295; CHECK-NEXT:    vsub.vv v12, v12, v8
296; CHECK-NEXT:    vsra.vi v12, v12, 2
297; CHECK-NEXT:    vsrl.vi v16, v12, 7
298; CHECK-NEXT:    vadd.vv v12, v12, v16
299; CHECK-NEXT:    li a0, -7
300; CHECK-NEXT:    vnmsac.vx v8, a0, v12
301; CHECK-NEXT:    ret
302  %vc = srem <vscale x 32 x i8> %va, splat (i8 -7)
303  ret <vscale x 32 x i8> %vc
304}
305
306define <vscale x 32 x i8> @vrem_vv_nxv32i8_sext_twice(<vscale x 32 x i8> %va, <vscale x 32 x i8> %vb) {
307; CHECK-LABEL: vrem_vv_nxv32i8_sext_twice:
308; CHECK:       # %bb.0:
309; CHECK-NEXT:    vsetvli a0, zero, e8, m4, ta, ma
310; CHECK-NEXT:    vrem.vv v8, v8, v12
311; CHECK-NEXT:    ret
312  %sext_va = sext <vscale x 32 x i8> %va to <vscale x 32 x i16>
313  %sext_vb = sext <vscale x 32 x i8> %vb to <vscale x 32 x i16>
314  %vc_ext = srem <vscale x 32 x i16> %sext_va, %sext_vb
315  %vc = trunc <vscale x 32 x i16> %vc_ext to <vscale x 32 x i8>
316  ret <vscale x 32 x i8> %vc
317}
318
319define <vscale x 64 x i8> @vrem_vv_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %vb) {
320; CHECK-LABEL: vrem_vv_nxv64i8:
321; CHECK:       # %bb.0:
322; CHECK-NEXT:    vsetvli a0, zero, e8, m8, ta, ma
323; CHECK-NEXT:    vrem.vv v8, v8, v16
324; CHECK-NEXT:    ret
325  %vc = srem <vscale x 64 x i8> %va, %vb
326  ret <vscale x 64 x i8> %vc
327}
328
329define <vscale x 64 x i8> @vrem_vx_nxv64i8(<vscale x 64 x i8> %va, i8 signext %b) {
330; CHECK-LABEL: vrem_vx_nxv64i8:
331; CHECK:       # %bb.0:
332; CHECK-NEXT:    vsetvli a1, zero, e8, m8, ta, ma
333; CHECK-NEXT:    vrem.vx v8, v8, a0
334; CHECK-NEXT:    ret
335  %head = insertelement <vscale x 64 x i8> poison, i8 %b, i32 0
336  %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> poison, <vscale x 64 x i32> zeroinitializer
337  %vc = srem <vscale x 64 x i8> %va, %splat
338  ret <vscale x 64 x i8> %vc
339}
340
341define <vscale x 64 x i8> @vrem_vi_nxv64i8_0(<vscale x 64 x i8> %va) {
342; CHECK-LABEL: vrem_vi_nxv64i8_0:
343; CHECK:       # %bb.0:
344; CHECK-NEXT:    li a0, 109
345; CHECK-NEXT:    vsetvli a1, zero, e8, m8, ta, ma
346; CHECK-NEXT:    vmulh.vx v16, v8, a0
347; CHECK-NEXT:    vsub.vv v16, v16, v8
348; CHECK-NEXT:    vsra.vi v16, v16, 2
349; CHECK-NEXT:    vsrl.vi v24, v16, 7
350; CHECK-NEXT:    vadd.vv v16, v16, v24
351; CHECK-NEXT:    li a0, -7
352; CHECK-NEXT:    vnmsac.vx v8, a0, v16
353; CHECK-NEXT:    ret
354  %vc = srem <vscale x 64 x i8> %va, splat (i8 -7)
355  ret <vscale x 64 x i8> %vc
356}
357
358define <vscale x 1 x i16> @vrem_vv_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %vb) {
359; CHECK-LABEL: vrem_vv_nxv1i16:
360; CHECK:       # %bb.0:
361; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, ma
362; CHECK-NEXT:    vrem.vv v8, v8, v9
363; CHECK-NEXT:    ret
364  %vc = srem <vscale x 1 x i16> %va, %vb
365  ret <vscale x 1 x i16> %vc
366}
367
368define <vscale x 1 x i16> @vrem_vx_nxv1i16(<vscale x 1 x i16> %va, i16 signext %b) {
369; CHECK-LABEL: vrem_vx_nxv1i16:
370; CHECK:       # %bb.0:
371; CHECK-NEXT:    vsetvli a1, zero, e16, mf4, ta, ma
372; CHECK-NEXT:    vrem.vx v8, v8, a0
373; CHECK-NEXT:    ret
374  %head = insertelement <vscale x 1 x i16> poison, i16 %b, i32 0
375  %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer
376  %vc = srem <vscale x 1 x i16> %va, %splat
377  ret <vscale x 1 x i16> %vc
378}
379
380define <vscale x 1 x i16> @vrem_vi_nxv1i16_0(<vscale x 1 x i16> %va) {
381; CHECK-LABEL: vrem_vi_nxv1i16_0:
382; CHECK:       # %bb.0:
383; CHECK-NEXT:    lui a0, 1048571
384; CHECK-NEXT:    addi a0, a0, 1755
385; CHECK-NEXT:    vsetvli a1, zero, e16, mf4, ta, ma
386; CHECK-NEXT:    vmulh.vx v9, v8, a0
387; CHECK-NEXT:    vsra.vi v9, v9, 1
388; CHECK-NEXT:    vsrl.vi v10, v9, 15
389; CHECK-NEXT:    vadd.vv v9, v9, v10
390; CHECK-NEXT:    li a0, -7
391; CHECK-NEXT:    vnmsac.vx v8, a0, v9
392; CHECK-NEXT:    ret
393  %vc = srem <vscale x 1 x i16> %va, splat (i16 -7)
394  ret <vscale x 1 x i16> %vc
395}
396
397define <vscale x 1 x i16> @vrem_vv_nxv1i16_sext_twice(<vscale x 1 x i16> %va, <vscale x 1 x i16> %vb) {
398; CHECK-LABEL: vrem_vv_nxv1i16_sext_twice:
399; CHECK:       # %bb.0:
400; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, ma
401; CHECK-NEXT:    vrem.vv v8, v8, v9
402; CHECK-NEXT:    ret
403  %sext_va = sext <vscale x 1 x i16> %va to <vscale x 1 x i32>
404  %sext_vb = sext <vscale x 1 x i16> %vb to <vscale x 1 x i32>
405  %vc_ext = srem <vscale x 1 x i32> %sext_va, %sext_vb
406  %vc = trunc <vscale x 1 x i32> %vc_ext to <vscale x 1 x i16>
407  ret <vscale x 1 x i16> %vc
408}
409
410define <vscale x 2 x i16> @vrem_vv_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %vb) {
411; CHECK-LABEL: vrem_vv_nxv2i16:
412; CHECK:       # %bb.0:
413; CHECK-NEXT:    vsetvli a0, zero, e16, mf2, ta, ma
414; CHECK-NEXT:    vrem.vv v8, v8, v9
415; CHECK-NEXT:    ret
416  %vc = srem <vscale x 2 x i16> %va, %vb
417  ret <vscale x 2 x i16> %vc
418}
419
420define <vscale x 2 x i16> @vrem_vx_nxv2i16(<vscale x 2 x i16> %va, i16 signext %b) {
421; CHECK-LABEL: vrem_vx_nxv2i16:
422; CHECK:       # %bb.0:
423; CHECK-NEXT:    vsetvli a1, zero, e16, mf2, ta, ma
424; CHECK-NEXT:    vrem.vx v8, v8, a0
425; CHECK-NEXT:    ret
426  %head = insertelement <vscale x 2 x i16> poison, i16 %b, i32 0
427  %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer
428  %vc = srem <vscale x 2 x i16> %va, %splat
429  ret <vscale x 2 x i16> %vc
430}
431
432define <vscale x 2 x i16> @vrem_vi_nxv2i16_0(<vscale x 2 x i16> %va) {
433; CHECK-LABEL: vrem_vi_nxv2i16_0:
434; CHECK:       # %bb.0:
435; CHECK-NEXT:    lui a0, 1048571
436; CHECK-NEXT:    addi a0, a0, 1755
437; CHECK-NEXT:    vsetvli a1, zero, e16, mf2, ta, ma
438; CHECK-NEXT:    vmulh.vx v9, v8, a0
439; CHECK-NEXT:    vsra.vi v9, v9, 1
440; CHECK-NEXT:    vsrl.vi v10, v9, 15
441; CHECK-NEXT:    vadd.vv v9, v9, v10
442; CHECK-NEXT:    li a0, -7
443; CHECK-NEXT:    vnmsac.vx v8, a0, v9
444; CHECK-NEXT:    ret
445  %vc = srem <vscale x 2 x i16> %va, splat (i16 -7)
446  ret <vscale x 2 x i16> %vc
447}
448
449define <vscale x 2 x i16> @vrem_vv_nxv2i16_sext_twice(<vscale x 2 x i16> %va, <vscale x 2 x i16> %vb) {
450; CHECK-LABEL: vrem_vv_nxv2i16_sext_twice:
451; CHECK:       # %bb.0:
452; CHECK-NEXT:    vsetvli a0, zero, e16, mf2, ta, ma
453; CHECK-NEXT:    vrem.vv v8, v8, v9
454; CHECK-NEXT:    ret
455  %sext_va = sext <vscale x 2 x i16> %va to <vscale x 2 x i32>
456  %sext_vb = sext <vscale x 2 x i16> %vb to <vscale x 2 x i32>
457  %vc_ext = srem <vscale x 2 x i32> %sext_va, %sext_vb
458  %vc = trunc <vscale x 2 x i32> %vc_ext to <vscale x 2 x i16>
459  ret <vscale x 2 x i16> %vc
460}
461
462define <vscale x 4 x i16> @vrem_vv_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %vb) {
463; CHECK-LABEL: vrem_vv_nxv4i16:
464; CHECK:       # %bb.0:
465; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, ma
466; CHECK-NEXT:    vrem.vv v8, v8, v9
467; CHECK-NEXT:    ret
468  %vc = srem <vscale x 4 x i16> %va, %vb
469  ret <vscale x 4 x i16> %vc
470}
471
472define <vscale x 4 x i16> @vrem_vx_nxv4i16(<vscale x 4 x i16> %va, i16 signext %b) {
473; CHECK-LABEL: vrem_vx_nxv4i16:
474; CHECK:       # %bb.0:
475; CHECK-NEXT:    vsetvli a1, zero, e16, m1, ta, ma
476; CHECK-NEXT:    vrem.vx v8, v8, a0
477; CHECK-NEXT:    ret
478  %head = insertelement <vscale x 4 x i16> poison, i16 %b, i32 0
479  %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> poison, <vscale x 4 x i32> zeroinitializer
480  %vc = srem <vscale x 4 x i16> %va, %splat
481  ret <vscale x 4 x i16> %vc
482}
483
484define <vscale x 4 x i16> @vrem_vi_nxv4i16_0(<vscale x 4 x i16> %va) {
485; CHECK-LABEL: vrem_vi_nxv4i16_0:
486; CHECK:       # %bb.0:
487; CHECK-NEXT:    lui a0, 1048571
488; CHECK-NEXT:    addi a0, a0, 1755
489; CHECK-NEXT:    vsetvli a1, zero, e16, m1, ta, ma
490; CHECK-NEXT:    vmulh.vx v9, v8, a0
491; CHECK-NEXT:    vsra.vi v9, v9, 1
492; CHECK-NEXT:    vsrl.vi v10, v9, 15
493; CHECK-NEXT:    vadd.vv v9, v9, v10
494; CHECK-NEXT:    li a0, -7
495; CHECK-NEXT:    vnmsac.vx v8, a0, v9
496; CHECK-NEXT:    ret
497  %vc = srem <vscale x 4 x i16> %va, splat (i16 -7)
498  ret <vscale x 4 x i16> %vc
499}
500
501define <vscale x 4 x i16> @vrem_vv_nxv4i16_sext_twice(<vscale x 4 x i16> %va, <vscale x 4 x i16> %vb) {
502; CHECK-LABEL: vrem_vv_nxv4i16_sext_twice:
503; CHECK:       # %bb.0:
504; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, ma
505; CHECK-NEXT:    vrem.vv v8, v8, v9
506; CHECK-NEXT:    ret
507  %sext_va = sext <vscale x 4 x i16> %va to <vscale x 4 x i32>
508  %sext_vb = sext <vscale x 4 x i16> %vb to <vscale x 4 x i32>
509  %vc_ext = srem <vscale x 4 x i32> %sext_va, %sext_vb
510  %vc = trunc <vscale x 4 x i32> %vc_ext to <vscale x 4 x i16>
511  ret <vscale x 4 x i16> %vc
512}
513
514define <vscale x 8 x i16> @vrem_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) {
515; CHECK-LABEL: vrem_vv_nxv8i16:
516; CHECK:       # %bb.0:
517; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, ma
518; CHECK-NEXT:    vrem.vv v8, v8, v10
519; CHECK-NEXT:    ret
520  %vc = srem <vscale x 8 x i16> %va, %vb
521  ret <vscale x 8 x i16> %vc
522}
523
524define <vscale x 8 x i16> @vrem_vx_nxv8i16(<vscale x 8 x i16> %va, i16 signext %b) {
525; CHECK-LABEL: vrem_vx_nxv8i16:
526; CHECK:       # %bb.0:
527; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, ma
528; CHECK-NEXT:    vrem.vx v8, v8, a0
529; CHECK-NEXT:    ret
530  %head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0
531  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
532  %vc = srem <vscale x 8 x i16> %va, %splat
533  ret <vscale x 8 x i16> %vc
534}
535
536define <vscale x 8 x i16> @vrem_vi_nxv8i16_0(<vscale x 8 x i16> %va) {
537; CHECK-LABEL: vrem_vi_nxv8i16_0:
538; CHECK:       # %bb.0:
539; CHECK-NEXT:    lui a0, 1048571
540; CHECK-NEXT:    addi a0, a0, 1755
541; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, ma
542; CHECK-NEXT:    vmulh.vx v10, v8, a0
543; CHECK-NEXT:    vsra.vi v10, v10, 1
544; CHECK-NEXT:    vsrl.vi v12, v10, 15
545; CHECK-NEXT:    vadd.vv v10, v10, v12
546; CHECK-NEXT:    li a0, -7
547; CHECK-NEXT:    vnmsac.vx v8, a0, v10
548; CHECK-NEXT:    ret
549  %vc = srem <vscale x 8 x i16> %va, splat (i16 -7)
550  ret <vscale x 8 x i16> %vc
551}
552
553define <vscale x 8 x i16> @vrem_vv_nxv8i16_sext_twice(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) {
554; CHECK-LABEL: vrem_vv_nxv8i16_sext_twice:
555; CHECK:       # %bb.0:
556; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, ma
557; CHECK-NEXT:    vrem.vv v8, v8, v10
558; CHECK-NEXT:    ret
559  %sext_va = sext <vscale x 8 x i16> %va to <vscale x 8 x i32>
560  %sext_vb = sext <vscale x 8 x i16> %vb to <vscale x 8 x i32>
561  %vc_ext = srem <vscale x 8 x i32> %sext_va, %sext_vb
562  %vc = trunc <vscale x 8 x i32> %vc_ext to <vscale x 8 x i16>
563  ret <vscale x 8 x i16> %vc
564}
565
566define <vscale x 16 x i16> @vrem_vv_nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %vb) {
567; CHECK-LABEL: vrem_vv_nxv16i16:
568; CHECK:       # %bb.0:
569; CHECK-NEXT:    vsetvli a0, zero, e16, m4, ta, ma
570; CHECK-NEXT:    vrem.vv v8, v8, v12
571; CHECK-NEXT:    ret
572  %vc = srem <vscale x 16 x i16> %va, %vb
573  ret <vscale x 16 x i16> %vc
574}
575
576define <vscale x 16 x i16> @vrem_vx_nxv16i16(<vscale x 16 x i16> %va, i16 signext %b) {
577; CHECK-LABEL: vrem_vx_nxv16i16:
578; CHECK:       # %bb.0:
579; CHECK-NEXT:    vsetvli a1, zero, e16, m4, ta, ma
580; CHECK-NEXT:    vrem.vx v8, v8, a0
581; CHECK-NEXT:    ret
582  %head = insertelement <vscale x 16 x i16> poison, i16 %b, i32 0
583  %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> poison, <vscale x 16 x i32> zeroinitializer
584  %vc = srem <vscale x 16 x i16> %va, %splat
585  ret <vscale x 16 x i16> %vc
586}
587
588define <vscale x 16 x i16> @vrem_vi_nxv16i16_0(<vscale x 16 x i16> %va) {
589; CHECK-LABEL: vrem_vi_nxv16i16_0:
590; CHECK:       # %bb.0:
591; CHECK-NEXT:    lui a0, 1048571
592; CHECK-NEXT:    addi a0, a0, 1755
593; CHECK-NEXT:    vsetvli a1, zero, e16, m4, ta, ma
594; CHECK-NEXT:    vmulh.vx v12, v8, a0
595; CHECK-NEXT:    vsra.vi v12, v12, 1
596; CHECK-NEXT:    vsrl.vi v16, v12, 15
597; CHECK-NEXT:    vadd.vv v12, v12, v16
598; CHECK-NEXT:    li a0, -7
599; CHECK-NEXT:    vnmsac.vx v8, a0, v12
600; CHECK-NEXT:    ret
601  %vc = srem <vscale x 16 x i16> %va, splat (i16 -7)
602  ret <vscale x 16 x i16> %vc
603}
604
605define <vscale x 16 x i16> @vrem_vv_nxv16i16_sext_twice(<vscale x 16 x i16> %va, <vscale x 16 x i16> %vb) {
606; CHECK-LABEL: vrem_vv_nxv16i16_sext_twice:
607; CHECK:       # %bb.0:
608; CHECK-NEXT:    vsetvli a0, zero, e16, m4, ta, ma
609; CHECK-NEXT:    vrem.vv v8, v8, v12
610; CHECK-NEXT:    ret
611  %sext_va = sext <vscale x 16 x i16> %va to <vscale x 16 x i32>
612  %sext_vb = sext <vscale x 16 x i16> %vb to <vscale x 16 x i32>
613  %vc_ext = srem <vscale x 16 x i32> %sext_va, %sext_vb
614  %vc = trunc <vscale x 16 x i32> %vc_ext to <vscale x 16 x i16>
615  ret <vscale x 16 x i16> %vc
616}
617
618define <vscale x 32 x i16> @vrem_vv_nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %vb) {
619; CHECK-LABEL: vrem_vv_nxv32i16:
620; CHECK:       # %bb.0:
621; CHECK-NEXT:    vsetvli a0, zero, e16, m8, ta, ma
622; CHECK-NEXT:    vrem.vv v8, v8, v16
623; CHECK-NEXT:    ret
624  %vc = srem <vscale x 32 x i16> %va, %vb
625  ret <vscale x 32 x i16> %vc
626}
627
628define <vscale x 32 x i16> @vrem_vx_nxv32i16(<vscale x 32 x i16> %va, i16 signext %b) {
629; CHECK-LABEL: vrem_vx_nxv32i16:
630; CHECK:       # %bb.0:
631; CHECK-NEXT:    vsetvli a1, zero, e16, m8, ta, ma
632; CHECK-NEXT:    vrem.vx v8, v8, a0
633; CHECK-NEXT:    ret
634  %head = insertelement <vscale x 32 x i16> poison, i16 %b, i32 0
635  %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> poison, <vscale x 32 x i32> zeroinitializer
636  %vc = srem <vscale x 32 x i16> %va, %splat
637  ret <vscale x 32 x i16> %vc
638}
639
640define <vscale x 32 x i16> @vrem_vi_nxv32i16_0(<vscale x 32 x i16> %va) {
641; CHECK-LABEL: vrem_vi_nxv32i16_0:
642; CHECK:       # %bb.0:
643; CHECK-NEXT:    lui a0, 1048571
644; CHECK-NEXT:    addi a0, a0, 1755
645; CHECK-NEXT:    vsetvli a1, zero, e16, m8, ta, ma
646; CHECK-NEXT:    vmulh.vx v16, v8, a0
647; CHECK-NEXT:    vsra.vi v16, v16, 1
648; CHECK-NEXT:    vsrl.vi v24, v16, 15
649; CHECK-NEXT:    vadd.vv v16, v16, v24
650; CHECK-NEXT:    li a0, -7
651; CHECK-NEXT:    vnmsac.vx v8, a0, v16
652; CHECK-NEXT:    ret
653  %vc = srem <vscale x 32 x i16> %va, splat (i16 -7)
654  ret <vscale x 32 x i16> %vc
655}
656
657define <vscale x 1 x i32> @vrem_vv_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb) {
658; CHECK-LABEL: vrem_vv_nxv1i32:
659; CHECK:       # %bb.0:
660; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, ma
661; CHECK-NEXT:    vrem.vv v8, v8, v9
662; CHECK-NEXT:    ret
663  %vc = srem <vscale x 1 x i32> %va, %vb
664  ret <vscale x 1 x i32> %vc
665}
666
667define <vscale x 1 x i32> @vrem_vx_nxv1i32(<vscale x 1 x i32> %va, i32 signext %b) {
668; CHECK-LABEL: vrem_vx_nxv1i32:
669; CHECK:       # %bb.0:
670; CHECK-NEXT:    vsetvli a1, zero, e32, mf2, ta, ma
671; CHECK-NEXT:    vrem.vx v8, v8, a0
672; CHECK-NEXT:    ret
673  %head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 0
674  %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer
675  %vc = srem <vscale x 1 x i32> %va, %splat
676  ret <vscale x 1 x i32> %vc
677}
678
679define <vscale x 1 x i32> @vrem_vi_nxv1i32_0(<vscale x 1 x i32> %va) {
680; RV32-LABEL: vrem_vi_nxv1i32_0:
681; RV32:       # %bb.0:
682; RV32-NEXT:    lui a0, 449390
683; RV32-NEXT:    addi a0, a0, -1171
684; RV32-NEXT:    vsetvli a1, zero, e32, mf2, ta, ma
685; RV32-NEXT:    vmulh.vx v9, v8, a0
686; RV32-NEXT:    vsub.vv v9, v9, v8
687; RV32-NEXT:    vsrl.vi v10, v9, 31
688; RV32-NEXT:    vsra.vi v9, v9, 2
689; RV32-NEXT:    vadd.vv v9, v9, v10
690; RV32-NEXT:    li a0, -7
691; RV32-NEXT:    vnmsac.vx v8, a0, v9
692; RV32-NEXT:    ret
693;
694; RV64-LABEL: vrem_vi_nxv1i32_0:
695; RV64:       # %bb.0:
696; RV64-NEXT:    lui a0, 449390
697; RV64-NEXT:    addi a0, a0, -1171
698; RV64-NEXT:    vsetvli a1, zero, e32, mf2, ta, ma
699; RV64-NEXT:    vmulh.vx v9, v8, a0
700; RV64-NEXT:    vsub.vv v9, v9, v8
701; RV64-NEXT:    vsra.vi v9, v9, 2
702; RV64-NEXT:    vsrl.vi v10, v9, 31
703; RV64-NEXT:    vadd.vv v9, v9, v10
704; RV64-NEXT:    li a0, -7
705; RV64-NEXT:    vnmsac.vx v8, a0, v9
706; RV64-NEXT:    ret
707  %vc = srem <vscale x 1 x i32> %va, splat (i32 -7)
708  ret <vscale x 1 x i32> %vc
709}
710
711define <vscale x 2 x i32> @vrem_vv_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb) {
712; CHECK-LABEL: vrem_vv_nxv2i32:
713; CHECK:       # %bb.0:
714; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, ma
715; CHECK-NEXT:    vrem.vv v8, v8, v9
716; CHECK-NEXT:    ret
717  %vc = srem <vscale x 2 x i32> %va, %vb
718  ret <vscale x 2 x i32> %vc
719}
720
721define <vscale x 2 x i32> @vrem_vx_nxv2i32(<vscale x 2 x i32> %va, i32 signext %b) {
722; CHECK-LABEL: vrem_vx_nxv2i32:
723; CHECK:       # %bb.0:
724; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, ma
725; CHECK-NEXT:    vrem.vx v8, v8, a0
726; CHECK-NEXT:    ret
727  %head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0
728  %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer
729  %vc = srem <vscale x 2 x i32> %va, %splat
730  ret <vscale x 2 x i32> %vc
731}
732
733define <vscale x 2 x i32> @vrem_vi_nxv2i32_0(<vscale x 2 x i32> %va) {
734; RV32-LABEL: vrem_vi_nxv2i32_0:
735; RV32:       # %bb.0:
736; RV32-NEXT:    lui a0, 449390
737; RV32-NEXT:    addi a0, a0, -1171
738; RV32-NEXT:    vsetvli a1, zero, e32, m1, ta, ma
739; RV32-NEXT:    vmulh.vx v9, v8, a0
740; RV32-NEXT:    vsub.vv v9, v9, v8
741; RV32-NEXT:    vsrl.vi v10, v9, 31
742; RV32-NEXT:    vsra.vi v9, v9, 2
743; RV32-NEXT:    vadd.vv v9, v9, v10
744; RV32-NEXT:    li a0, -7
745; RV32-NEXT:    vnmsac.vx v8, a0, v9
746; RV32-NEXT:    ret
747;
748; RV64-LABEL: vrem_vi_nxv2i32_0:
749; RV64:       # %bb.0:
750; RV64-NEXT:    lui a0, 449390
751; RV64-NEXT:    addi a0, a0, -1171
752; RV64-NEXT:    vsetvli a1, zero, e32, m1, ta, ma
753; RV64-NEXT:    vmulh.vx v9, v8, a0
754; RV64-NEXT:    vsub.vv v9, v9, v8
755; RV64-NEXT:    vsra.vi v9, v9, 2
756; RV64-NEXT:    vsrl.vi v10, v9, 31
757; RV64-NEXT:    vadd.vv v9, v9, v10
758; RV64-NEXT:    li a0, -7
759; RV64-NEXT:    vnmsac.vx v8, a0, v9
760; RV64-NEXT:    ret
761  %vc = srem <vscale x 2 x i32> %va, splat (i32 -7)
762  ret <vscale x 2 x i32> %vc
763}
764
765define <vscale x 4 x i32> @vrem_vv_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb) {
766; CHECK-LABEL: vrem_vv_nxv4i32:
767; CHECK:       # %bb.0:
768; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, ma
769; CHECK-NEXT:    vrem.vv v8, v8, v10
770; CHECK-NEXT:    ret
771  %vc = srem <vscale x 4 x i32> %va, %vb
772  ret <vscale x 4 x i32> %vc
773}
774
775define <vscale x 4 x i32> @vrem_vx_nxv4i32(<vscale x 4 x i32> %va, i32 signext %b) {
776; CHECK-LABEL: vrem_vx_nxv4i32:
777; CHECK:       # %bb.0:
778; CHECK-NEXT:    vsetvli a1, zero, e32, m2, ta, ma
779; CHECK-NEXT:    vrem.vx v8, v8, a0
780; CHECK-NEXT:    ret
781  %head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0
782  %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
783  %vc = srem <vscale x 4 x i32> %va, %splat
784  ret <vscale x 4 x i32> %vc
785}
786
787define <vscale x 4 x i32> @vrem_vi_nxv4i32_0(<vscale x 4 x i32> %va) {
788; RV32-LABEL: vrem_vi_nxv4i32_0:
789; RV32:       # %bb.0:
790; RV32-NEXT:    lui a0, 449390
791; RV32-NEXT:    addi a0, a0, -1171
792; RV32-NEXT:    vsetvli a1, zero, e32, m2, ta, ma
793; RV32-NEXT:    vmulh.vx v10, v8, a0
794; RV32-NEXT:    vsub.vv v10, v10, v8
795; RV32-NEXT:    vsrl.vi v12, v10, 31
796; RV32-NEXT:    vsra.vi v10, v10, 2
797; RV32-NEXT:    vadd.vv v10, v10, v12
798; RV32-NEXT:    li a0, -7
799; RV32-NEXT:    vnmsac.vx v8, a0, v10
800; RV32-NEXT:    ret
801;
802; RV64-LABEL: vrem_vi_nxv4i32_0:
803; RV64:       # %bb.0:
804; RV64-NEXT:    lui a0, 449390
805; RV64-NEXT:    addi a0, a0, -1171
806; RV64-NEXT:    vsetvli a1, zero, e32, m2, ta, ma
807; RV64-NEXT:    vmulh.vx v10, v8, a0
808; RV64-NEXT:    vsub.vv v10, v10, v8
809; RV64-NEXT:    vsra.vi v10, v10, 2
810; RV64-NEXT:    vsrl.vi v12, v10, 31
811; RV64-NEXT:    vadd.vv v10, v10, v12
812; RV64-NEXT:    li a0, -7
813; RV64-NEXT:    vnmsac.vx v8, a0, v10
814; RV64-NEXT:    ret
815  %vc = srem <vscale x 4 x i32> %va, splat (i32 -7)
816  ret <vscale x 4 x i32> %vc
817}
818
819define <vscale x 8 x i32> @vrem_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {
820; CHECK-LABEL: vrem_vv_nxv8i32:
821; CHECK:       # %bb.0:
822; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, ma
823; CHECK-NEXT:    vrem.vv v8, v8, v12
824; CHECK-NEXT:    ret
825  %vc = srem <vscale x 8 x i32> %va, %vb
826  ret <vscale x 8 x i32> %vc
827}
828
829define <vscale x 8 x i32> @vrem_vx_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b) {
830; CHECK-LABEL: vrem_vx_nxv8i32:
831; CHECK:       # %bb.0:
832; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, ma
833; CHECK-NEXT:    vrem.vx v8, v8, a0
834; CHECK-NEXT:    ret
835  %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
836  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
837  %vc = srem <vscale x 8 x i32> %va, %splat
838  ret <vscale x 8 x i32> %vc
839}
840
841define <vscale x 8 x i32> @vrem_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
842; RV32-LABEL: vrem_vi_nxv8i32_0:
843; RV32:       # %bb.0:
844; RV32-NEXT:    lui a0, 449390
845; RV32-NEXT:    addi a0, a0, -1171
846; RV32-NEXT:    vsetvli a1, zero, e32, m4, ta, ma
847; RV32-NEXT:    vmulh.vx v12, v8, a0
848; RV32-NEXT:    vsub.vv v12, v12, v8
849; RV32-NEXT:    vsrl.vi v16, v12, 31
850; RV32-NEXT:    vsra.vi v12, v12, 2
851; RV32-NEXT:    vadd.vv v12, v12, v16
852; RV32-NEXT:    li a0, -7
853; RV32-NEXT:    vnmsac.vx v8, a0, v12
854; RV32-NEXT:    ret
855;
856; RV64-LABEL: vrem_vi_nxv8i32_0:
857; RV64:       # %bb.0:
858; RV64-NEXT:    lui a0, 449390
859; RV64-NEXT:    addi a0, a0, -1171
860; RV64-NEXT:    vsetvli a1, zero, e32, m4, ta, ma
861; RV64-NEXT:    vmulh.vx v12, v8, a0
862; RV64-NEXT:    vsub.vv v12, v12, v8
863; RV64-NEXT:    vsra.vi v12, v12, 2
864; RV64-NEXT:    vsrl.vi v16, v12, 31
865; RV64-NEXT:    vadd.vv v12, v12, v16
866; RV64-NEXT:    li a0, -7
867; RV64-NEXT:    vnmsac.vx v8, a0, v12
868; RV64-NEXT:    ret
869  %vc = srem <vscale x 8 x i32> %va, splat (i32 -7)
870  ret <vscale x 8 x i32> %vc
871}
872
873define <vscale x 16 x i32> @vrem_vv_nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %vb) {
874; CHECK-LABEL: vrem_vv_nxv16i32:
875; CHECK:       # %bb.0:
876; CHECK-NEXT:    vsetvli a0, zero, e32, m8, ta, ma
877; CHECK-NEXT:    vrem.vv v8, v8, v16
878; CHECK-NEXT:    ret
879  %vc = srem <vscale x 16 x i32> %va, %vb
880  ret <vscale x 16 x i32> %vc
881}
882
883define <vscale x 16 x i32> @vrem_vx_nxv16i32(<vscale x 16 x i32> %va, i32 signext %b) {
884; CHECK-LABEL: vrem_vx_nxv16i32:
885; CHECK:       # %bb.0:
886; CHECK-NEXT:    vsetvli a1, zero, e32, m8, ta, ma
887; CHECK-NEXT:    vrem.vx v8, v8, a0
888; CHECK-NEXT:    ret
889  %head = insertelement <vscale x 16 x i32> poison, i32 %b, i32 0
890  %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> poison, <vscale x 16 x i32> zeroinitializer
891  %vc = srem <vscale x 16 x i32> %va, %splat
892  ret <vscale x 16 x i32> %vc
893}
894
895define <vscale x 16 x i32> @vrem_vi_nxv16i32_0(<vscale x 16 x i32> %va) {
896; RV32-LABEL: vrem_vi_nxv16i32_0:
897; RV32:       # %bb.0:
898; RV32-NEXT:    lui a0, 449390
899; RV32-NEXT:    addi a0, a0, -1171
900; RV32-NEXT:    vsetvli a1, zero, e32, m8, ta, ma
901; RV32-NEXT:    vmulh.vx v16, v8, a0
902; RV32-NEXT:    vsub.vv v16, v16, v8
903; RV32-NEXT:    vsrl.vi v24, v16, 31
904; RV32-NEXT:    vsra.vi v16, v16, 2
905; RV32-NEXT:    vadd.vv v16, v16, v24
906; RV32-NEXT:    li a0, -7
907; RV32-NEXT:    vnmsac.vx v8, a0, v16
908; RV32-NEXT:    ret
909;
910; RV64-LABEL: vrem_vi_nxv16i32_0:
911; RV64:       # %bb.0:
912; RV64-NEXT:    lui a0, 449390
913; RV64-NEXT:    addi a0, a0, -1171
914; RV64-NEXT:    vsetvli a1, zero, e32, m8, ta, ma
915; RV64-NEXT:    vmulh.vx v16, v8, a0
916; RV64-NEXT:    vsub.vv v16, v16, v8
917; RV64-NEXT:    vsra.vi v16, v16, 2
918; RV64-NEXT:    vsrl.vi v24, v16, 31
919; RV64-NEXT:    vadd.vv v16, v16, v24
920; RV64-NEXT:    li a0, -7
921; RV64-NEXT:    vnmsac.vx v8, a0, v16
922; RV64-NEXT:    ret
923  %vc = srem <vscale x 16 x i32> %va, splat (i32 -7)
924  ret <vscale x 16 x i32> %vc
925}
926
927define <vscale x 1 x i64> @vrem_vv_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb) {
928; CHECK-LABEL: vrem_vv_nxv1i64:
929; CHECK:       # %bb.0:
930; CHECK-NEXT:    vsetvli a0, zero, e64, m1, ta, ma
931; CHECK-NEXT:    vrem.vv v8, v8, v9
932; CHECK-NEXT:    ret
933  %vc = srem <vscale x 1 x i64> %va, %vb
934  ret <vscale x 1 x i64> %vc
935}
936
937define <vscale x 1 x i64> @vrem_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b) {
938; RV32-LABEL: vrem_vx_nxv1i64:
939; RV32:       # %bb.0:
940; RV32-NEXT:    addi sp, sp, -16
941; RV32-NEXT:    .cfi_def_cfa_offset 16
942; RV32-NEXT:    sw a0, 8(sp)
943; RV32-NEXT:    sw a1, 12(sp)
944; RV32-NEXT:    addi a0, sp, 8
945; RV32-NEXT:    vsetvli a1, zero, e64, m1, ta, ma
946; RV32-NEXT:    vlse64.v v9, (a0), zero
947; RV32-NEXT:    vrem.vv v8, v8, v9
948; RV32-NEXT:    addi sp, sp, 16
949; RV32-NEXT:    .cfi_def_cfa_offset 0
950; RV32-NEXT:    ret
951;
952; RV64-LABEL: vrem_vx_nxv1i64:
953; RV64:       # %bb.0:
954; RV64-NEXT:    vsetvli a1, zero, e64, m1, ta, ma
955; RV64-NEXT:    vrem.vx v8, v8, a0
956; RV64-NEXT:    ret
957  %head = insertelement <vscale x 1 x i64> poison, i64 %b, i32 0
958  %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer
959  %vc = srem <vscale x 1 x i64> %va, %splat
960  ret <vscale x 1 x i64> %vc
961}
962
963define <vscale x 1 x i64> @vrem_vi_nxv1i64_0(<vscale x 1 x i64> %va) {
964; RV32-V-LABEL: vrem_vi_nxv1i64_0:
965; RV32-V:       # %bb.0:
966; RV32-V-NEXT:    addi sp, sp, -16
967; RV32-V-NEXT:    .cfi_def_cfa_offset 16
968; RV32-V-NEXT:    lui a0, 748983
969; RV32-V-NEXT:    lui a1, 898779
970; RV32-V-NEXT:    addi a0, a0, -586
971; RV32-V-NEXT:    addi a1, a1, 1755
972; RV32-V-NEXT:    sw a1, 8(sp)
973; RV32-V-NEXT:    sw a0, 12(sp)
974; RV32-V-NEXT:    addi a0, sp, 8
975; RV32-V-NEXT:    vsetvli a1, zero, e64, m1, ta, ma
976; RV32-V-NEXT:    vlse64.v v9, (a0), zero
977; RV32-V-NEXT:    li a0, 63
978; RV32-V-NEXT:    vmulh.vv v9, v8, v9
979; RV32-V-NEXT:    vsrl.vx v10, v9, a0
980; RV32-V-NEXT:    vsra.vi v9, v9, 1
981; RV32-V-NEXT:    vadd.vv v9, v9, v10
982; RV32-V-NEXT:    li a0, -7
983; RV32-V-NEXT:    vnmsac.vx v8, a0, v9
984; RV32-V-NEXT:    addi sp, sp, 16
985; RV32-V-NEXT:    .cfi_def_cfa_offset 0
986; RV32-V-NEXT:    ret
987;
988; ZVE64X-LABEL: vrem_vi_nxv1i64_0:
989; ZVE64X:       # %bb.0:
990; ZVE64X-NEXT:    li a0, -7
991; ZVE64X-NEXT:    vsetvli a1, zero, e64, m1, ta, ma
992; ZVE64X-NEXT:    vrem.vx v8, v8, a0
993; ZVE64X-NEXT:    ret
994;
995; RV64-V-LABEL: vrem_vi_nxv1i64_0:
996; RV64-V:       # %bb.0:
997; RV64-V-NEXT:    lui a0, %hi(.LCPI67_0)
998; RV64-V-NEXT:    ld a0, %lo(.LCPI67_0)(a0)
999; RV64-V-NEXT:    vsetvli a1, zero, e64, m1, ta, ma
1000; RV64-V-NEXT:    vmulh.vx v9, v8, a0
1001; RV64-V-NEXT:    li a0, 63
1002; RV64-V-NEXT:    vsrl.vx v10, v9, a0
1003; RV64-V-NEXT:    vsra.vi v9, v9, 1
1004; RV64-V-NEXT:    vadd.vv v9, v9, v10
1005; RV64-V-NEXT:    li a0, -7
1006; RV64-V-NEXT:    vnmsac.vx v8, a0, v9
1007; RV64-V-NEXT:    ret
1008  %vc = srem <vscale x 1 x i64> %va, splat (i64 -7)
1009  ret <vscale x 1 x i64> %vc
1010}
1011
1012define <vscale x 2 x i64> @vrem_vv_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb) {
1013; CHECK-LABEL: vrem_vv_nxv2i64:
1014; CHECK:       # %bb.0:
1015; CHECK-NEXT:    vsetvli a0, zero, e64, m2, ta, ma
1016; CHECK-NEXT:    vrem.vv v8, v8, v10
1017; CHECK-NEXT:    ret
1018  %vc = srem <vscale x 2 x i64> %va, %vb
1019  ret <vscale x 2 x i64> %vc
1020}
1021
1022define <vscale x 2 x i64> @vrem_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b) {
1023; RV32-LABEL: vrem_vx_nxv2i64:
1024; RV32:       # %bb.0:
1025; RV32-NEXT:    addi sp, sp, -16
1026; RV32-NEXT:    .cfi_def_cfa_offset 16
1027; RV32-NEXT:    sw a0, 8(sp)
1028; RV32-NEXT:    sw a1, 12(sp)
1029; RV32-NEXT:    addi a0, sp, 8
1030; RV32-NEXT:    vsetvli a1, zero, e64, m2, ta, ma
1031; RV32-NEXT:    vlse64.v v10, (a0), zero
1032; RV32-NEXT:    vrem.vv v8, v8, v10
1033; RV32-NEXT:    addi sp, sp, 16
1034; RV32-NEXT:    .cfi_def_cfa_offset 0
1035; RV32-NEXT:    ret
1036;
1037; RV64-LABEL: vrem_vx_nxv2i64:
1038; RV64:       # %bb.0:
1039; RV64-NEXT:    vsetvli a1, zero, e64, m2, ta, ma
1040; RV64-NEXT:    vrem.vx v8, v8, a0
1041; RV64-NEXT:    ret
1042  %head = insertelement <vscale x 2 x i64> poison, i64 %b, i32 0
1043  %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
1044  %vc = srem <vscale x 2 x i64> %va, %splat
1045  ret <vscale x 2 x i64> %vc
1046}
1047
1048define <vscale x 2 x i64> @vrem_vi_nxv2i64_0(<vscale x 2 x i64> %va) {
1049; RV32-V-LABEL: vrem_vi_nxv2i64_0:
1050; RV32-V:       # %bb.0:
1051; RV32-V-NEXT:    addi sp, sp, -16
1052; RV32-V-NEXT:    .cfi_def_cfa_offset 16
1053; RV32-V-NEXT:    lui a0, 748983
1054; RV32-V-NEXT:    lui a1, 898779
1055; RV32-V-NEXT:    addi a0, a0, -586
1056; RV32-V-NEXT:    addi a1, a1, 1755
1057; RV32-V-NEXT:    sw a1, 8(sp)
1058; RV32-V-NEXT:    sw a0, 12(sp)
1059; RV32-V-NEXT:    addi a0, sp, 8
1060; RV32-V-NEXT:    vsetvli a1, zero, e64, m2, ta, ma
1061; RV32-V-NEXT:    vlse64.v v10, (a0), zero
1062; RV32-V-NEXT:    li a0, 63
1063; RV32-V-NEXT:    vmulh.vv v10, v8, v10
1064; RV32-V-NEXT:    vsrl.vx v12, v10, a0
1065; RV32-V-NEXT:    vsra.vi v10, v10, 1
1066; RV32-V-NEXT:    vadd.vv v10, v10, v12
1067; RV32-V-NEXT:    li a0, -7
1068; RV32-V-NEXT:    vnmsac.vx v8, a0, v10
1069; RV32-V-NEXT:    addi sp, sp, 16
1070; RV32-V-NEXT:    .cfi_def_cfa_offset 0
1071; RV32-V-NEXT:    ret
1072;
1073; ZVE64X-LABEL: vrem_vi_nxv2i64_0:
1074; ZVE64X:       # %bb.0:
1075; ZVE64X-NEXT:    li a0, -7
1076; ZVE64X-NEXT:    vsetvli a1, zero, e64, m2, ta, ma
1077; ZVE64X-NEXT:    vrem.vx v8, v8, a0
1078; ZVE64X-NEXT:    ret
1079;
1080; RV64-V-LABEL: vrem_vi_nxv2i64_0:
1081; RV64-V:       # %bb.0:
1082; RV64-V-NEXT:    lui a0, %hi(.LCPI70_0)
1083; RV64-V-NEXT:    ld a0, %lo(.LCPI70_0)(a0)
1084; RV64-V-NEXT:    vsetvli a1, zero, e64, m2, ta, ma
1085; RV64-V-NEXT:    vmulh.vx v10, v8, a0
1086; RV64-V-NEXT:    li a0, 63
1087; RV64-V-NEXT:    vsrl.vx v12, v10, a0
1088; RV64-V-NEXT:    vsra.vi v10, v10, 1
1089; RV64-V-NEXT:    vadd.vv v10, v10, v12
1090; RV64-V-NEXT:    li a0, -7
1091; RV64-V-NEXT:    vnmsac.vx v8, a0, v10
1092; RV64-V-NEXT:    ret
1093  %vc = srem <vscale x 2 x i64> %va, splat (i64 -7)
1094  ret <vscale x 2 x i64> %vc
1095}
1096
1097define <vscale x 4 x i64> @vrem_vv_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb) {
1098; CHECK-LABEL: vrem_vv_nxv4i64:
1099; CHECK:       # %bb.0:
1100; CHECK-NEXT:    vsetvli a0, zero, e64, m4, ta, ma
1101; CHECK-NEXT:    vrem.vv v8, v8, v12
1102; CHECK-NEXT:    ret
1103  %vc = srem <vscale x 4 x i64> %va, %vb
1104  ret <vscale x 4 x i64> %vc
1105}
1106
1107define <vscale x 4 x i64> @vrem_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b) {
1108; RV32-LABEL: vrem_vx_nxv4i64:
1109; RV32:       # %bb.0:
1110; RV32-NEXT:    addi sp, sp, -16
1111; RV32-NEXT:    .cfi_def_cfa_offset 16
1112; RV32-NEXT:    sw a0, 8(sp)
1113; RV32-NEXT:    sw a1, 12(sp)
1114; RV32-NEXT:    addi a0, sp, 8
1115; RV32-NEXT:    vsetvli a1, zero, e64, m4, ta, ma
1116; RV32-NEXT:    vlse64.v v12, (a0), zero
1117; RV32-NEXT:    vrem.vv v8, v8, v12
1118; RV32-NEXT:    addi sp, sp, 16
1119; RV32-NEXT:    .cfi_def_cfa_offset 0
1120; RV32-NEXT:    ret
1121;
1122; RV64-LABEL: vrem_vx_nxv4i64:
1123; RV64:       # %bb.0:
1124; RV64-NEXT:    vsetvli a1, zero, e64, m4, ta, ma
1125; RV64-NEXT:    vrem.vx v8, v8, a0
1126; RV64-NEXT:    ret
1127  %head = insertelement <vscale x 4 x i64> poison, i64 %b, i32 0
1128  %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer
1129  %vc = srem <vscale x 4 x i64> %va, %splat
1130  ret <vscale x 4 x i64> %vc
1131}
1132
1133define <vscale x 4 x i64> @vrem_vi_nxv4i64_0(<vscale x 4 x i64> %va) {
1134; RV32-V-LABEL: vrem_vi_nxv4i64_0:
1135; RV32-V:       # %bb.0:
1136; RV32-V-NEXT:    addi sp, sp, -16
1137; RV32-V-NEXT:    .cfi_def_cfa_offset 16
1138; RV32-V-NEXT:    lui a0, 748983
1139; RV32-V-NEXT:    lui a1, 898779
1140; RV32-V-NEXT:    addi a0, a0, -586
1141; RV32-V-NEXT:    addi a1, a1, 1755
1142; RV32-V-NEXT:    sw a1, 8(sp)
1143; RV32-V-NEXT:    sw a0, 12(sp)
1144; RV32-V-NEXT:    addi a0, sp, 8
1145; RV32-V-NEXT:    vsetvli a1, zero, e64, m4, ta, ma
1146; RV32-V-NEXT:    vlse64.v v12, (a0), zero
1147; RV32-V-NEXT:    li a0, 63
1148; RV32-V-NEXT:    vmulh.vv v12, v8, v12
1149; RV32-V-NEXT:    vsrl.vx v16, v12, a0
1150; RV32-V-NEXT:    vsra.vi v12, v12, 1
1151; RV32-V-NEXT:    vadd.vv v12, v12, v16
1152; RV32-V-NEXT:    li a0, -7
1153; RV32-V-NEXT:    vnmsac.vx v8, a0, v12
1154; RV32-V-NEXT:    addi sp, sp, 16
1155; RV32-V-NEXT:    .cfi_def_cfa_offset 0
1156; RV32-V-NEXT:    ret
1157;
1158; ZVE64X-LABEL: vrem_vi_nxv4i64_0:
1159; ZVE64X:       # %bb.0:
1160; ZVE64X-NEXT:    li a0, -7
1161; ZVE64X-NEXT:    vsetvli a1, zero, e64, m4, ta, ma
1162; ZVE64X-NEXT:    vrem.vx v8, v8, a0
1163; ZVE64X-NEXT:    ret
1164;
1165; RV64-V-LABEL: vrem_vi_nxv4i64_0:
1166; RV64-V:       # %bb.0:
1167; RV64-V-NEXT:    lui a0, %hi(.LCPI73_0)
1168; RV64-V-NEXT:    ld a0, %lo(.LCPI73_0)(a0)
1169; RV64-V-NEXT:    vsetvli a1, zero, e64, m4, ta, ma
1170; RV64-V-NEXT:    vmulh.vx v12, v8, a0
1171; RV64-V-NEXT:    li a0, 63
1172; RV64-V-NEXT:    vsrl.vx v16, v12, a0
1173; RV64-V-NEXT:    vsra.vi v12, v12, 1
1174; RV64-V-NEXT:    vadd.vv v12, v12, v16
1175; RV64-V-NEXT:    li a0, -7
1176; RV64-V-NEXT:    vnmsac.vx v8, a0, v12
1177; RV64-V-NEXT:    ret
1178  %vc = srem <vscale x 4 x i64> %va, splat (i64 -7)
1179  ret <vscale x 4 x i64> %vc
1180}
1181
1182define <vscale x 8 x i64> @vrem_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) {
1183; CHECK-LABEL: vrem_vv_nxv8i64:
1184; CHECK:       # %bb.0:
1185; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, ma
1186; CHECK-NEXT:    vrem.vv v8, v8, v16
1187; CHECK-NEXT:    ret
1188  %vc = srem <vscale x 8 x i64> %va, %vb
1189  ret <vscale x 8 x i64> %vc
1190}
1191
1192define <vscale x 8 x i64> @vrem_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
1193; RV32-LABEL: vrem_vx_nxv8i64:
1194; RV32:       # %bb.0:
1195; RV32-NEXT:    addi sp, sp, -16
1196; RV32-NEXT:    .cfi_def_cfa_offset 16
1197; RV32-NEXT:    sw a0, 8(sp)
1198; RV32-NEXT:    sw a1, 12(sp)
1199; RV32-NEXT:    addi a0, sp, 8
1200; RV32-NEXT:    vsetvli a1, zero, e64, m8, ta, ma
1201; RV32-NEXT:    vlse64.v v16, (a0), zero
1202; RV32-NEXT:    vrem.vv v8, v8, v16
1203; RV32-NEXT:    addi sp, sp, 16
1204; RV32-NEXT:    .cfi_def_cfa_offset 0
1205; RV32-NEXT:    ret
1206;
1207; RV64-LABEL: vrem_vx_nxv8i64:
1208; RV64:       # %bb.0:
1209; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, ma
1210; RV64-NEXT:    vrem.vx v8, v8, a0
1211; RV64-NEXT:    ret
1212  %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
1213  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
1214  %vc = srem <vscale x 8 x i64> %va, %splat
1215  ret <vscale x 8 x i64> %vc
1216}
1217
1218define <vscale x 8 x i64> @vrem_vi_nxv8i64_0(<vscale x 8 x i64> %va) {
1219; RV32-V-LABEL: vrem_vi_nxv8i64_0:
1220; RV32-V:       # %bb.0:
1221; RV32-V-NEXT:    addi sp, sp, -16
1222; RV32-V-NEXT:    .cfi_def_cfa_offset 16
1223; RV32-V-NEXT:    lui a0, 748983
1224; RV32-V-NEXT:    lui a1, 898779
1225; RV32-V-NEXT:    addi a0, a0, -586
1226; RV32-V-NEXT:    addi a1, a1, 1755
1227; RV32-V-NEXT:    sw a1, 8(sp)
1228; RV32-V-NEXT:    sw a0, 12(sp)
1229; RV32-V-NEXT:    addi a0, sp, 8
1230; RV32-V-NEXT:    vsetvli a1, zero, e64, m8, ta, ma
1231; RV32-V-NEXT:    vlse64.v v16, (a0), zero
1232; RV32-V-NEXT:    li a0, 63
1233; RV32-V-NEXT:    vmulh.vv v16, v8, v16
1234; RV32-V-NEXT:    vsrl.vx v24, v16, a0
1235; RV32-V-NEXT:    vsra.vi v16, v16, 1
1236; RV32-V-NEXT:    vadd.vv v16, v16, v24
1237; RV32-V-NEXT:    li a0, -7
1238; RV32-V-NEXT:    vnmsac.vx v8, a0, v16
1239; RV32-V-NEXT:    addi sp, sp, 16
1240; RV32-V-NEXT:    .cfi_def_cfa_offset 0
1241; RV32-V-NEXT:    ret
1242;
1243; ZVE64X-LABEL: vrem_vi_nxv8i64_0:
1244; ZVE64X:       # %bb.0:
1245; ZVE64X-NEXT:    li a0, -7
1246; ZVE64X-NEXT:    vsetvli a1, zero, e64, m8, ta, ma
1247; ZVE64X-NEXT:    vrem.vx v8, v8, a0
1248; ZVE64X-NEXT:    ret
1249;
1250; RV64-V-LABEL: vrem_vi_nxv8i64_0:
1251; RV64-V:       # %bb.0:
1252; RV64-V-NEXT:    lui a0, %hi(.LCPI76_0)
1253; RV64-V-NEXT:    ld a0, %lo(.LCPI76_0)(a0)
1254; RV64-V-NEXT:    vsetvli a1, zero, e64, m8, ta, ma
1255; RV64-V-NEXT:    vmulh.vx v16, v8, a0
1256; RV64-V-NEXT:    li a0, 63
1257; RV64-V-NEXT:    vsrl.vx v24, v16, a0
1258; RV64-V-NEXT:    vsra.vi v16, v16, 1
1259; RV64-V-NEXT:    vadd.vv v16, v16, v24
1260; RV64-V-NEXT:    li a0, -7
1261; RV64-V-NEXT:    vnmsac.vx v8, a0, v16
1262; RV64-V-NEXT:    ret
1263  %vc = srem <vscale x 8 x i64> %va, splat (i64 -7)
1264  ret <vscale x 8 x i64> %vc
1265}
1266