xref: /llvm-project/llvm/test/CodeGen/RISCV/rvv/vreductions-fp-vp.ll (revision 9122c5235ec85ce0c0ad337e862b006e7b349d84) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v -target-abi=ilp32d \
3; RUN:     -verify-machineinstrs < %s | FileCheck %s
4; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v -target-abi=lp64d \
5; RUN:     -verify-machineinstrs < %s | FileCheck %s
6
7declare half @llvm.vp.reduce.fadd.nxv1f16(half, <vscale x 1 x half>, <vscale x 1 x i1>, i32)
8
9define half @vpreduce_fadd_nxv1f16(half %s, <vscale x 1 x half> %v, <vscale x 1 x i1> %m, i32 zeroext %evl) {
10; CHECK-LABEL: vpreduce_fadd_nxv1f16:
11; CHECK:       # %bb.0:
12; CHECK-NEXT:    vsetivli zero, 1, e16, m1, ta, ma
13; CHECK-NEXT:    vfmv.s.f v9, fa0
14; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma
15; CHECK-NEXT:    vfredusum.vs v9, v8, v9, v0.t
16; CHECK-NEXT:    vfmv.f.s fa0, v9
17; CHECK-NEXT:    ret
18  %r = call reassoc half @llvm.vp.reduce.fadd.nxv1f16(half %s, <vscale x 1 x half> %v, <vscale x 1 x i1> %m, i32 %evl)
19  ret half %r
20}
21
22define half @vpreduce_ord_fadd_nxv1f16(half %s, <vscale x 1 x half> %v, <vscale x 1 x i1> %m, i32 zeroext %evl) {
23; CHECK-LABEL: vpreduce_ord_fadd_nxv1f16:
24; CHECK:       # %bb.0:
25; CHECK-NEXT:    vsetivli zero, 1, e16, m1, ta, ma
26; CHECK-NEXT:    vfmv.s.f v9, fa0
27; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma
28; CHECK-NEXT:    vfredosum.vs v9, v8, v9, v0.t
29; CHECK-NEXT:    vfmv.f.s fa0, v9
30; CHECK-NEXT:    ret
31  %r = call half @llvm.vp.reduce.fadd.nxv1f16(half %s, <vscale x 1 x half> %v, <vscale x 1 x i1> %m, i32 %evl)
32  ret half %r
33}
34
35declare half @llvm.vp.reduce.fadd.nxv2f16(half, <vscale x 2 x half>, <vscale x 2 x i1>, i32)
36
37define half @vpreduce_fadd_nxv2f16(half %s, <vscale x 2 x half> %v, <vscale x 2 x i1> %m, i32 zeroext %evl) {
38; CHECK-LABEL: vpreduce_fadd_nxv2f16:
39; CHECK:       # %bb.0:
40; CHECK-NEXT:    vsetivli zero, 1, e16, m1, ta, ma
41; CHECK-NEXT:    vfmv.s.f v9, fa0
42; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma
43; CHECK-NEXT:    vfredusum.vs v9, v8, v9, v0.t
44; CHECK-NEXT:    vfmv.f.s fa0, v9
45; CHECK-NEXT:    ret
46  %r = call reassoc half @llvm.vp.reduce.fadd.nxv2f16(half %s, <vscale x 2 x half> %v, <vscale x 2 x i1> %m, i32 %evl)
47  ret half %r
48}
49
50define half @vpreduce_ord_fadd_nxv2f16(half %s, <vscale x 2 x half> %v, <vscale x 2 x i1> %m, i32 zeroext %evl) {
51; CHECK-LABEL: vpreduce_ord_fadd_nxv2f16:
52; CHECK:       # %bb.0:
53; CHECK-NEXT:    vsetivli zero, 1, e16, m1, ta, ma
54; CHECK-NEXT:    vfmv.s.f v9, fa0
55; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma
56; CHECK-NEXT:    vfredosum.vs v9, v8, v9, v0.t
57; CHECK-NEXT:    vfmv.f.s fa0, v9
58; CHECK-NEXT:    ret
59  %r = call half @llvm.vp.reduce.fadd.nxv2f16(half %s, <vscale x 2 x half> %v, <vscale x 2 x i1> %m, i32 %evl)
60  ret half %r
61}
62
63declare half @llvm.vp.reduce.fadd.nxv4f16(half, <vscale x 4 x half>, <vscale x 4 x i1>, i32)
64
65define half @vpreduce_fadd_nxv4f16(half %s, <vscale x 4 x half> %v, <vscale x 4 x i1> %m, i32 zeroext %evl) {
66; CHECK-LABEL: vpreduce_fadd_nxv4f16:
67; CHECK:       # %bb.0:
68; CHECK-NEXT:    vsetivli zero, 1, e16, m1, ta, ma
69; CHECK-NEXT:    vfmv.s.f v9, fa0
70; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, ma
71; CHECK-NEXT:    vfredusum.vs v9, v8, v9, v0.t
72; CHECK-NEXT:    vfmv.f.s fa0, v9
73; CHECK-NEXT:    ret
74  %r = call reassoc half @llvm.vp.reduce.fadd.nxv4f16(half %s, <vscale x 4 x half> %v, <vscale x 4 x i1> %m, i32 %evl)
75  ret half %r
76}
77
78define half @vpreduce_ord_fadd_nxv4f16(half %s, <vscale x 4 x half> %v, <vscale x 4 x i1> %m, i32 zeroext %evl) {
79; CHECK-LABEL: vpreduce_ord_fadd_nxv4f16:
80; CHECK:       # %bb.0:
81; CHECK-NEXT:    vsetivli zero, 1, e16, m1, ta, ma
82; CHECK-NEXT:    vfmv.s.f v9, fa0
83; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, ma
84; CHECK-NEXT:    vfredosum.vs v9, v8, v9, v0.t
85; CHECK-NEXT:    vfmv.f.s fa0, v9
86; CHECK-NEXT:    ret
87  %r = call half @llvm.vp.reduce.fadd.nxv4f16(half %s, <vscale x 4 x half> %v, <vscale x 4 x i1> %m, i32 %evl)
88  ret half %r
89}
90
91declare half @llvm.vp.reduce.fadd.nxv64f16(half, <vscale x 64 x half>, <vscale x 64 x i1>, i32)
92
93define half @vpreduce_fadd_nxv64f16(half %s, <vscale x 64 x half> %v, <vscale x 64 x i1> %m, i32 zeroext %evl) {
94; CHECK-LABEL: vpreduce_fadd_nxv64f16:
95; CHECK:       # %bb.0:
96; CHECK-NEXT:    csrr a2, vlenb
97; CHECK-NEXT:    srli a1, a2, 1
98; CHECK-NEXT:    slli a2, a2, 2
99; CHECK-NEXT:    vsetvli a3, zero, e8, m1, ta, ma
100; CHECK-NEXT:    vslidedown.vx v24, v0, a1
101; CHECK-NEXT:    sub a1, a0, a2
102; CHECK-NEXT:    sltu a3, a0, a1
103; CHECK-NEXT:    addi a3, a3, -1
104; CHECK-NEXT:    and a1, a3, a1
105; CHECK-NEXT:    bltu a0, a2, .LBB6_2
106; CHECK-NEXT:  # %bb.1:
107; CHECK-NEXT:    mv a0, a2
108; CHECK-NEXT:  .LBB6_2:
109; CHECK-NEXT:    vsetvli zero, zero, e16, m2, ta, ma
110; CHECK-NEXT:    vfmv.s.f v25, fa0
111; CHECK-NEXT:    vsetvli zero, a0, e16, m8, ta, ma
112; CHECK-NEXT:    vfredusum.vs v25, v8, v25, v0.t
113; CHECK-NEXT:    vmv1r.v v0, v24
114; CHECK-NEXT:    vsetvli zero, a1, e16, m8, ta, ma
115; CHECK-NEXT:    vfredusum.vs v25, v16, v25, v0.t
116; CHECK-NEXT:    vfmv.f.s fa0, v25
117; CHECK-NEXT:    ret
118  %r = call reassoc half @llvm.vp.reduce.fadd.nxv64f16(half %s, <vscale x 64 x half> %v, <vscale x 64 x i1> %m, i32 %evl)
119  ret half %r
120}
121
122define half @vpreduce_ord_fadd_nxv64f16(half %s, <vscale x 64 x half> %v, <vscale x 64 x i1> %m, i32 zeroext %evl) {
123; CHECK-LABEL: vpreduce_ord_fadd_nxv64f16:
124; CHECK:       # %bb.0:
125; CHECK-NEXT:    csrr a2, vlenb
126; CHECK-NEXT:    srli a1, a2, 1
127; CHECK-NEXT:    slli a2, a2, 2
128; CHECK-NEXT:    vsetvli a3, zero, e8, m1, ta, ma
129; CHECK-NEXT:    vslidedown.vx v24, v0, a1
130; CHECK-NEXT:    sub a1, a0, a2
131; CHECK-NEXT:    sltu a3, a0, a1
132; CHECK-NEXT:    addi a3, a3, -1
133; CHECK-NEXT:    and a1, a3, a1
134; CHECK-NEXT:    bltu a0, a2, .LBB7_2
135; CHECK-NEXT:  # %bb.1:
136; CHECK-NEXT:    mv a0, a2
137; CHECK-NEXT:  .LBB7_2:
138; CHECK-NEXT:    vsetvli zero, zero, e16, m2, ta, ma
139; CHECK-NEXT:    vfmv.s.f v25, fa0
140; CHECK-NEXT:    vsetvli zero, a0, e16, m8, ta, ma
141; CHECK-NEXT:    vfredosum.vs v25, v8, v25, v0.t
142; CHECK-NEXT:    vmv1r.v v0, v24
143; CHECK-NEXT:    vsetvli zero, a1, e16, m8, ta, ma
144; CHECK-NEXT:    vfredosum.vs v25, v16, v25, v0.t
145; CHECK-NEXT:    vfmv.f.s fa0, v25
146; CHECK-NEXT:    ret
147  %r = call half @llvm.vp.reduce.fadd.nxv64f16(half %s, <vscale x 64 x half> %v, <vscale x 64 x i1> %m, i32 %evl)
148  ret half %r
149}
150
151declare float @llvm.vp.reduce.fadd.nxv1f32(float, <vscale x 1 x float>, <vscale x 1 x i1>, i32)
152
153define float @vpreduce_fadd_nxv1f32(float %s, <vscale x 1 x float> %v, <vscale x 1 x i1> %m, i32 zeroext %evl) {
154; CHECK-LABEL: vpreduce_fadd_nxv1f32:
155; CHECK:       # %bb.0:
156; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
157; CHECK-NEXT:    vfmv.s.f v9, fa0
158; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma
159; CHECK-NEXT:    vfredusum.vs v9, v8, v9, v0.t
160; CHECK-NEXT:    vfmv.f.s fa0, v9
161; CHECK-NEXT:    ret
162  %r = call reassoc float @llvm.vp.reduce.fadd.nxv1f32(float %s, <vscale x 1 x float> %v, <vscale x 1 x i1> %m, i32 %evl)
163  ret float %r
164}
165
166define float @vpreduce_ord_fadd_nxv1f32(float %s, <vscale x 1 x float> %v, <vscale x 1 x i1> %m, i32 zeroext %evl) {
167; CHECK-LABEL: vpreduce_ord_fadd_nxv1f32:
168; CHECK:       # %bb.0:
169; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
170; CHECK-NEXT:    vfmv.s.f v9, fa0
171; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma
172; CHECK-NEXT:    vfredosum.vs v9, v8, v9, v0.t
173; CHECK-NEXT:    vfmv.f.s fa0, v9
174; CHECK-NEXT:    ret
175  %r = call float @llvm.vp.reduce.fadd.nxv1f32(float %s, <vscale x 1 x float> %v, <vscale x 1 x i1> %m, i32 %evl)
176  ret float %r
177}
178
179declare float @llvm.vp.reduce.fadd.nxv2f32(float, <vscale x 2 x float>, <vscale x 2 x i1>, i32)
180
181define float @vpreduce_fadd_nxv2f32(float %s, <vscale x 2 x float> %v, <vscale x 2 x i1> %m, i32 zeroext %evl) {
182; CHECK-LABEL: vpreduce_fadd_nxv2f32:
183; CHECK:       # %bb.0:
184; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
185; CHECK-NEXT:    vfmv.s.f v9, fa0
186; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma
187; CHECK-NEXT:    vfredusum.vs v9, v8, v9, v0.t
188; CHECK-NEXT:    vfmv.f.s fa0, v9
189; CHECK-NEXT:    ret
190  %r = call reassoc float @llvm.vp.reduce.fadd.nxv2f32(float %s, <vscale x 2 x float> %v, <vscale x 2 x i1> %m, i32 %evl)
191  ret float %r
192}
193
194define float @vpreduce_ord_fadd_nxv2f32(float %s, <vscale x 2 x float> %v, <vscale x 2 x i1> %m, i32 zeroext %evl) {
195; CHECK-LABEL: vpreduce_ord_fadd_nxv2f32:
196; CHECK:       # %bb.0:
197; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
198; CHECK-NEXT:    vfmv.s.f v9, fa0
199; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma
200; CHECK-NEXT:    vfredosum.vs v9, v8, v9, v0.t
201; CHECK-NEXT:    vfmv.f.s fa0, v9
202; CHECK-NEXT:    ret
203  %r = call float @llvm.vp.reduce.fadd.nxv2f32(float %s, <vscale x 2 x float> %v, <vscale x 2 x i1> %m, i32 %evl)
204  ret float %r
205}
206
207declare float @llvm.vp.reduce.fadd.nxv4f32(float, <vscale x 4 x float>, <vscale x 4 x i1>, i32)
208
209define float @vpreduce_fadd_nxv4f32(float %s, <vscale x 4 x float> %v, <vscale x 4 x i1> %m, i32 zeroext %evl) {
210; CHECK-LABEL: vpreduce_fadd_nxv4f32:
211; CHECK:       # %bb.0:
212; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
213; CHECK-NEXT:    vfmv.s.f v10, fa0
214; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma
215; CHECK-NEXT:    vfredusum.vs v10, v8, v10, v0.t
216; CHECK-NEXT:    vfmv.f.s fa0, v10
217; CHECK-NEXT:    ret
218  %r = call reassoc float @llvm.vp.reduce.fadd.nxv4f32(float %s, <vscale x 4 x float> %v, <vscale x 4 x i1> %m, i32 %evl)
219  ret float %r
220}
221
222define float @vpreduce_ord_fadd_nxv4f32(float %s, <vscale x 4 x float> %v, <vscale x 4 x i1> %m, i32 zeroext %evl) {
223; CHECK-LABEL: vpreduce_ord_fadd_nxv4f32:
224; CHECK:       # %bb.0:
225; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
226; CHECK-NEXT:    vfmv.s.f v10, fa0
227; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma
228; CHECK-NEXT:    vfredosum.vs v10, v8, v10, v0.t
229; CHECK-NEXT:    vfmv.f.s fa0, v10
230; CHECK-NEXT:    ret
231  %r = call float @llvm.vp.reduce.fadd.nxv4f32(float %s, <vscale x 4 x float> %v, <vscale x 4 x i1> %m, i32 %evl)
232  ret float %r
233}
234
235declare double @llvm.vp.reduce.fadd.nxv1f64(double, <vscale x 1 x double>, <vscale x 1 x i1>, i32)
236
237define double @vpreduce_fadd_nxv1f64(double %s, <vscale x 1 x double> %v, <vscale x 1 x i1> %m, i32 zeroext %evl) {
238; CHECK-LABEL: vpreduce_fadd_nxv1f64:
239; CHECK:       # %bb.0:
240; CHECK-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
241; CHECK-NEXT:    vfmv.s.f v9, fa0
242; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, ma
243; CHECK-NEXT:    vfredusum.vs v9, v8, v9, v0.t
244; CHECK-NEXT:    vfmv.f.s fa0, v9
245; CHECK-NEXT:    ret
246  %r = call reassoc double @llvm.vp.reduce.fadd.nxv1f64(double %s, <vscale x 1 x double> %v, <vscale x 1 x i1> %m, i32 %evl)
247  ret double %r
248}
249
250define double @vpreduce_ord_fadd_nxv1f64(double %s, <vscale x 1 x double> %v, <vscale x 1 x i1> %m, i32 zeroext %evl) {
251; CHECK-LABEL: vpreduce_ord_fadd_nxv1f64:
252; CHECK:       # %bb.0:
253; CHECK-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
254; CHECK-NEXT:    vfmv.s.f v9, fa0
255; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, ma
256; CHECK-NEXT:    vfredosum.vs v9, v8, v9, v0.t
257; CHECK-NEXT:    vfmv.f.s fa0, v9
258; CHECK-NEXT:    ret
259  %r = call double @llvm.vp.reduce.fadd.nxv1f64(double %s, <vscale x 1 x double> %v, <vscale x 1 x i1> %m, i32 %evl)
260  ret double %r
261}
262
263declare double @llvm.vp.reduce.fadd.nxv2f64(double, <vscale x 2 x double>, <vscale x 2 x i1>, i32)
264
265define double @vpreduce_fadd_nxv2f64(double %s, <vscale x 2 x double> %v, <vscale x 2 x i1> %m, i32 zeroext %evl) {
266; CHECK-LABEL: vpreduce_fadd_nxv2f64:
267; CHECK:       # %bb.0:
268; CHECK-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
269; CHECK-NEXT:    vfmv.s.f v10, fa0
270; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, ma
271; CHECK-NEXT:    vfredusum.vs v10, v8, v10, v0.t
272; CHECK-NEXT:    vfmv.f.s fa0, v10
273; CHECK-NEXT:    ret
274  %r = call reassoc double @llvm.vp.reduce.fadd.nxv2f64(double %s, <vscale x 2 x double> %v, <vscale x 2 x i1> %m, i32 %evl)
275  ret double %r
276}
277
278define double @vpreduce_ord_fadd_nxv2f64(double %s, <vscale x 2 x double> %v, <vscale x 2 x i1> %m, i32 zeroext %evl) {
279; CHECK-LABEL: vpreduce_ord_fadd_nxv2f64:
280; CHECK:       # %bb.0:
281; CHECK-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
282; CHECK-NEXT:    vfmv.s.f v10, fa0
283; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, ma
284; CHECK-NEXT:    vfredosum.vs v10, v8, v10, v0.t
285; CHECK-NEXT:    vfmv.f.s fa0, v10
286; CHECK-NEXT:    ret
287  %r = call double @llvm.vp.reduce.fadd.nxv2f64(double %s, <vscale x 2 x double> %v, <vscale x 2 x i1> %m, i32 %evl)
288  ret double %r
289}
290
291declare double @llvm.vp.reduce.fadd.nxv3f64(double, <vscale x 3 x double>, <vscale x 3 x i1>, i32)
292
293define double @vpreduce_fadd_nxv3f64(double %s, <vscale x 3 x double> %v, <vscale x 3 x i1> %m, i32 zeroext %evl) {
294; CHECK-LABEL: vpreduce_fadd_nxv3f64:
295; CHECK:       # %bb.0:
296; CHECK-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
297; CHECK-NEXT:    vfmv.s.f v12, fa0
298; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, ma
299; CHECK-NEXT:    vfredusum.vs v12, v8, v12, v0.t
300; CHECK-NEXT:    vfmv.f.s fa0, v12
301; CHECK-NEXT:    ret
302  %r = call reassoc double @llvm.vp.reduce.fadd.nxv3f64(double %s, <vscale x 3 x double> %v, <vscale x 3 x i1> %m, i32 %evl)
303  ret double %r
304}
305
306define double @vpreduce_ord_fadd_nxv3f64(double %s, <vscale x 3 x double> %v, <vscale x 3 x i1> %m, i32 zeroext %evl) {
307; CHECK-LABEL: vpreduce_ord_fadd_nxv3f64:
308; CHECK:       # %bb.0:
309; CHECK-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
310; CHECK-NEXT:    vfmv.s.f v12, fa0
311; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, ma
312; CHECK-NEXT:    vfredosum.vs v12, v8, v12, v0.t
313; CHECK-NEXT:    vfmv.f.s fa0, v12
314; CHECK-NEXT:    ret
315  %r = call double @llvm.vp.reduce.fadd.nxv3f64(double %s, <vscale x 3 x double> %v, <vscale x 3 x i1> %m, i32 %evl)
316  ret double %r
317}
318
319declare double @llvm.vp.reduce.fadd.nxv4f64(double, <vscale x 4 x double>, <vscale x 4 x i1>, i32)
320
321define double @vpreduce_fadd_nxv4f64(double %s, <vscale x 4 x double> %v, <vscale x 4 x i1> %m, i32 zeroext %evl) {
322; CHECK-LABEL: vpreduce_fadd_nxv4f64:
323; CHECK:       # %bb.0:
324; CHECK-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
325; CHECK-NEXT:    vfmv.s.f v12, fa0
326; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, ma
327; CHECK-NEXT:    vfredusum.vs v12, v8, v12, v0.t
328; CHECK-NEXT:    vfmv.f.s fa0, v12
329; CHECK-NEXT:    ret
330  %r = call reassoc double @llvm.vp.reduce.fadd.nxv4f64(double %s, <vscale x 4 x double> %v, <vscale x 4 x i1> %m, i32 %evl)
331  ret double %r
332}
333
334define double @vpreduce_ord_fadd_nxv4f64(double %s, <vscale x 4 x double> %v, <vscale x 4 x i1> %m, i32 zeroext %evl) {
335; CHECK-LABEL: vpreduce_ord_fadd_nxv4f64:
336; CHECK:       # %bb.0:
337; CHECK-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
338; CHECK-NEXT:    vfmv.s.f v12, fa0
339; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, ma
340; CHECK-NEXT:    vfredosum.vs v12, v8, v12, v0.t
341; CHECK-NEXT:    vfmv.f.s fa0, v12
342; CHECK-NEXT:    ret
343  %r = call double @llvm.vp.reduce.fadd.nxv4f64(double %s, <vscale x 4 x double> %v, <vscale x 4 x i1> %m, i32 %evl)
344  ret double %r
345}
346
347define float @vreduce_fminimum_nxv4f32(float %start, <vscale x 4 x float> %val, <vscale x 4 x i1> %m, i32 zeroext %evl) {
348; CHECK-LABEL: vreduce_fminimum_nxv4f32:
349; CHECK:       # %bb.0:
350; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
351; CHECK-NEXT:    vfmv.s.f v10, fa0
352; CHECK-NEXT:    feq.s a1, fa0, fa0
353; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma
354; CHECK-NEXT:    vfredmin.vs v10, v8, v10, v0.t
355; CHECK-NEXT:    vmfne.vv v11, v8, v8, v0.t
356; CHECK-NEXT:    vcpop.m a0, v11, v0.t
357; CHECK-NEXT:    xori a1, a1, 1
358; CHECK-NEXT:    or a0, a0, a1
359; CHECK-NEXT:    beqz a0, .LBB22_2
360; CHECK-NEXT:  # %bb.1:
361; CHECK-NEXT:    lui a0, 523264
362; CHECK-NEXT:    fmv.w.x fa0, a0
363; CHECK-NEXT:    ret
364; CHECK-NEXT:  .LBB22_2:
365; CHECK-NEXT:    vfmv.f.s fa0, v10
366; CHECK-NEXT:    ret
367  %s = call float @llvm.vp.reduce.fminimum.nxv4f32(float %start, <vscale x 4 x float> %val, <vscale x 4 x i1> %m, i32 %evl)
368  ret float %s
369}
370
371define float @vreduce_fmaximum_nxv4f32(float %start, <vscale x 4 x float> %val, <vscale x 4 x i1> %m, i32 zeroext %evl) {
372; CHECK-LABEL: vreduce_fmaximum_nxv4f32:
373; CHECK:       # %bb.0:
374; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
375; CHECK-NEXT:    vfmv.s.f v10, fa0
376; CHECK-NEXT:    feq.s a1, fa0, fa0
377; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma
378; CHECK-NEXT:    vfredmax.vs v10, v8, v10, v0.t
379; CHECK-NEXT:    vmfne.vv v11, v8, v8, v0.t
380; CHECK-NEXT:    vcpop.m a0, v11, v0.t
381; CHECK-NEXT:    xori a1, a1, 1
382; CHECK-NEXT:    or a0, a0, a1
383; CHECK-NEXT:    beqz a0, .LBB23_2
384; CHECK-NEXT:  # %bb.1:
385; CHECK-NEXT:    lui a0, 523264
386; CHECK-NEXT:    fmv.w.x fa0, a0
387; CHECK-NEXT:    ret
388; CHECK-NEXT:  .LBB23_2:
389; CHECK-NEXT:    vfmv.f.s fa0, v10
390; CHECK-NEXT:    ret
391  %s = call float @llvm.vp.reduce.fmaximum.nxv4f32(float %start, <vscale x 4 x float> %val, <vscale x 4 x i1> %m, i32 %evl)
392  ret float %s
393}
394
395define float @vreduce_fminimum_nnan_nxv4f32(float %start, <vscale x 4 x float> %val, <vscale x 4 x i1> %m, i32 zeroext %evl) {
396; CHECK-LABEL: vreduce_fminimum_nnan_nxv4f32:
397; CHECK:       # %bb.0:
398; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
399; CHECK-NEXT:    vfmv.s.f v10, fa0
400; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma
401; CHECK-NEXT:    vfredmin.vs v10, v8, v10, v0.t
402; CHECK-NEXT:    vfmv.f.s fa0, v10
403; CHECK-NEXT:    ret
404  %s = call nnan float @llvm.vp.reduce.fminimum.nxv4f32(float %start, <vscale x 4 x float> %val, <vscale x 4 x i1> %m, i32 %evl)
405  ret float %s
406}
407
408define float @vreduce_fmaximum_nnan_nxv4f32(float %start, <vscale x 4 x float> %val, <vscale x 4 x i1> %m, i32 zeroext %evl) {
409; CHECK-LABEL: vreduce_fmaximum_nnan_nxv4f32:
410; CHECK:       # %bb.0:
411; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
412; CHECK-NEXT:    vfmv.s.f v10, fa0
413; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma
414; CHECK-NEXT:    vfredmax.vs v10, v8, v10, v0.t
415; CHECK-NEXT:    vfmv.f.s fa0, v10
416; CHECK-NEXT:    ret
417  %s = call nnan float @llvm.vp.reduce.fmaximum.nxv4f32(float %start, <vscale x 4 x float> %val, <vscale x 4 x i1> %m, i32 %evl)
418  ret float %s
419}
420
421define float @vreduce_fminimum_v4f32(float %start, <4 x float> %val, <4 x i1> %m, i32 zeroext %evl) {
422; CHECK-LABEL: vreduce_fminimum_v4f32:
423; CHECK:       # %bb.0:
424; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
425; CHECK-NEXT:    vfmv.s.f v9, fa0
426; CHECK-NEXT:    feq.s a1, fa0, fa0
427; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma
428; CHECK-NEXT:    vfredmin.vs v9, v8, v9, v0.t
429; CHECK-NEXT:    vmfne.vv v8, v8, v8, v0.t
430; CHECK-NEXT:    vcpop.m a0, v8, v0.t
431; CHECK-NEXT:    xori a1, a1, 1
432; CHECK-NEXT:    or a0, a0, a1
433; CHECK-NEXT:    beqz a0, .LBB26_2
434; CHECK-NEXT:  # %bb.1:
435; CHECK-NEXT:    lui a0, 523264
436; CHECK-NEXT:    fmv.w.x fa0, a0
437; CHECK-NEXT:    ret
438; CHECK-NEXT:  .LBB26_2:
439; CHECK-NEXT:    vfmv.f.s fa0, v9
440; CHECK-NEXT:    ret
441  %s = call float @llvm.vp.reduce.fminimum.v4f32(float %start, <4 x float> %val, <4 x i1> %m, i32 %evl)
442  ret float %s
443}
444
445define float @vreduce_fmaximum_v4f32(float %start, <4 x float> %val, <4 x i1> %m, i32 zeroext %evl) {
446; CHECK-LABEL: vreduce_fmaximum_v4f32:
447; CHECK:       # %bb.0:
448; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
449; CHECK-NEXT:    vfmv.s.f v9, fa0
450; CHECK-NEXT:    feq.s a1, fa0, fa0
451; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma
452; CHECK-NEXT:    vfredmax.vs v9, v8, v9, v0.t
453; CHECK-NEXT:    vmfne.vv v8, v8, v8, v0.t
454; CHECK-NEXT:    vcpop.m a0, v8, v0.t
455; CHECK-NEXT:    xori a1, a1, 1
456; CHECK-NEXT:    or a0, a0, a1
457; CHECK-NEXT:    beqz a0, .LBB27_2
458; CHECK-NEXT:  # %bb.1:
459; CHECK-NEXT:    lui a0, 523264
460; CHECK-NEXT:    fmv.w.x fa0, a0
461; CHECK-NEXT:    ret
462; CHECK-NEXT:  .LBB27_2:
463; CHECK-NEXT:    vfmv.f.s fa0, v9
464; CHECK-NEXT:    ret
465  %s = call float @llvm.vp.reduce.fmaximum.v4f32(float %start, <4 x float> %val, <4 x i1> %m, i32 %evl)
466  ret float %s
467}
468