xref: /llvm-project/llvm/test/CodeGen/RISCV/rvv/vpstore.ll (revision b6c0f1bfa79a3a32d841ac5ab1f94c3aee3b5d90) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+zvfbfmin,+v \
3; RUN:     -verify-machineinstrs < %s | FileCheck %s
4; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+zvfbfmin,+v \
5; RUN:     -verify-machineinstrs < %s | FileCheck %s
6; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfhmin,+zvfbfmin,+v \
7; RUN:     -verify-machineinstrs < %s | FileCheck %s
8; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfhmin,+zvfbfmin,+v \
9; RUN:     -verify-machineinstrs < %s | FileCheck %s
10
11declare void @llvm.vp.store.nxv1i8.p0(<vscale x 1 x i8>, ptr, <vscale x 1 x i1>, i32)
12
13define void @vpstore_nxv1i8(<vscale x 1 x i8> %val, ptr %ptr, <vscale x 1 x i1> %m, i32 zeroext %evl) {
14; CHECK-LABEL: vpstore_nxv1i8:
15; CHECK:       # %bb.0:
16; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma
17; CHECK-NEXT:    vse8.v v8, (a0), v0.t
18; CHECK-NEXT:    ret
19  call void @llvm.vp.store.nxv1i8.p0(<vscale x 1 x i8> %val, ptr %ptr, <vscale x 1 x i1> %m, i32 %evl)
20  ret void
21}
22
23declare void @llvm.vp.store.nxv2i8.p0(<vscale x 2 x i8>, ptr, <vscale x 2 x i1>, i32)
24
25define void @vpstore_nxv2i8(<vscale x 2 x i8> %val, ptr %ptr, <vscale x 2 x i1> %m, i32 zeroext %evl) {
26; CHECK-LABEL: vpstore_nxv2i8:
27; CHECK:       # %bb.0:
28; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma
29; CHECK-NEXT:    vse8.v v8, (a0), v0.t
30; CHECK-NEXT:    ret
31  call void @llvm.vp.store.nxv2i8.p0(<vscale x 2 x i8> %val, ptr %ptr, <vscale x 2 x i1> %m, i32 %evl)
32  ret void
33}
34
35declare void @llvm.vp.store.nxv3i8.p0(<vscale x 3 x i8>, ptr, <vscale x 3 x i1>, i32)
36
37define void @vpstore_nxv3i8(<vscale x 3 x i8> %val, ptr %ptr, <vscale x 3 x i1> %m, i32 zeroext %evl) {
38; CHECK-LABEL: vpstore_nxv3i8:
39; CHECK:       # %bb.0:
40; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma
41; CHECK-NEXT:    vse8.v v8, (a0), v0.t
42; CHECK-NEXT:    ret
43  call void @llvm.vp.store.nxv3i8.p0(<vscale x 3 x i8> %val, ptr %ptr, <vscale x 3 x i1> %m, i32 %evl)
44  ret void
45}
46
47declare void @llvm.vp.store.nxv4i8.p0(<vscale x 4 x i8>, ptr, <vscale x 4 x i1>, i32)
48
49define void @vpstore_nxv4i8(<vscale x 4 x i8> %val, ptr %ptr, <vscale x 4 x i1> %m, i32 zeroext %evl) {
50; CHECK-LABEL: vpstore_nxv4i8:
51; CHECK:       # %bb.0:
52; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma
53; CHECK-NEXT:    vse8.v v8, (a0), v0.t
54; CHECK-NEXT:    ret
55  call void @llvm.vp.store.nxv4i8.p0(<vscale x 4 x i8> %val, ptr %ptr, <vscale x 4 x i1> %m, i32 %evl)
56  ret void
57}
58
59declare void @llvm.vp.store.nxv8i8.p0(<vscale x 8 x i8>, ptr, <vscale x 8 x i1>, i32)
60
61define void @vpstore_nxv8i8(<vscale x 8 x i8> %val, ptr %ptr, <vscale x 8 x i1> %m, i32 zeroext %evl) {
62; CHECK-LABEL: vpstore_nxv8i8:
63; CHECK:       # %bb.0:
64; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma
65; CHECK-NEXT:    vse8.v v8, (a0), v0.t
66; CHECK-NEXT:    ret
67  call void @llvm.vp.store.nxv8i8.p0(<vscale x 8 x i8> %val, ptr %ptr, <vscale x 8 x i1> %m, i32 %evl)
68  ret void
69}
70
71declare void @llvm.vp.store.nxv1i16.p0(<vscale x 1 x i16>, ptr, <vscale x 1 x i1>, i32)
72
73define void @vpstore_nxv1i16(<vscale x 1 x i16> %val, ptr %ptr, <vscale x 1 x i1> %m, i32 zeroext %evl) {
74; CHECK-LABEL: vpstore_nxv1i16:
75; CHECK:       # %bb.0:
76; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
77; CHECK-NEXT:    vse16.v v8, (a0), v0.t
78; CHECK-NEXT:    ret
79  call void @llvm.vp.store.nxv1i16.p0(<vscale x 1 x i16> %val, ptr %ptr, <vscale x 1 x i1> %m, i32 %evl)
80  ret void
81}
82
83declare void @llvm.vp.store.nxv2i16.p0(<vscale x 2 x i16>, ptr, <vscale x 2 x i1>, i32)
84
85define void @vpstore_nxv2i16(<vscale x 2 x i16> %val, ptr %ptr, <vscale x 2 x i1> %m, i32 zeroext %evl) {
86; CHECK-LABEL: vpstore_nxv2i16:
87; CHECK:       # %bb.0:
88; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
89; CHECK-NEXT:    vse16.v v8, (a0), v0.t
90; CHECK-NEXT:    ret
91  call void @llvm.vp.store.nxv2i16.p0(<vscale x 2 x i16> %val, ptr %ptr, <vscale x 2 x i1> %m, i32 %evl)
92  ret void
93}
94
95declare void @llvm.vp.store.nxv4i16.p0(<vscale x 4 x i16>, ptr, <vscale x 4 x i1>, i32)
96
97define void @vpstore_nxv4i16(<vscale x 4 x i16> %val, ptr %ptr, <vscale x 4 x i1> %m, i32 zeroext %evl) {
98; CHECK-LABEL: vpstore_nxv4i16:
99; CHECK:       # %bb.0:
100; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
101; CHECK-NEXT:    vse16.v v8, (a0), v0.t
102; CHECK-NEXT:    ret
103  call void @llvm.vp.store.nxv4i16.p0(<vscale x 4 x i16> %val, ptr %ptr, <vscale x 4 x i1> %m, i32 %evl)
104  ret void
105}
106
107declare void @llvm.vp.store.nxv8i12.nxv8i12.p0(<vscale x 8 x i12>, <vscale x 8 x i12>*, <vscale x 8 x i1>, i32)
108
109define void @vpstore_nxv8i12(<vscale x 8 x i12> %val, <vscale x 8 x i12>* %ptr, <vscale x 8 x i1> %m, i32 zeroext %evl) {
110; CHECK-LABEL: vpstore_nxv8i12:
111; CHECK:       # %bb.0:
112; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma
113; CHECK-NEXT:    vse16.v v8, (a0), v0.t
114; CHECK-NEXT:    ret
115  call void @llvm.vp.store.nxv8i12.nxv8i12.p0(<vscale x 8 x i12> %val, <vscale x 8 x i12>* %ptr, <vscale x 8 x i1> %m, i32 %evl)
116  ret void
117}
118
119declare void @llvm.vp.store.nxv8i16.p0(<vscale x 8 x i16>, ptr, <vscale x 8 x i1>, i32)
120
121define void @vpstore_nxv8i16(<vscale x 8 x i16> %val, ptr %ptr, <vscale x 8 x i1> %m, i32 zeroext %evl) {
122; CHECK-LABEL: vpstore_nxv8i16:
123; CHECK:       # %bb.0:
124; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma
125; CHECK-NEXT:    vse16.v v8, (a0), v0.t
126; CHECK-NEXT:    ret
127  call void @llvm.vp.store.nxv8i16.p0(<vscale x 8 x i16> %val, ptr %ptr, <vscale x 8 x i1> %m, i32 %evl)
128  ret void
129}
130
131declare void @llvm.vp.store.nxv1i32.p0(<vscale x 1 x i32>, ptr, <vscale x 1 x i1>, i32)
132
133define void @vpstore_nxv1i32(<vscale x 1 x i32> %val, ptr %ptr, <vscale x 1 x i1> %m, i32 zeroext %evl) {
134; CHECK-LABEL: vpstore_nxv1i32:
135; CHECK:       # %bb.0:
136; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma
137; CHECK-NEXT:    vse32.v v8, (a0), v0.t
138; CHECK-NEXT:    ret
139  call void @llvm.vp.store.nxv1i32.p0(<vscale x 1 x i32> %val, ptr %ptr, <vscale x 1 x i1> %m, i32 %evl)
140  ret void
141}
142
143declare void @llvm.vp.store.nxv2i32.p0(<vscale x 2 x i32>, ptr, <vscale x 2 x i1>, i32)
144
145define void @vpstore_nxv2i32(<vscale x 2 x i32> %val, ptr %ptr, <vscale x 2 x i1> %m, i32 zeroext %evl) {
146; CHECK-LABEL: vpstore_nxv2i32:
147; CHECK:       # %bb.0:
148; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma
149; CHECK-NEXT:    vse32.v v8, (a0), v0.t
150; CHECK-NEXT:    ret
151  call void @llvm.vp.store.nxv2i32.p0(<vscale x 2 x i32> %val, ptr %ptr, <vscale x 2 x i1> %m, i32 %evl)
152  ret void
153}
154
155declare void @llvm.vp.store.nxv4i32.p0(<vscale x 4 x i32>, ptr, <vscale x 4 x i1>, i32)
156
157define void @vpstore_nxv4i32(<vscale x 4 x i32> %val, ptr %ptr, <vscale x 4 x i1> %m, i32 zeroext %evl) {
158; CHECK-LABEL: vpstore_nxv4i32:
159; CHECK:       # %bb.0:
160; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma
161; CHECK-NEXT:    vse32.v v8, (a0), v0.t
162; CHECK-NEXT:    ret
163  call void @llvm.vp.store.nxv4i32.p0(<vscale x 4 x i32> %val, ptr %ptr, <vscale x 4 x i1> %m, i32 %evl)
164  ret void
165}
166
167declare void @llvm.vp.store.nxv8i32.p0(<vscale x 8 x i32>, ptr, <vscale x 8 x i1>, i32)
168
169define void @vpstore_nxv8i32(<vscale x 8 x i32> %val, ptr %ptr, <vscale x 8 x i1> %m, i32 zeroext %evl) {
170; CHECK-LABEL: vpstore_nxv8i32:
171; CHECK:       # %bb.0:
172; CHECK-NEXT:    vsetvli zero, a1, e32, m4, ta, ma
173; CHECK-NEXT:    vse32.v v8, (a0), v0.t
174; CHECK-NEXT:    ret
175  call void @llvm.vp.store.nxv8i32.p0(<vscale x 8 x i32> %val, ptr %ptr, <vscale x 8 x i1> %m, i32 %evl)
176  ret void
177}
178
179declare void @llvm.vp.store.nxv1i64.p0(<vscale x 1 x i64>, ptr, <vscale x 1 x i1>, i32)
180
181define void @vpstore_nxv1i64(<vscale x 1 x i64> %val, ptr %ptr, <vscale x 1 x i1> %m, i32 zeroext %evl) {
182; CHECK-LABEL: vpstore_nxv1i64:
183; CHECK:       # %bb.0:
184; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
185; CHECK-NEXT:    vse64.v v8, (a0), v0.t
186; CHECK-NEXT:    ret
187  call void @llvm.vp.store.nxv1i64.p0(<vscale x 1 x i64> %val, ptr %ptr, <vscale x 1 x i1> %m, i32 %evl)
188  ret void
189}
190
191declare void @llvm.vp.store.nxv2i64.p0(<vscale x 2 x i64>, ptr, <vscale x 2 x i1>, i32)
192
193define void @vpstore_nxv2i64(<vscale x 2 x i64> %val, ptr %ptr, <vscale x 2 x i1> %m, i32 zeroext %evl) {
194; CHECK-LABEL: vpstore_nxv2i64:
195; CHECK:       # %bb.0:
196; CHECK-NEXT:    vsetvli zero, a1, e64, m2, ta, ma
197; CHECK-NEXT:    vse64.v v8, (a0), v0.t
198; CHECK-NEXT:    ret
199  call void @llvm.vp.store.nxv2i64.p0(<vscale x 2 x i64> %val, ptr %ptr, <vscale x 2 x i1> %m, i32 %evl)
200  ret void
201}
202
203declare void @llvm.vp.store.nxv4i64.p0(<vscale x 4 x i64>, ptr, <vscale x 4 x i1>, i32)
204
205define void @vpstore_nxv4i64(<vscale x 4 x i64> %val, ptr %ptr, <vscale x 4 x i1> %m, i32 zeroext %evl) {
206; CHECK-LABEL: vpstore_nxv4i64:
207; CHECK:       # %bb.0:
208; CHECK-NEXT:    vsetvli zero, a1, e64, m4, ta, ma
209; CHECK-NEXT:    vse64.v v8, (a0), v0.t
210; CHECK-NEXT:    ret
211  call void @llvm.vp.store.nxv4i64.p0(<vscale x 4 x i64> %val, ptr %ptr, <vscale x 4 x i1> %m, i32 %evl)
212  ret void
213}
214
215declare void @llvm.vp.store.nxv8i64.p0(<vscale x 8 x i64>, ptr, <vscale x 8 x i1>, i32)
216
217define void @vpstore_nxv8i64(<vscale x 8 x i64> %val, ptr %ptr, <vscale x 8 x i1> %m, i32 zeroext %evl) {
218; CHECK-LABEL: vpstore_nxv8i64:
219; CHECK:       # %bb.0:
220; CHECK-NEXT:    vsetvli zero, a1, e64, m8, ta, ma
221; CHECK-NEXT:    vse64.v v8, (a0), v0.t
222; CHECK-NEXT:    ret
223  call void @llvm.vp.store.nxv8i64.p0(<vscale x 8 x i64> %val, ptr %ptr, <vscale x 8 x i1> %m, i32 %evl)
224  ret void
225}
226
227declare void @llvm.vp.store.nxv1bf16.p0(<vscale x 1 x bfloat>, ptr, <vscale x 1 x i1>, i32)
228
229define void @vpstore_nxv1bf16(<vscale x 1 x bfloat> %val, ptr %ptr, <vscale x 1 x i1> %m, i32 zeroext %evl) {
230; CHECK-LABEL: vpstore_nxv1bf16:
231; CHECK:       # %bb.0:
232; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
233; CHECK-NEXT:    vse16.v v8, (a0), v0.t
234; CHECK-NEXT:    ret
235  call void @llvm.vp.store.nxv1bf16.p0(<vscale x 1 x bfloat> %val, ptr %ptr, <vscale x 1 x i1> %m, i32 %evl)
236  ret void
237}
238
239declare void @llvm.vp.store.nxv2bf16.p0(<vscale x 2 x bfloat>, ptr, <vscale x 2 x i1>, i32)
240
241define void @vpstore_nxv2bf16(<vscale x 2 x bfloat> %val, ptr %ptr, <vscale x 2 x i1> %m, i32 zeroext %evl) {
242; CHECK-LABEL: vpstore_nxv2bf16:
243; CHECK:       # %bb.0:
244; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
245; CHECK-NEXT:    vse16.v v8, (a0), v0.t
246; CHECK-NEXT:    ret
247  call void @llvm.vp.store.nxv2bf16.p0(<vscale x 2 x bfloat> %val, ptr %ptr, <vscale x 2 x i1> %m, i32 %evl)
248  ret void
249}
250
251declare void @llvm.vp.store.nxv4bf16.p0(<vscale x 4 x bfloat>, ptr, <vscale x 4 x i1>, i32)
252
253define void @vpstore_nxv4bf16(<vscale x 4 x bfloat> %val, ptr %ptr, <vscale x 4 x i1> %m, i32 zeroext %evl) {
254; CHECK-LABEL: vpstore_nxv4bf16:
255; CHECK:       # %bb.0:
256; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
257; CHECK-NEXT:    vse16.v v8, (a0), v0.t
258; CHECK-NEXT:    ret
259  call void @llvm.vp.store.nxv4bf16.p0(<vscale x 4 x bfloat> %val, ptr %ptr, <vscale x 4 x i1> %m, i32 %evl)
260  ret void
261}
262
263declare void @llvm.vp.store.nxv8bf16.p0(<vscale x 8 x bfloat>, ptr, <vscale x 8 x i1>, i32)
264
265define void @vpstore_nxv8bf16(<vscale x 8 x bfloat> %val, ptr %ptr, <vscale x 8 x i1> %m, i32 zeroext %evl) {
266; CHECK-LABEL: vpstore_nxv8bf16:
267; CHECK:       # %bb.0:
268; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma
269; CHECK-NEXT:    vse16.v v8, (a0), v0.t
270; CHECK-NEXT:    ret
271  call void @llvm.vp.store.nxv8bf16.p0(<vscale x 8 x bfloat> %val, ptr %ptr, <vscale x 8 x i1> %m, i32 %evl)
272  ret void
273}
274
275declare void @llvm.vp.store.nxv1f16.p0(<vscale x 1 x half>, ptr, <vscale x 1 x i1>, i32)
276
277define void @vpstore_nxv1f16(<vscale x 1 x half> %val, ptr %ptr, <vscale x 1 x i1> %m, i32 zeroext %evl) {
278; CHECK-LABEL: vpstore_nxv1f16:
279; CHECK:       # %bb.0:
280; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
281; CHECK-NEXT:    vse16.v v8, (a0), v0.t
282; CHECK-NEXT:    ret
283  call void @llvm.vp.store.nxv1f16.p0(<vscale x 1 x half> %val, ptr %ptr, <vscale x 1 x i1> %m, i32 %evl)
284  ret void
285}
286
287declare void @llvm.vp.store.nxv2f16.p0(<vscale x 2 x half>, ptr, <vscale x 2 x i1>, i32)
288
289define void @vpstore_nxv2f16(<vscale x 2 x half> %val, ptr %ptr, <vscale x 2 x i1> %m, i32 zeroext %evl) {
290; CHECK-LABEL: vpstore_nxv2f16:
291; CHECK:       # %bb.0:
292; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
293; CHECK-NEXT:    vse16.v v8, (a0), v0.t
294; CHECK-NEXT:    ret
295  call void @llvm.vp.store.nxv2f16.p0(<vscale x 2 x half> %val, ptr %ptr, <vscale x 2 x i1> %m, i32 %evl)
296  ret void
297}
298
299declare void @llvm.vp.store.nxv4f16.p0(<vscale x 4 x half>, ptr, <vscale x 4 x i1>, i32)
300
301define void @vpstore_nxv4f16(<vscale x 4 x half> %val, ptr %ptr, <vscale x 4 x i1> %m, i32 zeroext %evl) {
302; CHECK-LABEL: vpstore_nxv4f16:
303; CHECK:       # %bb.0:
304; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
305; CHECK-NEXT:    vse16.v v8, (a0), v0.t
306; CHECK-NEXT:    ret
307  call void @llvm.vp.store.nxv4f16.p0(<vscale x 4 x half> %val, ptr %ptr, <vscale x 4 x i1> %m, i32 %evl)
308  ret void
309}
310
311declare void @llvm.vp.store.nxv8f16.p0(<vscale x 8 x half>, ptr, <vscale x 8 x i1>, i32)
312
313define void @vpstore_nxv8f16(<vscale x 8 x half> %val, ptr %ptr, <vscale x 8 x i1> %m, i32 zeroext %evl) {
314; CHECK-LABEL: vpstore_nxv8f16:
315; CHECK:       # %bb.0:
316; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma
317; CHECK-NEXT:    vse16.v v8, (a0), v0.t
318; CHECK-NEXT:    ret
319  call void @llvm.vp.store.nxv8f16.p0(<vscale x 8 x half> %val, ptr %ptr, <vscale x 8 x i1> %m, i32 %evl)
320  ret void
321}
322
323declare void @llvm.vp.store.nxv1f32.p0(<vscale x 1 x float>, ptr, <vscale x 1 x i1>, i32)
324
325define void @vpstore_nxv1f32(<vscale x 1 x float> %val, ptr %ptr, <vscale x 1 x i1> %m, i32 zeroext %evl) {
326; CHECK-LABEL: vpstore_nxv1f32:
327; CHECK:       # %bb.0:
328; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma
329; CHECK-NEXT:    vse32.v v8, (a0), v0.t
330; CHECK-NEXT:    ret
331  call void @llvm.vp.store.nxv1f32.p0(<vscale x 1 x float> %val, ptr %ptr, <vscale x 1 x i1> %m, i32 %evl)
332  ret void
333}
334
335declare void @llvm.vp.store.nxv2f32.p0(<vscale x 2 x float>, ptr, <vscale x 2 x i1>, i32)
336
337define void @vpstore_nxv2f32(<vscale x 2 x float> %val, ptr %ptr, <vscale x 2 x i1> %m, i32 zeroext %evl) {
338; CHECK-LABEL: vpstore_nxv2f32:
339; CHECK:       # %bb.0:
340; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma
341; CHECK-NEXT:    vse32.v v8, (a0), v0.t
342; CHECK-NEXT:    ret
343  call void @llvm.vp.store.nxv2f32.p0(<vscale x 2 x float> %val, ptr %ptr, <vscale x 2 x i1> %m, i32 %evl)
344  ret void
345}
346
347declare void @llvm.vp.store.nxv4f32.p0(<vscale x 4 x float>, ptr, <vscale x 4 x i1>, i32)
348
349define void @vpstore_nxv4f32(<vscale x 4 x float> %val, ptr %ptr, <vscale x 4 x i1> %m, i32 zeroext %evl) {
350; CHECK-LABEL: vpstore_nxv4f32:
351; CHECK:       # %bb.0:
352; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma
353; CHECK-NEXT:    vse32.v v8, (a0), v0.t
354; CHECK-NEXT:    ret
355  call void @llvm.vp.store.nxv4f32.p0(<vscale x 4 x float> %val, ptr %ptr, <vscale x 4 x i1> %m, i32 %evl)
356  ret void
357}
358
359declare void @llvm.vp.store.nxv8f32.p0(<vscale x 8 x float>, ptr, <vscale x 8 x i1>, i32)
360
361define void @vpstore_nxv8f32(<vscale x 8 x float> %val, ptr %ptr, <vscale x 8 x i1> %m, i32 zeroext %evl) {
362; CHECK-LABEL: vpstore_nxv8f32:
363; CHECK:       # %bb.0:
364; CHECK-NEXT:    vsetvli zero, a1, e32, m4, ta, ma
365; CHECK-NEXT:    vse32.v v8, (a0), v0.t
366; CHECK-NEXT:    ret
367  call void @llvm.vp.store.nxv8f32.p0(<vscale x 8 x float> %val, ptr %ptr, <vscale x 8 x i1> %m, i32 %evl)
368  ret void
369}
370
371declare void @llvm.vp.store.nxv1f64.p0(<vscale x 1 x double>, ptr, <vscale x 1 x i1>, i32)
372
373define void @vpstore_nxv1f64(<vscale x 1 x double> %val, ptr %ptr, <vscale x 1 x i1> %m, i32 zeroext %evl) {
374; CHECK-LABEL: vpstore_nxv1f64:
375; CHECK:       # %bb.0:
376; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
377; CHECK-NEXT:    vse64.v v8, (a0), v0.t
378; CHECK-NEXT:    ret
379  call void @llvm.vp.store.nxv1f64.p0(<vscale x 1 x double> %val, ptr %ptr, <vscale x 1 x i1> %m, i32 %evl)
380  ret void
381}
382
383declare void @llvm.vp.store.nxv2f64.p0(<vscale x 2 x double>, ptr, <vscale x 2 x i1>, i32)
384
385define void @vpstore_nxv2f64(<vscale x 2 x double> %val, ptr %ptr, <vscale x 2 x i1> %m, i32 zeroext %evl) {
386; CHECK-LABEL: vpstore_nxv2f64:
387; CHECK:       # %bb.0:
388; CHECK-NEXT:    vsetvli zero, a1, e64, m2, ta, ma
389; CHECK-NEXT:    vse64.v v8, (a0), v0.t
390; CHECK-NEXT:    ret
391  call void @llvm.vp.store.nxv2f64.p0(<vscale x 2 x double> %val, ptr %ptr, <vscale x 2 x i1> %m, i32 %evl)
392  ret void
393}
394
395declare void @llvm.vp.store.nxv4f64.p0(<vscale x 4 x double>, ptr, <vscale x 4 x i1>, i32)
396
397define void @vpstore_nxv4f64(<vscale x 4 x double> %val, ptr %ptr, <vscale x 4 x i1> %m, i32 zeroext %evl) {
398; CHECK-LABEL: vpstore_nxv4f64:
399; CHECK:       # %bb.0:
400; CHECK-NEXT:    vsetvli zero, a1, e64, m4, ta, ma
401; CHECK-NEXT:    vse64.v v8, (a0), v0.t
402; CHECK-NEXT:    ret
403  call void @llvm.vp.store.nxv4f64.p0(<vscale x 4 x double> %val, ptr %ptr, <vscale x 4 x i1> %m, i32 %evl)
404  ret void
405}
406
407declare void @llvm.vp.store.nxv8f64.p0(<vscale x 8 x double>, ptr, <vscale x 8 x i1>, i32)
408
409define void @vpstore_nxv8f64(<vscale x 8 x double> %val, ptr %ptr, <vscale x 8 x i1> %m, i32 zeroext %evl) {
410; CHECK-LABEL: vpstore_nxv8f64:
411; CHECK:       # %bb.0:
412; CHECK-NEXT:    vsetvli zero, a1, e64, m8, ta, ma
413; CHECK-NEXT:    vse64.v v8, (a0), v0.t
414; CHECK-NEXT:    ret
415  call void @llvm.vp.store.nxv8f64.p0(<vscale x 8 x double> %val, ptr %ptr, <vscale x 8 x i1> %m, i32 %evl)
416  ret void
417}
418
419define void @vpstore_nxv1i8_allones_mask(<vscale x 1 x i8> %val, ptr %ptr, i32 zeroext %evl) {
420; CHECK-LABEL: vpstore_nxv1i8_allones_mask:
421; CHECK:       # %bb.0:
422; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma
423; CHECK-NEXT:    vse8.v v8, (a0)
424; CHECK-NEXT:    ret
425  call void @llvm.vp.store.nxv1i8.p0(<vscale x 1 x i8> %val, ptr %ptr, <vscale x 1 x i1> splat (i1 true), i32 %evl)
426  ret void
427}
428
429declare void @llvm.vp.store.nxv16f64.p0(<vscale x 16 x double>, ptr, <vscale x 16 x i1>, i32)
430
431define void @vpstore_nxv16f64(<vscale x 16 x double> %val, ptr %ptr, <vscale x 16 x i1> %m, i32 zeroext %evl) {
432; CHECK-LABEL: vpstore_nxv16f64:
433; CHECK:       # %bb.0:
434; CHECK-NEXT:    csrr a2, vlenb
435; CHECK-NEXT:    mv a3, a1
436; CHECK-NEXT:    bltu a1, a2, .LBB35_2
437; CHECK-NEXT:  # %bb.1:
438; CHECK-NEXT:    mv a3, a2
439; CHECK-NEXT:  .LBB35_2:
440; CHECK-NEXT:    vsetvli zero, a3, e64, m8, ta, ma
441; CHECK-NEXT:    vse64.v v8, (a0), v0.t
442; CHECK-NEXT:    srli a3, a2, 3
443; CHECK-NEXT:    vsetvli a4, zero, e8, mf4, ta, ma
444; CHECK-NEXT:    vslidedown.vx v0, v0, a3
445; CHECK-NEXT:    sub a3, a1, a2
446; CHECK-NEXT:    slli a2, a2, 3
447; CHECK-NEXT:    sltu a1, a1, a3
448; CHECK-NEXT:    addi a1, a1, -1
449; CHECK-NEXT:    and a1, a1, a3
450; CHECK-NEXT:    add a0, a0, a2
451; CHECK-NEXT:    vsetvli zero, a1, e64, m8, ta, ma
452; CHECK-NEXT:    vse64.v v16, (a0), v0.t
453; CHECK-NEXT:    ret
454  call void @llvm.vp.store.nxv16f64.p0(<vscale x 16 x double> %val, ptr %ptr, <vscale x 16 x i1> %m, i32 %evl)
455  ret void
456}
457
458declare void @llvm.vp.store.nxv17f64.p0(<vscale x 17 x double>, ptr, <vscale x 17 x i1>, i32)
459
460; Widen to nxv32f64 then split into 4 x nxv8f64, of which 1 is empty.
461
462define void @vpstore_nxv17f64(<vscale x 17 x double> %val, ptr %ptr, <vscale x 17 x i1> %m, i32 zeroext %evl) {
463; CHECK-LABEL: vpstore_nxv17f64:
464; CHECK:       # %bb.0:
465; CHECK-NEXT:    addi sp, sp, -16
466; CHECK-NEXT:    .cfi_def_cfa_offset 16
467; CHECK-NEXT:    csrr a3, vlenb
468; CHECK-NEXT:    slli a3, a3, 3
469; CHECK-NEXT:    sub sp, sp, a3
470; CHECK-NEXT:    .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
471; CHECK-NEXT:    vsetivli zero, 1, e8, m1, ta, ma
472; CHECK-NEXT:    vmv1r.v v24, v0
473; CHECK-NEXT:    addi a3, sp, 16
474; CHECK-NEXT:    vs8r.v v16, (a3) # Unknown-size Folded Spill
475; CHECK-NEXT:    csrr a3, vlenb
476; CHECK-NEXT:    slli a4, a3, 1
477; CHECK-NEXT:    mv a5, a2
478; CHECK-NEXT:    bltu a2, a4, .LBB36_2
479; CHECK-NEXT:  # %bb.1:
480; CHECK-NEXT:    mv a5, a4
481; CHECK-NEXT:  .LBB36_2:
482; CHECK-NEXT:    mv a6, a5
483; CHECK-NEXT:    bltu a5, a3, .LBB36_4
484; CHECK-NEXT:  # %bb.3:
485; CHECK-NEXT:    mv a6, a3
486; CHECK-NEXT:  .LBB36_4:
487; CHECK-NEXT:    vmv1r.v v0, v24
488; CHECK-NEXT:    vl8re64.v v16, (a0)
489; CHECK-NEXT:    vsetvli zero, a6, e64, m8, ta, ma
490; CHECK-NEXT:    vse64.v v8, (a1), v0.t
491; CHECK-NEXT:    sub a0, a5, a3
492; CHECK-NEXT:    srli a6, a3, 3
493; CHECK-NEXT:    vsetvli a7, zero, e8, mf4, ta, ma
494; CHECK-NEXT:    vslidedown.vx v0, v24, a6
495; CHECK-NEXT:    slli a6, a3, 3
496; CHECK-NEXT:    sub a4, a2, a4
497; CHECK-NEXT:    sltu a5, a5, a0
498; CHECK-NEXT:    add a6, a1, a6
499; CHECK-NEXT:    sltu a2, a2, a4
500; CHECK-NEXT:    addi a5, a5, -1
501; CHECK-NEXT:    addi a2, a2, -1
502; CHECK-NEXT:    and a5, a5, a0
503; CHECK-NEXT:    and a0, a2, a4
504; CHECK-NEXT:    addi a2, sp, 16
505; CHECK-NEXT:    vl8r.v v8, (a2) # Unknown-size Folded Reload
506; CHECK-NEXT:    vsetvli zero, a5, e64, m8, ta, ma
507; CHECK-NEXT:    vse64.v v8, (a6), v0.t
508; CHECK-NEXT:    bltu a0, a3, .LBB36_6
509; CHECK-NEXT:  # %bb.5:
510; CHECK-NEXT:    mv a0, a3
511; CHECK-NEXT:  .LBB36_6:
512; CHECK-NEXT:    slli a2, a3, 4
513; CHECK-NEXT:    srli a3, a3, 2
514; CHECK-NEXT:    vsetvli a4, zero, e8, mf2, ta, ma
515; CHECK-NEXT:    vslidedown.vx v0, v24, a3
516; CHECK-NEXT:    add a1, a1, a2
517; CHECK-NEXT:    vsetvli zero, a0, e64, m8, ta, ma
518; CHECK-NEXT:    vse64.v v16, (a1), v0.t
519; CHECK-NEXT:    csrr a0, vlenb
520; CHECK-NEXT:    slli a0, a0, 3
521; CHECK-NEXT:    add sp, sp, a0
522; CHECK-NEXT:    .cfi_def_cfa sp, 16
523; CHECK-NEXT:    addi sp, sp, 16
524; CHECK-NEXT:    .cfi_def_cfa_offset 0
525; CHECK-NEXT:    ret
526  call void @llvm.vp.store.nxv17f64.p0(<vscale x 17 x double> %val, ptr %ptr, <vscale x 17 x i1> %m, i32 %evl)
527  ret void
528}
529
530define void @vpstore_all_active_nxv8i8(<vscale x 8 x i8> %val, ptr %ptr) {
531; CHECK-LABEL: vpstore_all_active_nxv8i8:
532; CHECK:       # %bb.0:
533; CHECK-NEXT:    vs1r.v v8, (a0)
534; CHECK-NEXT:    ret
535  %vscale = call i32 @llvm.vscale()
536  %evl = mul i32 %vscale, 8
537  call void @llvm.vp.store.nxv8i8.p0(<vscale x 8 x i8> %val, ptr %ptr, <vscale x 8 x i1> splat (i1 true), i32 %evl)
538  ret void
539}
540