xref: /llvm-project/llvm/test/CodeGen/RISCV/rvv/vp-splice-mask-fixed-vectors.ll (revision b6c0f1bfa79a3a32d841ac5ab1f94c3aee3b5d90) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs -riscv-v-vector-bits-min=128 \
3; RUN:   < %s | FileCheck %s
4
5declare <2 x i1> @llvm.experimental.vp.splice.v2i1(<2 x i1>, <2 x i1>, i32, <2 x i1>, i32, i32)
6declare <4 x i1> @llvm.experimental.vp.splice.v4i1(<4 x i1>, <4 x i1>, i32, <4 x i1>, i32, i32)
7declare <8 x i1> @llvm.experimental.vp.splice.v8i1(<8 x i1>, <8 x i1>, i32, <8 x i1>, i32, i32)
8declare <16 x i1> @llvm.experimental.vp.splice.v16i1(<16 x i1>, <16 x i1>, i32, <16 x i1>, i32, i32)
9
10define <2 x i1> @test_vp_splice_v2i1(<2 x i1> %va, <2 x i1> %vb, i32 zeroext %evla, i32 zeroext %evlb) {
11; CHECK-LABEL: test_vp_splice_v2i1:
12; CHECK:       # %bb.0:
13; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma
14; CHECK-NEXT:    vmv1r.v v9, v0
15; CHECK-NEXT:    vmv1r.v v0, v8
16; CHECK-NEXT:    vmv.v.i v8, 0
17; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
18; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, ma
19; CHECK-NEXT:    vmv.v.i v10, 0
20; CHECK-NEXT:    vmv1r.v v0, v9
21; CHECK-NEXT:    vmerge.vim v9, v10, 1, v0
22; CHECK-NEXT:    addi a0, a0, -5
23; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, ma
24; CHECK-NEXT:    vslidedown.vi v9, v9, 5
25; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma
26; CHECK-NEXT:    vslideup.vx v9, v8, a0
27; CHECK-NEXT:    vmsne.vi v0, v9, 0
28; CHECK-NEXT:    ret
29
30  %v = call <2 x i1> @llvm.experimental.vp.splice.v2i1(<2 x i1> %va, <2 x i1> %vb, i32 5, <2 x i1> splat (i1 1), i32 %evla, i32 %evlb)
31  ret <2 x i1> %v
32}
33
34define <2 x i1> @test_vp_splice_v2i1_negative_offset(<2 x i1> %va, <2 x i1> %vb, i32 zeroext %evla, i32 zeroext %evlb) {
35; CHECK-LABEL: test_vp_splice_v2i1_negative_offset:
36; CHECK:       # %bb.0:
37; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma
38; CHECK-NEXT:    vmv1r.v v9, v0
39; CHECK-NEXT:    vmv1r.v v0, v8
40; CHECK-NEXT:    vmv.v.i v8, 0
41; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
42; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, ma
43; CHECK-NEXT:    vmv.v.i v10, 0
44; CHECK-NEXT:    vmv1r.v v0, v9
45; CHECK-NEXT:    vmerge.vim v9, v10, 1, v0
46; CHECK-NEXT:    addi a0, a0, -5
47; CHECK-NEXT:    vsetivli zero, 5, e8, mf8, ta, ma
48; CHECK-NEXT:    vslidedown.vx v9, v9, a0
49; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma
50; CHECK-NEXT:    vslideup.vi v9, v8, 5
51; CHECK-NEXT:    vmsne.vi v0, v9, 0
52; CHECK-NEXT:    ret
53
54  %v = call <2 x i1> @llvm.experimental.vp.splice.v2i1(<2 x i1> %va, <2 x i1> %vb, i32 -5, <2 x i1> splat (i1 1), i32 %evla, i32 %evlb)
55  ret <2 x i1> %v
56}
57
58define <2 x i1> @test_vp_splice_v2i1_masked(<2 x i1> %va, <2 x i1> %vb, <2 x i1> %mask, i32 zeroext %evla, i32 zeroext %evlb) {
59; CHECK-LABEL: test_vp_splice_v2i1_masked:
60; CHECK:       # %bb.0:
61; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma
62; CHECK-NEXT:    vmv1r.v v10, v0
63; CHECK-NEXT:    vmv1r.v v0, v8
64; CHECK-NEXT:    vmv.v.i v8, 0
65; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
66; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, ma
67; CHECK-NEXT:    vmv.v.i v11, 0
68; CHECK-NEXT:    vmv1r.v v0, v10
69; CHECK-NEXT:    vmerge.vim v10, v11, 1, v0
70; CHECK-NEXT:    addi a0, a0, -5
71; CHECK-NEXT:    vmv1r.v v0, v9
72; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, ma
73; CHECK-NEXT:    vslidedown.vi v10, v10, 5, v0.t
74; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, mu
75; CHECK-NEXT:    vslideup.vx v10, v8, a0, v0.t
76; CHECK-NEXT:    vsetvli zero, zero, e8, mf8, ta, ma
77; CHECK-NEXT:    vmsne.vi v0, v10, 0, v0.t
78; CHECK-NEXT:    ret
79  %v = call <2 x i1> @llvm.experimental.vp.splice.v2i1(<2 x i1> %va, <2 x i1> %vb, i32 5, <2 x i1> %mask, i32 %evla, i32 %evlb)
80  ret <2 x i1> %v
81}
82
83define <4 x i1> @test_vp_splice_v4i1(<4 x i1> %va, <4 x i1> %vb, i32 zeroext %evla, i32 zeroext %evlb) {
84; CHECK-LABEL: test_vp_splice_v4i1:
85; CHECK:       # %bb.0:
86; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma
87; CHECK-NEXT:    vmv1r.v v9, v0
88; CHECK-NEXT:    vmv1r.v v0, v8
89; CHECK-NEXT:    vmv.v.i v8, 0
90; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
91; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, ma
92; CHECK-NEXT:    vmv.v.i v10, 0
93; CHECK-NEXT:    vmv1r.v v0, v9
94; CHECK-NEXT:    vmerge.vim v9, v10, 1, v0
95; CHECK-NEXT:    addi a0, a0, -5
96; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, ma
97; CHECK-NEXT:    vslidedown.vi v9, v9, 5
98; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma
99; CHECK-NEXT:    vslideup.vx v9, v8, a0
100; CHECK-NEXT:    vmsne.vi v0, v9, 0
101; CHECK-NEXT:    ret
102
103  %v = call <4 x i1> @llvm.experimental.vp.splice.v4i1(<4 x i1> %va, <4 x i1> %vb, i32 5, <4 x i1> splat (i1 1), i32 %evla, i32 %evlb)
104  ret <4 x i1> %v
105}
106
107define <4 x i1> @test_vp_splice_v4i1_negative_offset(<4 x i1> %va, <4 x i1> %vb, i32 zeroext %evla, i32 zeroext %evlb) {
108; CHECK-LABEL: test_vp_splice_v4i1_negative_offset:
109; CHECK:       # %bb.0:
110; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma
111; CHECK-NEXT:    vmv1r.v v9, v0
112; CHECK-NEXT:    vmv1r.v v0, v8
113; CHECK-NEXT:    vmv.v.i v8, 0
114; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
115; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, ma
116; CHECK-NEXT:    vmv.v.i v10, 0
117; CHECK-NEXT:    vmv1r.v v0, v9
118; CHECK-NEXT:    vmerge.vim v9, v10, 1, v0
119; CHECK-NEXT:    addi a0, a0, -5
120; CHECK-NEXT:    vsetivli zero, 5, e8, mf4, ta, ma
121; CHECK-NEXT:    vslidedown.vx v9, v9, a0
122; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma
123; CHECK-NEXT:    vslideup.vi v9, v8, 5
124; CHECK-NEXT:    vmsne.vi v0, v9, 0
125; CHECK-NEXT:    ret
126
127  %v = call <4 x i1> @llvm.experimental.vp.splice.v4i1(<4 x i1> %va, <4 x i1> %vb, i32 -5, <4 x i1> splat (i1 1), i32 %evla, i32 %evlb)
128  ret <4 x i1> %v
129}
130
131define <4 x i1> @test_vp_splice_v4i1_masked(<4 x i1> %va, <4 x i1> %vb, <4 x i1> %mask, i32 zeroext %evla, i32 zeroext %evlb) {
132; CHECK-LABEL: test_vp_splice_v4i1_masked:
133; CHECK:       # %bb.0:
134; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma
135; CHECK-NEXT:    vmv1r.v v10, v0
136; CHECK-NEXT:    vmv1r.v v0, v8
137; CHECK-NEXT:    vmv.v.i v8, 0
138; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
139; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, ma
140; CHECK-NEXT:    vmv.v.i v11, 0
141; CHECK-NEXT:    vmv1r.v v0, v10
142; CHECK-NEXT:    vmerge.vim v10, v11, 1, v0
143; CHECK-NEXT:    addi a0, a0, -5
144; CHECK-NEXT:    vmv1r.v v0, v9
145; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, ma
146; CHECK-NEXT:    vslidedown.vi v10, v10, 5, v0.t
147; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, mu
148; CHECK-NEXT:    vslideup.vx v10, v8, a0, v0.t
149; CHECK-NEXT:    vsetvli zero, zero, e8, mf4, ta, ma
150; CHECK-NEXT:    vmsne.vi v0, v10, 0, v0.t
151; CHECK-NEXT:    ret
152  %v = call <4 x i1> @llvm.experimental.vp.splice.v4i1(<4 x i1> %va, <4 x i1> %vb, i32 5, <4 x i1> %mask, i32 %evla, i32 %evlb)
153  ret <4 x i1> %v
154}
155
156define <8 x i1> @test_vp_splice_v8i1(<8 x i1> %va, <8 x i1> %vb, i32 zeroext %evla, i32 zeroext %evlb) {
157; CHECK-LABEL: test_vp_splice_v8i1:
158; CHECK:       # %bb.0:
159; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma
160; CHECK-NEXT:    vmv1r.v v9, v0
161; CHECK-NEXT:    vmv1r.v v0, v8
162; CHECK-NEXT:    vmv.v.i v8, 0
163; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
164; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma
165; CHECK-NEXT:    vmv.v.i v10, 0
166; CHECK-NEXT:    vmv1r.v v0, v9
167; CHECK-NEXT:    vmerge.vim v9, v10, 1, v0
168; CHECK-NEXT:    addi a0, a0, -5
169; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma
170; CHECK-NEXT:    vslidedown.vi v9, v9, 5
171; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma
172; CHECK-NEXT:    vslideup.vx v9, v8, a0
173; CHECK-NEXT:    vmsne.vi v0, v9, 0
174; CHECK-NEXT:    ret
175
176  %v = call <8 x i1> @llvm.experimental.vp.splice.v8i1(<8 x i1> %va, <8 x i1> %vb, i32 5, <8 x i1> splat (i1 1), i32 %evla, i32 %evlb)
177  ret <8 x i1> %v
178}
179
180define <8 x i1> @test_vp_splice_v8i1_negative_offset(<8 x i1> %va, <8 x i1> %vb, i32 zeroext %evla, i32 zeroext %evlb) {
181; CHECK-LABEL: test_vp_splice_v8i1_negative_offset:
182; CHECK:       # %bb.0:
183; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma
184; CHECK-NEXT:    vmv1r.v v9, v0
185; CHECK-NEXT:    vmv1r.v v0, v8
186; CHECK-NEXT:    vmv.v.i v8, 0
187; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
188; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma
189; CHECK-NEXT:    vmv.v.i v10, 0
190; CHECK-NEXT:    vmv1r.v v0, v9
191; CHECK-NEXT:    vmerge.vim v9, v10, 1, v0
192; CHECK-NEXT:    addi a0, a0, -5
193; CHECK-NEXT:    vsetivli zero, 5, e8, mf2, ta, ma
194; CHECK-NEXT:    vslidedown.vx v9, v9, a0
195; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma
196; CHECK-NEXT:    vslideup.vi v9, v8, 5
197; CHECK-NEXT:    vmsne.vi v0, v9, 0
198; CHECK-NEXT:    ret
199
200  %v = call <8 x i1> @llvm.experimental.vp.splice.v8i1(<8 x i1> %va, <8 x i1> %vb, i32 -5, <8 x i1> splat (i1 1), i32 %evla, i32 %evlb)
201  ret <8 x i1> %v
202}
203
204define <8 x i1> @test_vp_splice_v8i1_masked(<8 x i1> %va, <8 x i1> %vb, <8 x i1> %mask, i32 zeroext %evla, i32 zeroext %evlb) {
205; CHECK-LABEL: test_vp_splice_v8i1_masked:
206; CHECK:       # %bb.0:
207; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma
208; CHECK-NEXT:    vmv1r.v v10, v0
209; CHECK-NEXT:    vmv1r.v v0, v8
210; CHECK-NEXT:    vmv.v.i v8, 0
211; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
212; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma
213; CHECK-NEXT:    vmv.v.i v11, 0
214; CHECK-NEXT:    vmv1r.v v0, v10
215; CHECK-NEXT:    vmerge.vim v10, v11, 1, v0
216; CHECK-NEXT:    addi a0, a0, -5
217; CHECK-NEXT:    vmv1r.v v0, v9
218; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma
219; CHECK-NEXT:    vslidedown.vi v10, v10, 5, v0.t
220; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, mu
221; CHECK-NEXT:    vslideup.vx v10, v8, a0, v0.t
222; CHECK-NEXT:    vsetvli zero, zero, e8, mf2, ta, ma
223; CHECK-NEXT:    vmsne.vi v0, v10, 0, v0.t
224; CHECK-NEXT:    ret
225  %v = call <8 x i1> @llvm.experimental.vp.splice.v8i1(<8 x i1> %va, <8 x i1> %vb, i32 5, <8 x i1> %mask, i32 %evla, i32 %evlb)
226  ret <8 x i1> %v
227}
228
229define <16 x i1> @test_vp_splice_v16i1(<16 x i1> %va, <16 x i1> %vb, i32 zeroext %evla, i32 zeroext %evlb) {
230; CHECK-LABEL: test_vp_splice_v16i1:
231; CHECK:       # %bb.0:
232; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma
233; CHECK-NEXT:    vmv1r.v v9, v0
234; CHECK-NEXT:    vmv1r.v v0, v8
235; CHECK-NEXT:    vmv.v.i v8, 0
236; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
237; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, ma
238; CHECK-NEXT:    vmv.v.i v10, 0
239; CHECK-NEXT:    vmv1r.v v0, v9
240; CHECK-NEXT:    vmerge.vim v9, v10, 1, v0
241; CHECK-NEXT:    addi a0, a0, -5
242; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, ma
243; CHECK-NEXT:    vslidedown.vi v9, v9, 5
244; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma
245; CHECK-NEXT:    vslideup.vx v9, v8, a0
246; CHECK-NEXT:    vmsne.vi v0, v9, 0
247; CHECK-NEXT:    ret
248
249  %v = call <16 x i1> @llvm.experimental.vp.splice.v16i1(<16 x i1> %va, <16 x i1> %vb, i32 5, <16 x i1> splat (i1 1), i32 %evla, i32 %evlb)
250  ret <16 x i1> %v
251}
252
253define <16 x i1> @test_vp_splice_v16i1_negative_offset(<16 x i1> %va, <16 x i1> %vb, i32 zeroext %evla, i32 zeroext %evlb) {
254; CHECK-LABEL: test_vp_splice_v16i1_negative_offset:
255; CHECK:       # %bb.0:
256; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma
257; CHECK-NEXT:    vmv1r.v v9, v0
258; CHECK-NEXT:    vmv1r.v v0, v8
259; CHECK-NEXT:    vmv.v.i v8, 0
260; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
261; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, ma
262; CHECK-NEXT:    vmv.v.i v10, 0
263; CHECK-NEXT:    vmv1r.v v0, v9
264; CHECK-NEXT:    vmerge.vim v9, v10, 1, v0
265; CHECK-NEXT:    addi a0, a0, -5
266; CHECK-NEXT:    vsetivli zero, 5, e8, m1, ta, ma
267; CHECK-NEXT:    vslidedown.vx v9, v9, a0
268; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma
269; CHECK-NEXT:    vslideup.vi v9, v8, 5
270; CHECK-NEXT:    vmsne.vi v0, v9, 0
271; CHECK-NEXT:    ret
272
273  %v = call <16 x i1> @llvm.experimental.vp.splice.v16i1(<16 x i1> %va, <16 x i1> %vb, i32 -5, <16 x i1> splat (i1 1), i32 %evla, i32 %evlb)
274  ret <16 x i1> %v
275}
276
277define <16 x i1> @test_vp_splice_v16i1_masked(<16 x i1> %va, <16 x i1> %vb, <16 x i1> %mask, i32 zeroext %evla, i32 zeroext %evlb) {
278; CHECK-LABEL: test_vp_splice_v16i1_masked:
279; CHECK:       # %bb.0:
280; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma
281; CHECK-NEXT:    vmv1r.v v10, v0
282; CHECK-NEXT:    vmv1r.v v0, v8
283; CHECK-NEXT:    vmv.v.i v8, 0
284; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
285; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, ma
286; CHECK-NEXT:    vmv.v.i v11, 0
287; CHECK-NEXT:    vmv1r.v v0, v10
288; CHECK-NEXT:    vmerge.vim v10, v11, 1, v0
289; CHECK-NEXT:    addi a0, a0, -5
290; CHECK-NEXT:    vmv1r.v v0, v9
291; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, ma
292; CHECK-NEXT:    vslidedown.vi v10, v10, 5, v0.t
293; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, mu
294; CHECK-NEXT:    vslideup.vx v10, v8, a0, v0.t
295; CHECK-NEXT:    vsetvli zero, zero, e8, m1, ta, ma
296; CHECK-NEXT:    vmsne.vi v0, v10, 0, v0.t
297; CHECK-NEXT:    ret
298  %v = call <16 x i1> @llvm.experimental.vp.splice.v16i1(<16 x i1> %va, <16 x i1> %vb, i32 5, <16 x i1> %mask, i32 %evla, i32 %evlb)
299  ret <16 x i1> %v
300}
301